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Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory

J. Fu1, K. D. Buddharaju, S. H. G. Teo, Chunxiang Zhu1, M. B. Yu*, N. Singh, G. Q. Lo,

N. Balasubramanian, and D. L. Kwong

Institute of Microelectronics, Singapore, 11 Science Park Road, Singapore 117685 1 Also with Silicon Nano Device Lab, ECE Department, National University of Singapore, Singapore, 117576

*Corresponding Author: M. B. Yu, (65)-6770-5755, mingbin@ime.a-star.edu.sg.

Abstract

Trap layer engineered gate-all-around (GAA) silicon nanowire SONOS memory showing excellent device performance is demonstrated for the first time. Nitride and silicon nanocrystal (Si-NC) has have been incorporated as the engineered charge trapping layer. Fast transient memory characteristic is shown owing to the nanowire channel structure. The device with embedded Si-NC achieves even faster higher memory speed and increased window, up to 3.2 V ΔVth shift for 1 μs and 6.25 V memory window. The nanowire based non-volatile SONOS memory is promising for the future high speed and low power NAND-type flash memory application.

Introduction

Conventional NAND-type nonvolatile flash memory

reaches its critical scaling limitations, namely the floating gate capacitance efficiency and retention reliability beyond 50nm [1]. DThe discrete charge-trapping storage, such as SONOS and nanocrystal based devices, have been considered as potential replacement of current floating gate based technology to overcome these issues;, since it isthey are inherently immune to capacitive coupling issue and hence it enables thinner gate stacks utilization. [2]. Meanwhile, the emerging FinFET and Gate-All-Around (GAA) structures promise further device scalability as they offer excellent electrostatic control of the short-channel body [3]. FinFET and GAA silicon nanowire combined with SONOS flash memory have had been reported with improved performance over planar structure device, large effective programming window were observed [4,5].

In order to fully take advantage of the narrow device

structure, and also the more advanced charge-trapping material, this work reports on a memory-cell with GAA vertically stacked twin Si-nanowire (VST Si-NW) body and a kind form of trap layer engineering (TLE) [6], in which a charge storage medium consisting of nitride and silicon nanocrystal (Si-NC) is utilized. Taking advantageThis scheme of trap layer engineering and nanowire structure, enabled fast program/erase speed and wide memory window, is achieved along with excellent device reliability.

Experiments

Fig. 1 describes the integration flow of fabricating GAA SONOS memory-cell. After forming the Si nanowire [7], tunneling oxide, Si3N4 trapping layer and blocking oxide were

deposited. Considering εSiN~7, the equivalent oxide thickness (EOT) of ONO stack is 15nm. Three types of memory devices were studied in this work, as summarized in Table-1. Si nanocrystal was formed using SiH4 as the gas source in LPCVD on Si3N4. AFM image scanned on 1×1 μm2 surface area reveals the formation of Si-NC with a density of 7.5×109

cm-2 [Fig. 2]. Fig. 3 and 4 show the tilted SEM images of two kinds of SiNW SONOS, with and without TLE respectively. The difference between TLE and non-TLE devices is evidently shown by the uniformly distributed nanocrystals. LPCVD of 130nm poly-Si deposition was followed by the gate electrode patterning and etching. Fig. 5 shows tilted view after gate definition. All wafers were underwent ion-implantation (Phosphorus with dose of 30 keV/4×1015 cm-2) for source/drain and gate and dopant activation at 1000ºC for 5s. Standard metallization and sintering were performed to conclude the process.

Results and Discussion

Fig. 6 and 7 exhibits the cross-sectional TEM image of vertically stacked twin nanowires SONOS device with wire diameter of 5nm and surrounding ONO stack (the thickness is 4.5/4.5/8 nm for tunneling oxide, charge trapping and blocking oxide layer). Fig. 8 shows the Id-Vg characteristics for two kinds of SONOS devices (with and without TLE), with Lg~850 nm and diameter~5nm. Similar to previously reported Si-NW FETs [7], the vertically stacked twin Si-nanowire SONOS devices also exhibit excellent transfer characteristics. The SONOS device without Si-NC is relatively superior in terms of subthreshold behavior (75 vs 84 mV/dec), which could be due to a better interface quality between gate stack layers. The sharp subthreshold turn-on and low DIBL (≤30mV/V) with EOT=15 nm represents good short channel effect control for the nanowire structure channel.

FN-injection scheme was used for whole channel program

and erasure by biasing the gate electrode in positive or negative polarities, with channel body and source/drain grounded. The program/erase (P/E) characteristic on TLE SONOS memory is shown in Fig. 9 and 10, for two different wire diameters (5 and 8 nm). All P/E were performed using very low biasing condition ‘6/ -11 V to 11/ -6 V’ applied on the gate. For 5 nm diameter wire device, faster P/E speed can be achieved up to ΔVth=3.2 V at Vp=11 V within 1 μs and at Ve=-10 V within 1 ms. Due to the excessive scaling of channel body into several

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nanometers, the width of potential well in the nanowire channel is reduced [8]. The charges being injected in the channel are pushed closer to the interface, thus thefurther facilitating carrier injection becomes more facilitated and efficientcy in the nanowire structure SONOS. Fig. 11 compares the P/E speed characteristics for different diameter devices. It can be easily found seen that the thinner wire device has much faster speed which is may be attributed to increased greater vertical electrical field strength. It means that the vertical electric field in nanowire structure device is not only related to EOT of gate dielectrics as in planar device, but also associated with the channel body itself. As the wire diameter is decreasesing, in other wordsi.e., the channel body is scalingscaled, the vertical electric field increases and accelerates enhances carriers tunneling [5]. Meanwhile, the energy bandgap widening effect due to quantum mechanism for smaller GAA nanowire Si channel could induce a higher larger amount of tunneling carriers too, because the potential barriers that the charge has to pass overcome is reduced when the conduction band of the channel is lifted up [9]. These effects could enhance aid the electrons tunneling from the body into the trapping layers and hence improves the speed greatly.

The P/E characteristics of SONOS device without TLE

have been characterized in Fig. 12. Comparing the P/E speed of SONOS and TLE SONOS [Fig. 13], with the same nanowire diameter, device with trap layer engineeringTLE exhibits faster larger speed. An enhanced 6.25V P/E window was obtained for TLE SONOS, compared to 4.5V window of SONOS only [Fig. 14]. The enhanced larger memory window speed with in TLE SONOS is due to the increased trap density in the storage layer. The density of trapping center in the trapping layer is a key factor which will influence the memory window and program/erase speed. Large memory window is necessary for developing the multi-level cell technology leading to trend of, multi-level cell for in application to memory operation with more than two -bits operation in a single memory cell. Also, Vth saturation issue is significant can be found significant at larger erasing voltage for nitride SONOSonly devices, which which is because gate gate electrons injection neutralizes the holes tunneling into the nitride and results in a dynamic balance. However, the erase saturation is much relievedmitigated forin TLE SONOS. This could may be explained due to the reason that the Si-NC captures more holes during the carriers tunneled tunneling from the substrate, at the same value of erase voltage. The enlarged threshold voltage shift mitigated saturation issue is benefit advantageous for widening the ΔVth during the window at the erase partcycle. Fig. 15 depicts the band diagrams of the two devices when programming voltage is applied. Therefore more charges can be trapped Ffor TLE SONOS device, is more charges can be trapped due to the separately grown Si-NC, and the conduction band offset between Si and SiN. leads to more electrons being trapped . The additive Si nanocrystals can effectively increase the trap density in the trapping layer, but it does not affect the device scaling. Since the separately distributed Si nanocrystals do not sacrifice the EOT of single device, which it is a better substitution to than increasing the thickness of nitride.

The data retention characteristics of the two types of SONOS are shown in Fig. 16. Both devices display good retention properties as ΔVth can be well maintained up to ~104s without memory window degradation being observed. The relatively thick blocking oxide is part of the reason for this excellent retention property for the nanowire device. It could also be attriubuted to the lower possibility of stored charge tunneling back to the channel due to the lifted, higher level ground state energy. The memory device with trap layer engineeringTLE has been shown with to provide improved operating speeds but without compromising reliability behavior. Fig. 17 shows endurance characteristics of TLE and non-TLE SONOS device. The It can be seem thatdevice with TLE also shows the advantage of better endurance properties, as can be seen,with smaller Vth shift upon cycling than non-TLE device.

For Si-NC growing on tunnel oxide (wafer 3), small Vth

shift is obtained as shown in Fig. 18. Such small memory window could be due to the Si-NC density is being lower than 1011 to- 1012 cm-2 which is a propera suitable value for application of using only nanocrystalsnanocrystal only, as trap storage medium [10].

Conclusion

GAA vertically stacked twin Si-nanowire SONOS memory has been integrated with trap layer engineered by incorporating Si nanocrystal. Our results exhibit the advanced memory characteristics of the thinner wires structure device with the trap layer engineering, achieving faster P/E speed, wider memory window without trade-off in retention and endurance properties. The nanowire SONOS non-volatile memory with trap layer engineering is promising in future high performance and low voltage and multi level cell application field.

References

[1] J. D. Lee, et al. “Effects of floating-gate interference on NAND flash memory cell operation,” IEEE Electron Device Lett., vol. 23, No. 5, 2002, pp. 264-266, 2002.

[2] S. K. Samanta, et al, “Enhancement of memory window in short channel non-volatile memory devices using double layer tungsten nanocrystals,” in IEDM Tech. Dig., pp. 170-173, 2005.

[3] K. H. Yeo, et al, “Gate-All-Around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires,” in IEDM Tech. Dig., pp. 539-542, 2006.

[4] P. Xuan, et al., “FinFET SONOS flash memory for embedded applications ,” in IEDM Tech. Dig., pp. 609-612, 2003.

[5] S. D. Suk, et al., “Gate-all-around twin silicon nanowire SONOS memory,” in Symp. on VLSI Tech., pp. 142-143, 2007.

[6] Y. J. Ahn et al., “Trap layer engineering FinFET NAND flash with enhanced memory window,” in Symp. on VLSI Tech., p. 88, 2006.

[7] N. Singh et al., “Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance,” in IEDM Tech. Dig., p. 547-560, 2006.

[8] L. Chang, et al., “Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs,” in IEDM Tech. Dig., pp. 5.2.1 - 5.2.4, 1980.

[9] H. J. Lee, et al., “A nanowire transistor for high performance logic and terabit non-volatile memory devices,” in Symp. on VLSI Tech., pp. 144-145, 2007.

[10] S. Tiwari et al., “Volatile and non-volatile memories with nano-crystal storage,” in IEDM Tech. Dig., p. 521-524, 1995.

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Table-1: Fabricated device structures differ in dielectric layer stack. Experimental designs of trap layer

engineering (TLE) are highlighted for wafer 1.

Layer stack wafer 1

TLE SONOS wafer 2 SONOS

wafer 3 NC on SiO2

SiO2 (blocking oxide) √ √ √

Si-NC √ √

Nitride √ √

SiO2 (tunnel oxide) √ √ √

Fig. 1. Process flow of device fabrication for

vertically Stacked Twin Si nanowire

(VST-SiNW) SONOS.

Fig. 2. AFM image of NC formed on Si3N4. The

scanned size is 1x1 μm2. The dots density is

7.5x109cm-2.

Fig. 3. Tilted top view SEM image of twin

nanowires of 1μm wire length after Si NC

formation on silicon nitride for TLE device.

Fig. 4. Tilted top view SEM image of 0.5μm long

nanowire without Si-NC formation for non-TLE

device.

Fig. 5. Tilted top view SEM image of isolated

TLE SONOS single device after gate electrode

formed.

Fig. 6. TEM image of VST SiNW. The two Si

nanowires with surrounding ONO stack in

poly-Si can be clearly seen.

Fig. 7. Cross-sectional TEM image of single

wire. Diameter of wire is 5 nm and thickness of

ONO stack is 4.5/4.5/8 nm.

Fig. 8. Id-Vg characteristics for diameter 5 nm

and gate length 850 nm nanowire devices, with

TLE and without TLE.

Fig. 9. Programming characteristics using FN tunneling mechanism of TLE SONOS memory device

with diameter 5 nm and 8 nm. The wire with smaller diameter shows much faster program speed.

10-7 10-6 10-5 10-4 10-3 10-2

0

1

2

3

4

58nm dia TLE SONOS

Vth (V

)

Time (s)

6V 7V 8V 9V 10V 11V

VST-Si nanowire formation

Gate patterning and etching

Sintering at 420ºC, 30min, 10%H2

Gate electrode definition

Implantation and dopant activation

Contact etch and metallization

ONO and TLE ONO deposition

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.010-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

5nm dia Si-NW

Vd=0.05V

Vd=1.2V

I d (μA

)

Vg (V)

TLE SONOS (ss=84mV/dec, DIBL=26mV/V)

SONOS (ss=75mV/dec, DIBL=15mV/V)

10-7 10-6 10-5 10-4 10-3 10-2

0

1

2

3

4

5

V th (V

)

Time (s)

6V 7V 8V 9V 10V 11V

5nm dia TLE SONOS

Top NW

Bottom NW

Top NW

Bottom NW

81

Fig. 10. Erasing characteristics of TLE SONOS memory device with diameter 5 nm and 8 nm. The

results also show faster erasing speed of device with smaller nanowire diameter.

Fig. 11. ΔVth shift comparison in terms of

different wire diameter at Vp=9V and Ve=-10V.

Fig. 12. Programming and Erasing characteristics of non-TLE SONOS memory device with 5 nm wire

diameter and 850 nm gate length.

Fig. 13. ΔVth shift comparison for SONOS and

TLE SONOS. TLE device exhibits faster speed

and allievated erasure saturation problem.

(a)

(b) Fig. 14. Id-Vg at programmed and erased states.

TLE shows enhanced P/E capability with larger

P/E window.

Fig. 15. Band diagrams of the two kinds of devices (a) SONOS without TLE, (b) TLE SONOS when

program voltage is applied. For TLE SONOS device, more charge can be trapped due to embedded

Si-NC.

Fig. 16. Data retention characterisctics. ΔVth is

almost maintained up to 104 second for both w

and w/o TLE SONOS (wire diameter=5nm).

Fig. 17. Endurance characteristics up to 104

cycles for SONOS and TLE SONOS (wire

diameter=5nm).

Fig. 18. Programming and Erasing characteristics

for wafer 3 memory device with wire diameter 5

nm.

-2 0 2 4 610-4

10-3

10-2

10-1

100

PGM4.5V

I dLin (μ

A)

Vg (V)

TLE SONOS SONOS

6.25V

dia=5nm

ERS

10-7 10-6 10-5 10-4 10-3 10-2-4

-3

-2

-1

0

1

2

3

4

Open: Erase, Ve=-10V

Δ V

th (V

)

Time (s)

dia=5nm dia=8nm

Solid: Program, Vp=9V

10-7 10-6 10-5 10-4 10-3 10-2-1

0

1

2

35nm dia SONOS w/o TLE

Vth (V

)

Time (s)

-6V -7V -8V -9V -10V -11V

10-7 10-6 10-5 10-4 10-3 10-2

0

1

2

3

4

55nm dia SONOS w/o TLE

Vth (V

)

Time (s)

6V 7V 8V 9V 10V 11V

10-7 10-6 10-5 10-4 10-3

-4

-2

0

2

4

Time (s)

Δ V th

(V)

Solid: Program, Vp=10V

Open: Erase, Ve= -10V

TLE SONOS SONOS

100 101 102 103 104-2

-1

0

1

2

3

V th (V

)

Time (s)

TLE SONOS SONOS

Solid: PGM (Vg=8V, 100μs)Open: ERS (Vg=-9V, 1ms)

10-1 100 101 102 103 1040.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5Solid: PGM Open: ERS

Vth (V

)

Cycle (number)

TLE SONOS(PGM: 9V, 100μs, ERS: -8V, 1ms )

SONOS(PGM: 9V, 400μs, ERS: -8V, 5ms )

10-7 10-6 10-5 10-4 10-3 10-2-1.0

-0.5

0.0

0.5

1.0

1.58nm dia TLE SONOS

Vth (V

)

Time (s)

-6V -7V -8V -9V -10V

10-7 10-6 10-5 10-4 10-3 10-20.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

10-7 10-6 10-5 10-4 10-30.4

0.6

0.8

1.0

1.2

Vth

(V)

Time (s)

-6V -7V -8V -9V -10V

Wafer 35nm dia

Vth (V

)

Time (s)

6V 7V 8V 9V 10V

10-7 10-6 10-5 10-4 10-3 10-2-1

0

1

2

3

4

5nm dia TLE SONOSV th

(V)

Time (s)

-6V -7V -8V -9V -10V

82