Copyright

by

Floyd L. Dankert

2005

Wireless USB Transmit and Receive Scheme: Clock Recovery Circuitry

by

Floyd L. Dankert, BSEE

Report

Presented to the Faculty of the Graduate School of

The University of Texas at Austin

in Partial Fulfillment

of the Requirements

for the Degree of

Master of Science in Engineering

The University of Texas at Austin

December 2005

Wireless USB Transmit and Receive Scheme: Clock Recovery Circuitry

Approved by Supervising Committee:

iv

Acknowledgements

The author is extremely grateful to Dr. Shawn Searles, at Advanced Micro Devices, for technical discussions and his amazing insight into clock recovery schemes. Additionally, the author would like to thank Dr. Adnan Aziz, at the University of Texas, for his technical advice on wireless transmission schemes. Furthermore, the author would like to thank Dr. Saf Asghar for his technical advice on clock recovery and state-of-the-art wireless transmission schemes. Finally, the author would like to thank his friends and family for all of the support that they have provided throughout my college career.

December 2005

v

Abstract

Wireless USB Transmit and Receive Scheme: Clock Recovery Circuitry

Floyd L. Dankert, MSE

The University of Texas at Austin, 2005

Supervisor: Adnan Aziz

This paper will present the motivations behind and actions taken to create a

wireless device compatible with Universal Serial Bus 2.0 (USB). This device is intended

to be used in portable devices needing a USB link to a host controller, serving as a

replacement for the normal wired transceiver. Integrating a small wireless transceiver

with standard USB 2.0 host, hub, and function controllers in lieu of the standard wired

connection would help to eliminate nests of wires without compromising the usefulness

of the broad range of designs that already conform to the USB specifications. Wireless

mice and keyboards can already be purchased that can connect to USB, but these devices

are all low speed human interface devices. The proposed transceivers would extend this

wireless capability to full-speed and high-speed USB 2.0 protocols; allowing for devices

vi

such as disk drives, digital cameras, and others to connect wirelessly to a PC while still

utilizing the robustness of the USB protocol.

Area and power savings were the two main focal points in implementing this

transceiver. A unique protocol layer was developed for this application to aid the

transmission and reception of various analog USB states. Both digital and analog clock

recovery systems were employed as well as an error correction block to aid in bit error

rate minimization. A simple ROM based CORDIC sine wave generation scheme was

employed for the reference clocks in the local oscillators. Emphasis was placed in the RF

front end to limit the number of discrete components needed to transmit and receive.

Finally, a combination of MatLab, Hspice, and VCS simulations were used to determine

and fine tune operation of both the digital and analog components

This specific paper will focus on what is typically one of the most complicated

aspects, which is the aspect of clock recovery. That is, recovering the phase and

frequency of the transmitted data at the receiver in order to properly recover the data

from the incoming signal. This paper focuses on a straight-forward approach that can be

used to recover both the clock information and the data information in an M-PSK system.

(Though it can quite surely be used in almost any wireless transmission scheme) The

paper will first focus on implanting the scheme with a continuous time approach in order

to realize the corresponding mathematical equations. It will then move on to describe

how this scheme can be realized in a discreet time system. The paper will also include

methods by which be can reduce the sensitivity if the scheme to jitter and skew.

vii

Table of Contents

List of Figures........................................................................................................ ix

List of Tables.......................................................................................................... x

List of Tables.......................................................................................................... x

Chapter 1: Introduction............................................................................................1

1.1 Design Space.............................................................................................1

1.2 Overall Design Problem............................................................................1

1.3 Specific Design Problem...........................................................................3

Chapter 2: Top-Level Architecture..........................................................................6

2.1 Desired Characteristics and Features:....................................................6

2.2 USB 2.0 Requirements...........................................................................7

2.3 Transceiver Requirements.....................................................................8

2.4 Clocking and Wireless Requirements....................................................9

2.5 USB Interface.........................................................................................9

2.6 Top Level Details.................................................................................11

2.7 Transmit and Receive Details..............................................................15

2.8 Clocking Details...................................................................................18

Chapter 3: Clock Recovery Details........................................................................20

3.1 Background.............................................................................................20

3.2 Block Realization of Phase Recovery.....................................................23

3.3 Block Realization of Frame Recovery....................................................25

3.4 Matlab Implementation...........................................................................26

Chapter 4: Power and Area Estimates ...................................................................31

4.1 PLL Area Estimates................................................................................31

4.2 PLL Power Estimates..............................................................................32

4.3 Amplifier Area Estimates .......................................................................33

4.4 Amplifier Power Estimates.....................................................................34

4.5 Overall Power Estimate..........................................................................35

viii

Chapter 5: Project Integration and Conclusion.....................................................36

5.1 Digital USB Interface and Error Correction Circuitry.........................37

5.2 Clock Recovery Mechanism................................................................39

5.3 Low-Noise Amplifier, Power Amplifier, and Antenna.......................40

5.4 Frequency Synthesizer .........................................................................41

5.5 Summary..............................................................................................42

Appendices............................................................................................................ xii

A1 Acronym Definitions.......................................................................... xii

A2 Wireless USB Schematic................................................................... xiii

A3 Test Environment.................................................................................. xiii

A4 Receive Logic .................................................................................... xiv

A4 Transmit Logic.................................................................................... xv

A5 Control Logic..................................................................................... xvi

A6 Data I/O............................................................................................. xvii

A7 Clock Recover Model ...................................................................... xviii

References............................................................................................................ xix

Vita ........................................................................................................................xx

ix

List of Figures

Figure 1: Phasor Diagrams for QPSK Modulation Scheme.................................... 4 Figure 1: System-Level Block Diagram.................................................................. 7 Figure 2: USB Transceiver Details [3] .................................................................. 10 Figure 3: Wireless USB Transceiver Top Level Diagram .................................... 12 Figure 4: Encoder Block Diagram......................................................................... 17 Figure 5: Decoder Block Diagram ........................................................................ 17 Figure 6: Clock Selection Circuitry....................................................................... 18 Figure 7: Reset Detection Circuitry....................................................................... 19 Figure 8: Phase Shifted Signals............................................................................. 21 Figure 9: Simplified Block Diagram of Phase and Data Recovery....................... 23 Figure 10: Block Diagram of Phase and Data Recovery......................................... 25 Figure 11: Matlab Implentation of Clock Recovery................................................ 27 Figure 12: PLL Realization..................................................................................... 28 Figure 13: Scatter Plots of RX and Recovered Signals........................................... 29 Figure 14: Input Data Vs. Recovered Data............................................................. 30 Figure 15: Layout of Generic PLL .......................................................................... 32 Figure 16: Power Measurements of the PLL proper. .............................................. 32 Figure 17: Amplifier Layout ................................................................................... 34 Figure 18: Amplifier Power Estimate...................................................................... 34

x

List of Tables

Table 1: List of possible states...................................................................................... 15

1

Chapter 1: Introduction

1.1 DESIGN SPACE

The design space that this project will be focusing on is the Universal Serial Bus

(USB) 2.0 domain. More specifically, it will focus on the implementation of a wireless

transmit and receive scheme that adheres to all USB 2.0 protocols as defined in the

Universal Serial Bus Specification Revision 1.0. [3] Additional efforts will be made to

incorporate power reduction techniques, increasing the range of products that could

benefit from this solution. Furthermore, efforts will be made to make the device interface

to the host controller as simple as possible so that any future changes to the protocol

would result in a minimal change to the interface.

1.2 OVERALL DESIGN PROBLEM

As with any design, it is important to step back and identify the problem that is

being solved. The problem was first identified when looking at the computer setup in one

of the designer’s houses. The spider web of USB cables running between the CPU box

and peripheral devices had expanded beyond control. The need for a solution quickly

became apparent; a generic wireless USB device that could be substituted for cables.

After doing some preliminary research, it became apparent that a generic wireless USB

solution did not exist in the marketplace. Several questions came to light. First, how

would this device need to function? How would this device be powered? How could this

device be made desirable in the marketplace? What wireless transmission scheme would

2

be best suited for this device? Answering these questions and more is the basis for this

report.

First and foremost, the device needs to adhere to the USB 2.0 protocol [3].

Additionally, the device would need to use a limited amount of power so that it could

either be powered by the USB power bus (ideally) or by a single AA sized lithium ion

battery. Any additional power needs would require a more bulky power supply or wires;

both of which would decrease its popularity in the marketplace.

This device also requires a transmitter, receiver, antenna, clock recovery

mechanism, error correcting scheme, low noise amplifier (LNA), and an algorithm for

sine wave generation. This set of devices would be the minimum required regardless of

the transmission scheme that was used. Once a transmission scheme has been chosen, the

above devices can be designed to best fit the system.

Since this device will be wireless, it needs a modulation scheme and quadrature

phase shift keying (QPSK) will be used for this solution. Why was QPSK chosen as the

modulation scheme over other schemes? The answer is that QPSK offers a good balance

between the number of symbols it can transmit at a time and the modulation complexity

required to implement it. While binary phase shift keying (BPSK) offers a large amount

of distance between the symbols it transmits and is a very simple modulation scheme, it

can only transmit one symbol per period. QPSK, on the other hand, can transmit two

symbols per period with only a slightly more complex modulator, essentially halving the

clock speed needed to transmit a given chunk of data compared with BPSK. There are

other modulation schemes that can transmit more symbols per period, but they come with

added modulator complexity. Also, the frequency reduction achieved by transmitting

three symbols per period compared with two is only 33%, whereas going from one

symbol to two offered a frequency decrease of 50%. The frequency reduction percentage

3

only decreases as more symbols are transmitted per period, while the complexity of the

modulator increases and the distances between distinct symbols decreases. As the

distance between symbols decreases, the probability of channel noise causing a different

symbol than the one transmitted to be received increases. Hence, QPSK was chosen as it

offers an optimal balance between modulation complexities, number of symbols

transmitted per period, and distance between distinct symbols [2].

The design needs an upper level protocol that would adhere to the host controller

specifications. By choosing to implement this in a simple digital controller, the design

can be completed using simple digital building blocks, aiding the speed of design and

validation. In addition, prior to the wire in a current USB transceiver, all of the signals

are digital. By eliminating the wire and utilizing the USB controller’s digital signals, the

use of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) can

be avoided, as can the added complexity that they create. One other advantage to the

digital controller is that it can easily be updated should any future USB protocols require

different specifications, providing a quick path to creating future product iterations.

Each of the above requirements presents a different challenge to the design team.

By attacking these problems from many different angles, solutions were found to each of

these problems that were tailored to best suit the design. Additionally, by providing

innovative and unique solutions to these problems, the design could be marketed as an

attractive solution in the market place.

1.3 SPECIFIC DESIGN PROBLEM

So why do we need to recover the clock at all? Let us try to take an intuitive look

at clock recovery. Say a switch man at a train yard knows that two trains will be arriving

4

a minute apart. One train is scheduled to arrive at 4:00 and the other at 4:01. Each train

will be carrying different cargo and the switch man must direct the train based on the

cargo. Let us also say that a third train will be arriving at 4:03 carrying the same cargo as

train 1. If the switch man does not have a method by which he can synchronize his clock

with the clock on the incoming trains, then it is quite possible that the trains could be

directed the wrong way. This is the idea behind clock recovery. By looking at when the

trains cross a certain point, the train conductor can deduce what the train is carrying.

Even though M-PSK systems (from here on, let us focus on QPSK – Quad Phase

Shift Keying) are fairly tolerant to phase/frequency shifts, it is still important for us to

recover a reference point from the transmitted clock. This way, we will be way to sync

up our receiver clock with the incoming data and our frame boundaries will naturally fall

into place. We can see an illustration of what is actually happening in Figure 1.

(0,0)

(0,1)

(1,0)

(1,1)

(0,0)

(0,1)

(1,0)

(1,1)

(0,0)

(0,1)

(1,0)

(1,1)

Frequency and Phase Drifting Frequency Locked Phase Drifting Frequency and Phase Locked

Figure 1: Phasor Diagrams for QPSK Modulation Scheme

The phasor on the left illustrates what happens when we have drift in frequency

(which can be modeled as being out of phase) and in phase. (If this is compared to our

train analogy, the switch man would have no idea what number of trains there are.) We

5

can see that there is a solid rotation which would result in the data being corrupted. In

the center diagram, we have aligned frequency. (It is very inexpensive to purchase

crystals with a tolerance of 400ppm.) Notice that we now have four clear regions, yet

there is still a rotation to the graph. (Again, if this is compared to our train analogy, the

switch man would now know that there are four trains, but he would have no idea what

the cargo in each train was.) This is due to the phase difference between the TX and the

RX “slipping.” This too will eventually result in the data being corrupted. In the figure

on the right, we have locked on to both the phase and frequency of the TX. (Turning to

our analogy one more time, the switch man would now know that there are four trains

and would be able to discern the cargo of each train.) Although the signal will oscillate

around the axis, we will still be able to recover incoming data without loss. (Ideal)

6

Chapter 2: Top-Level Architecture

2.1 DESIRED CHARACTERISTICS AND FEATURES:

The wireless transceiver serves as an interpreter; translating the outputs of a USB

device into the desired wireless protocol for transmission and performing the opposite

translation during reception. Ideally, the transceiver simply replaces the wired

transceiver utilized in USB 2.0. It bolts onto the USB function, hub, or host controller

with minimal integration. Another solution would allow for the transceiver to simply

plug into the USB receptacles on the host and functional devices. The device supports all

forms of USB transmission, including low, full, and high speed data rates. It utilizes the

power of the USB bus wherever possible to minimize the use of external power sources.

Ideally, the transceiver would support numerous functional devices when attached

to a hub or a host, but this is not a requirement of this first pass system. Each of the

components in this system has its own requirements. Figure 1 details some of the major

sub-blocks of this system. The USB interface is represented by the host controller. The

transceiver contains the digital interface, the error correction blocks, and QPSK blocks.

The clocking block consists of the clock recovery, direct digital frequency synthesizer,

and the phase-locked loops. The wireless block consists of the two power and low noise

amplifiers, filters, and the antenna. The bulleted lists below mention the requirements

briefly, and they will be expanded upon later.

7

Figure 1: System-Level Block Diagram

2.2 USB 2.0 REQUIREMENTS

The list below illustrates the specifications that must be met to enable USB 2.0

[3].

• USB 2.0, including low, full, and high speed data transmission must be supported.

This means data can be transmitted at 1.5 Mb/s, 12 Mb/s, and 480 Mb/s.

• Device connection, disconnection, reset, and suspend should not be impeded by

the wireless protocol.

• All data normally transmitted through a wired USB connection must be supported

through the wireless connection.

• Data high and low values for all speeds (referred to as differential 1, differential 0,

also called J and K states)

8

• Single-ended zero values for all speeds which are used to indicate a reset

condition.

• Chirp J and Chirp K states utilized during reset to reset devices into the high

speed mode

• Squelching of invalid data when in high speed mode

• Device disconnection in high speed mode

• Total delay from USB transmit to USB receive (through the wireless protocol)

cannot exceed the maximum allowable USB cable delay of 30nanoseconds

• Total current consumption of wireless transceiver plus the attached function

controller cannot exceed a current of 200mA drawn from the USB controller.

2.3 TRANSCEIVER REQUIREMENTS

The list below illustrates the requirements of the wireless receiver.

• Must provide some simple error correction.

• Attach easily to the controller portion of the USB device. Must be attached where

the wire would normally attach and support digital controls, allowing it to be

turned off and on by the state of the USB controller.

• Finite state machine that performs the translation from USB to wireless and back.

All of the states mentioned in the USB requirements above must be accounted for.

• Some knowledge of reset is needed to allow for the proper transmission of the

chirp J and chirp K states. A counter will be used to determine how many

consecutive single-ended zero (SE0) states have been received and will indicate a

reset accordingly.

• Two extra bits are used to indicate the start of a transmission packet. This

becomes quite helpful when the packet is received and must be decoded.

9

• Should take care of switching between full speed and high speed transmission

rates. Low speed devices cannot connect as high speed devices but high speed

devices need to connect as full speed before indicating it can utilize high speed

data rates.

2.4 CLOCKING AND WIRELESS REQUIREMENTS

The list below illustrates the clocking and carrier frequency requirements.

• Must support clock synchronization through the wireless channel

• Need to support 1.5 Mb/s 12 Mb/s, and 480 Mb/s transmission rates, as well the

wireless carrier wave, ideally 3.6 GHz.

• If utilizing current state transmission and start/end of packet transmission, clock

speeds of 3 times the various transmission rates must be supported/generated.

• Use some sort of digital frequency synthesis for carrier frequency generation.

Otherwise, use a PLL or off-chip crystal to generate the carrier frequency.

2.5 USB INTERFACE

The USB interface shown in Figure 2 below is taken from the USB 2.0

specification [3] and it was the starting point for interfacing the transceiver with USB.

The transceiver design basically removes the wire and the various resistors, but still has

to look functionally similar to the USB host controller. The USB signals that must be

accounted for are below the figure, and these signals must be accounted for in the

wireless transceiver.

10

Figure 2: USB Transceiver Details [3]

The list below illustrates the signals required in a USB transceiver.

• Rpu_enable – pull up resistor enable. Not needed, as there are no resistors in the

wireless transceiver

• HS_Current_Source_Enable – enables high speed current source of the high speed

transmitter. Used in conjunction with HS_Drive_Enable to indicate high speed

data rates.

• HS_Drive_Enable – signal to enable high speed data transmission

• HS_Data_Drive_Input – High speed data stream for transmission.

• LS/FS_Data_Drive_Input – Low or full speed data stream for transmission

11

• Assert_Single_Ended_Zero – Asserts a single ended zero on the output of the low

or full speed transmitter

• FS_Edge_Mode_Sel – Chooses low speed or full speed data rates for LS/FS

transmitter

• HS_Differential_Receiver_Output – data stream from the receiver during high

speed operation

• Squelch – Utilized during high speed operation to indicate that invalid data has

been received (in wired operation, the data was below the expected differential

thresholds)

• LS/FS_Differential_Receiver_Output – data stream from the receiver during low

or high speed operation

• HS_Disconnect – Utilized during high speed operation to indicate that a device

has been disconnected

• SE_Data+_Receiver_Output – D+ signal used when single-ended data is received

(SE one is not allowed).

• SE_Data-_Reciever_Output – D- signal used when single-ended data is received

(SE one is not allowed).

2.6 TOP LEVEL DETAILS

The top level block diagram of the wireless transceiver in the figure below shares

a substantial portion of the interface with the USB controller as the transceiver shown

above from the USB specifications. This diagram does not include the complex registers

that connect to the ECC blocks. Those registers will be handled later in Figures 4 and 5,

as will all the components in the dotted line box in the bottom-right corner.

12

Figure 3: Wireless USB Transceiver Top Level Diagram

There is a circuit in the upper-left corner of Figure 3 that handles the high-speed

transmission, converting a 1 on the HS_Data_Driver line to 1 on Data+ and 0 on the

Data- terminals, and vice versa if a zero occurs on the same line. There is a similar

circuit that handles low speed and full speed transmission, converting a 1 into a Data+ =

1 and Data- = 0 for a 1 to be transmitted and vice versa for a 0 in full speed mode. The

opposite translation is done if low speed mode. The receiving circuitry to translate the

received data on the Data+ and Data- lines into the correct value to be sent to the host

controller is basically the same as shown in the USB specification transceiver. The only

13

addition is the RxEn gating signal that enables the output of the receiving circuitry only

when a valid packet reception has occurred.

There are a number of signals in the wireless transceiver that are not in the USB

specification transceiver.

• RxEn – Indicates that the receiver and receiver buffer should be enabled. This

occurs when none of the transmitter drivers are enabled by the USB controller.

• TxEn – Indicates that the transmitter and transmission buffer should be enabled.

This occurs when the USB controller indicates that either the HS or LS/FS driver

should be enabled. This also causes deactivation of the receiving circuitry.

• TxReset – Detects a reset state during transmission of 3.0 ms or more of state

SE0. Note that the counters that indicate the duration must have knowledge of the

current transmission speed to accurately detect this 3.0 ms.

• RxReset – Detects a reset state during reception of 2.5 us or more of SE0

• Reset – Indicates a reset state (either transmit reset or receive reset)

• LS_Clock_3x – Clock running at 3x the speed of LS transmission (4.5 MHz)

• FS_Clock_3x – Clock running at 3x the speed of FS transmission (36 MHz)

• HS_Clock_3x – Clock running at 3x the speed of HS transmission (1.44 GHz)

• Clock_3x – Clock running at 3x the speed of the current USB mode clock. This

is chosen based on what speed the USB controller is transmitting with.

• Clock_1x – Clock running at the speed of the current USB mode clock. This is

derived from the Clock_3x signal using a divide by 3 clock divider.

• TxChirp – Indicates that the J or K state being sent is actually a chirp signal, as

the device is in reset.

• RxChirp – Indicates that a chirp has been detected.

14

• RxPacket – Indicates that a packet has been successfully received, due to the

presence of a 1 in both the RX0 and RX1 flops in addition to the receiver being

enabled due to the assertion of RxEn.

Many of the signals in the transceiver are dependent upon the states being

transmitted or received. There are numerous states possible in the USB 2.0 architecture.

In low speed and full speed, there are 2 main states, the J and K state, which correspond

to either 01 or 10 on the Data+ and Data- lines. There is also a single-ended zero state

(SE0), which is denoted by zeros on both data lines. The high-speed state also has J, K,

and SE0 states. Since there are 3 main states for all transmission modes, it makes sense

to use 2 bits to denote the state transmitted. However, the high-speed mode also has

some extraneous states that are possible. When coming out of reset in high speed mode,

the host controller will broadcast chirp J and chirp K states, which in a wired solution

have a larger voltage swing than normal, but in the wireless solution will require an extra

bit to be sent, indicating that the device is chirping. Also in the high-speed state, the

transceiver must also indicate that data was being squelched, or that a device is

disconnecting. Between chirping, squelch, and disconnect, there are an additional three

states that must be accounted for.

To allow for error correction to work without increasing the clock frequency, six

USB transmissions are buffered together before transmission. This means that there are

twelve bits of USB data that need to be transmitted in each packet. To account for the

squelch, disconnect and chirp states, it would seem that there should be an additional 12

bits transmitted to indicate whether any of these states occurred during the transmission

of the USB data. However, since these states are all persistent states, meaning they most

likely occurred for a long string of USB states, only two bits are sent. If a squelch,

15

disconnect, or chirp occurred in any of the six USB transmissions, these bits are set

appropriately. Therefore, each packet will consist of sixteen bits: two header bits to

indicate start of transmission, twelve USB data information bits, and two chirp,

squelch/disconnect bits. The header consists of two consecutive ones, and the rest of the

bits are guaranteed to never repeat that sequence (once the data stream is partitioned for

QPSK modulation). This feature is to help the receiver realize when the start of a packet

occurs.

Below is a list of the possible states, if only one USB bit were packetized (six bits

sent instead of sixteen). The list of possible states for the six USB buffered packet is too

long to list here.

Header D+ D- S/D Chirp Definition

1 1 0 0 0 0 Single-Ended 01 1 1 0 0 0 Differential 11 1 0 1 0 0 Differential 01 1 0 0 1 0 Squelch (invalid range)1 1 0 0 1 1 Disconnect Detected1 1 1 0 0 1 Chirp J State1 1 0 1 0 1 Chirp K State

Table 1: List of possible states

There is a register that will capture these sixteen bits and pass them along to the

ECC block sequentially. The ECC block encodes the sixteen bits using convolutional

coding, and the encoded sequence is passed along to the QPSK transmit block, which

modulates the signal.

2.7 TRANSMIT AND RECEIVE DETAILS

After QPSK modulation, the modulated signal is filtered and sent to the power

amplifier, where only the desired frequency is amplified before being sent to the antenna

16

for transmission. On the receiving side, the encoded packet will pass through a filter, a

low noise amplifier, and then pass through the QPSK demodulator, which passes the

received sequence on to the ECC decoder (Viterbi decoder). The Viterbi decoder will

reconstruct the original packet from the received packet. When the packet is received,

the various bits will be used to create the RxPacket, squelch, disconnect, and data signals,

which will be passed on to the USB controller on the receive side.

Figure 4 focuses on the register shown in the top-level diagram that precedes the

ECC block on the transmit path. This register packetizes the data that needs to be

encoded. There are four six-bit shift registers that capture the information on the Data+,

Data-, S/D, and Chirp lines on the 1x clock. These registers are enabled only when the

device is transmitting, and the various clocks will be discussed later. The outputs of the

data shift registers are fed sequentially to two inputs of a six-input multiplexor. The

logical OR of the outputs of the S/D shift register is sent to another input of the six-input

multiplexor, as is the logical OR of the outputs of the Chirp shift register. The final two

bits of the six-input multiplexor are tied to logic one, and represent the start of packet

information.

There is a small state machine that iterates through which multiplexor input drives

the output to the ECC encoder. This state machine is triggered on rising edges of the 3x

clock, ensuring all eighteen bits (sixteen data bits and two flush bits) are encoded in six

1x clock cycles. The eighteen bit input packet is encoded into a 36 bit packet. The

encoder also partitions the data into two data streams of 18 bits that are sent into the I and

Q inputs of the QPSK modulator.

17

Figure 4: Encoder Block Diagram

Figure 5: Decoder Block Diagram

18

On the receive side, the two outputs of the QPSK demodulator are sent straight to

the Viterbi decoder on the 3x clock. The Viterbi decoder takes these two 18-bit

sequences and decodes them into a single 16-bit sequence that contains all of the original

data. It then sends this data to the USB logic in packets of six bits that look like those

shown in Table 1. Not shown in Figure 5 are the filter and LNA that precede the

demodulator, nor the details of the Viterbi decoder, which is covered later.

2.8 CLOCKING DETAILS

Figure 6: Clock Selection Circuitry

USB 2.0 requires support of three different data speeds: 1.5 Mb/s, 12 Mb/s, and

480 Mb/s (Compaq). For purposes of this project, these are defined as the 1x clocks.

The transmit and receive registers as well as the ECC blocks require a clock that is three

times this frequency. All of these clocks are generated off of the same, high frequency

clock that is synthesized by a phase-locked loop, or PLL. This PLL clock is then divided

down to the 3 possible 3x clock frequencies (4.5 MHz, 36 MHz, and 1.44 GHz). As

portrayed in Figure 6, one system level 3x clock is chosen depending on the mode of

operation, and this system level 3x clock is passed through a divide by three circuit that

creates the system level 1x clock, which is the same speed as the USB data rate.

19

Figure 7: Reset Detection Circuitry

There are two reset conditions defined by the USB specification [3] and a circuit

to detect these conditions is shown in Figure 7. If a device is in transmit mode, and it has

transmitted more than three milliseconds worth of the single-ended zero (SE0) state, the

transceiver needs recognize the reset state. If the device is in the receive mode, and it has

received more than 2.5 microseconds of SE0, then it must realize the transmitting device

is in reset. These two possible reset conditions are detected using counters, based on the

1x clock. If a non-SE0 state occurs, the counters are reset. If the counters reach either 3

ms on the transmit side or 2.5 us on the receive side, then the reset signal is enabled.

20

Chapter 3: Clock Recovery Details

3.1 BACKGROUND

Now that we have established the need for a clock recovery scheme, (Refer back to

our switch man example.) we need to dive into the mathematics in order to find a suitable

solution. In a QPSK system, one of four symbols is transmitted: (1, 1), (-1, -1), (1, -1), (-

1, 1) [2]. This is done by mixing one bit of the symbol with either a sin or a cosine term

and then transmitting the sum of the sin/cosine pair. From that we can see that we will

then need at the receiver a sin/cosine pair of the same frequency and phase in order to

demodulate our data.

The trick here is that we will only have available to us a sum of the sin/cosine pair.

Let’s assume for now though, for ease of illustration, that we are only sending sin( ) or

–sin( ). Using Euler’s identities, we can show that [13]:

[ ])cos()2cos(2

1)sin()sin( θθωωθω ++−=+ ttt

[ ])sin()2sin(2

1)cos()sin( θθωωθω ++=+ ttt

If we integrate over n periods of ω

π2 or -

ω

π2 we can see the following:

1. )cos(2

1 θωπ

n for 1.

21

2. )sin(2

1 θωπ

n for 2.

Notice that we are left with a clear data slice when we are in phase lock. In phase

ω

π

2

n , if sin( ) is transmitted and

ω

π

2

n− , if -

sin( ) is transmitted.

To illustrate this, let’s assume that we have a phase error as shown in the

figure below.

sin( t + 15º)sin( t)

Figure 8: Phase Shifted Signals

22

It is clear that our local RX clock is out of phase with the incoming data by 15º.

Equation 2 above is yielding a positive number, which is in effect, giving us a request to

increase our speed. If we examine the result of 2 more closely, we can see that:

θω

π

2

n≈b So, if we scale the result by

π

ω

n

2 we can get the actual phase error.

One thing to note here is if we are sending –s 2 will return a negative

value, which is a reversal in the error term. To correct this, we can recover the data from

1, and then multiply that by 2 to get the correct sign. This will become clearer in the next

section.

Now we need to ensure that the error in integrating over the high frequency terms

in 1 and 2 proceeding

and following the current bit is of opposite signs.

ωθ

ωπ

ωθ

ωπ

θωω

θω−

−

+−=+∫

2

0

2

02cos(

2

1)2sin( tdtt

ωπ

ωθ

ωπ

ωπ

ωθ

ωπ θω

ωθω

2

2

2

2 2cos(2

1)2sin(

−−

+−−=+−∫ tdtt

0)]cos()cos()cos()[cos(2

1 =−−+−−= θθθθω

As can be seen from the equation above, there is no residual error in the high

frequency term. However, we did introduce an error into the phase term.

]22

)[sin()sin()sin(2

2

2

0 ωθπθθθ ω

π

ωθ

ωπ

ωπ −=− ∫∫ −

dtdt

This error term is a second order error term and will not really affect our system.

Since we will be using a phase lock loop, the system will self correct for this error.

23

3.2 BLOCK REALIZATION OF PHASE RECOVERY

Now that we have the mathematical basis for our design, we can begin to realize

this scheme in hardware. The diagram below represents a simple block diagram for the

system that we have just proven above.

πω

n

2

πω

n

2

sin( t + )

+ 90º

sin( t)

cos( t)

r(t)

sin( t)

cos( t)

sample

data

Figure 9: Simplified Block Diagram of Phase and Data Recovery

–

in the previous section. If we look at what is actually going on, we can directly map this

system to equations 1 and 2.

As r(t) comes into the system, it first is passed through a Low Noise Amplifier.

(This is actually one source of noise.) After some filtering to remove undesired frequency

components, the incoming data is then split into two paths. We perform the convolution

24

we now have the correct absolute value of the phase on the cos path. If we perform an

additional integration on the sin path, we can then recover the data. Using the sign of the

data, we can then get the correct value for the phase offset, which is the sent to the VCO

model to generate the phase correct sin and cos values.

To take this a step further, we could then integrate the phase correction over many

cycles and then feed that value into the VCO. By doing this, we can increase our

immunity to jitter caused by both the transmitter and the channel. What we are doing

here is keeping our VCO from bouncing back and forth over every cycle and instead

taking an average value over many cycles. The beauty of an M-PSK system is that it can

tolerate minor phase offsets, which still may occur. These can be caused by noise from

the LNA, noise from the filters, or even noise injected into the channel. (In this case, the

channel is the air.)

In the QPSK system that we are using for an example, it is also wise to note that

the data will then need to go through a 2X over-sampling in order to make the data

serialized again. (In a sense, this is parallel to serial data conversion.) The following

diagram illustrates the block level implementation of this scheme for QPSK.

25

πω

n

2

πω

n

2

sin( t + )

+ 90º

sin( t)

cos( t)

r(t)

sin( t)

cos( t)

sample

Control Logic=1:2?Sin

Data=2:1?Sin

Data1

2

Figure 10: Block Diagram of Phase and Data Recovery

3.3 BLOCK REALIZATION OF FRAME RECOVERY

Now that we have the recovered the data and the clock from the transmitted

signal, we need to acquire our frame window. If we assume that we are getting random

data sent into the TX, then we can assume that the probabilities of any given symbol over

a sufficiently long period will be equal. If r(t) is the signal at the receiver, then the

following equation can be written [12]:

∫∞

=0

0)( dttr

Therefore if we integrate of a period T where, T >> Frame Size, the following

approximation will hold true [12]:

26

∫ ≈T

dttr0

0)(

If the frame boundary is not aligned, this integral will result in an absolute value

somewhat larger than zero. The frame can then be marched until the integral reaches a

minimum. Once we have found that, we can safely assume that we have aligned our

frame boundary.

Unfortunately, in a real system the integral will not truly reach zero due to a

multitude of reasons, however a minimum can still be found and a proper frame boundary

can be established.

3.4 MATLAB IMPLEMENTATION

After completing the initial calculations, the system was implemented in a very

straightforward approach using Matlab. Matlab was chosen as the simulator because it

provides a very good method by which the mathematical model can be implemented and

tested. The implementation scheme follows the direct realizations shown above. The

following figure is the Simulink model of the system:

27

Figure 11: Matlab Implentation of Clock Recovery

The two outputs from the system above are the actual recovered data and the

phase offset. The phase offset is then to be used to control the VCO in a PLL.

Obviously, some scaling and dividing will need to be done on the signal in order to

provide an appropriate control for the VCO. The next figure illustrates the PLL to be

used and its associated output signals [7]:

28

Figure 12: PLL Realization

The first graph shows the under damped response of the VCO control signal. The

additional two graphs show the synthesized output of the PLL along with the input

reference signal.

29

After the clock recovery system was simulated, (omitting the PLL for simulation

time reasons and using an ideal frequency), the following two graphs resulted:

Figure 13: Scatter Plots of RX and Recovered Signals

30

Figure 14: Input Data Vs. Recovered Data

The scatter plots track well with what was originally predicted. The plot on the

left shows the RX phasor prior to clock recovery and the plot on the right illustrates the

phasor after the clock recovery.

Figure 14 shows the data being transmitted on the top and the recovered data on

e shift was introduced.

Additionally, a non-ideal “noisy” channel was introduced in Matlab using the Add White

Gaussian Noise Model. (AWGN) The AWGN model used had a 60 dB signal-to-noise

ratio with an input signal power of 1 watt [7].

31

Chapter 4: Power and Area Estimates

The following section will provide rough estimates for power and area of the PLL

and differential amplifiers used in the clock recovery block. Simple models will be used

for the PLL and for the Differential Amplifier. The purpose of this is to predict the

feasibility of the design in both the power and area space. First, we will explore the PLL

for area and power and then the differential amplifier.

4.1 PLL AREA ESTIMATES

For this specific application, a generic PLL was chosen to illustrate the feasibility

of the design. This PLL uses a phase detector, charge pump, and a voltage controlled

oscillator. (VCO) The reference design was taken directly from Microwind®. The

following figure shows the layout of the PLL chosen [9].

32

Figure 15: Layout of Generic PLL

This specific design can be realized in a bounding box of 198 µm by 420 µm.

Obviously, the bounding box could be filled additional logic, such as our ECC logic or

our generic control logic.

4.2 PLL POWER ESTIMATES

Next, we turn to the simulations to evaluate the power of the PLL. If we look at

the simulation of the PLL proper at an output frequency of 6.86 GHz, the measured

power number is 0.498 mW. If the band-gap circuitry, clock drivers, and associated test

logic are included in the design, a reasonable estimate for the power in the PLL and

associated circuitry would be around 20mW [12]. The following figure shows the

measured power for the PLL proper at 6.86 GHz [9].

Figure 16: Power Measurements of the PLL proper.

33

Since the reference design has an output frequency of 6.86 GHZ, we can see that

the target frequency of 3.6 GHz can be achieved with this reference design of the PLL.

4.3 AMPLIFIER AREA ESTIMATES

For this application, a generic amplifier was chosen to evaluate the power for

feasibility purposes. Using the Microwind® design as a reference, the approximate are of

the design is approximately 168 µm by 162 µm as can be seen in the figure below [9].

34

Figure 17: Amplifier Layout

4.4 AMPLIFIER POWER ESTIMATES

Again, we turn to the simulations to evaluate the power of the amplifier. The

power estimate does not include the power needed by the bandgap reference circuitry,

however we have already accounted for that power usage in the PLL model. Looking at

the simulations, we can see that the amplifier consumes approximately 0.248mW of

power. That power number is for the amplifier base. Once stages are added to get the

desired output impedance, we can again assume that the amplifier power will increase to

somewhere around 20mW [12]. (Depending on the type and amount of stages added)

The power simulation for the amplifier can be seen in the figure below [9].

Figure 18: Amplifier Power Estimate

35

4.5 OVERALL POWER ESTIMATE

The overall clock recovery scheme will use 2 Phase-Lock Loops, 6 amplifiers (4

differential and 2 common source), 4 mixers, 2 low-pass filters (for phase shift), and

some random control logic. If we assume that the mixer power is negligible as compared

to the amplifiers and PLLs, then we can neglect the power contribution from the mixer.

Additionally, the low-pass filters will be composed of passive devices, so there will be no

active power consumption. Finally, if we take a conservative estimate on the random

logic and assume that it will consume the same amount of power as the PLL, then we can

get a rough estimate of the power usage for the clock recovery circuitry. Using that

model, we can propose a power estimate of 180mW for the entire clock recovery block.

36

Chapter 5: Project Integration and Conclusion

A systematic approach has been presented for the design of a wireless USB

transceiver, from a problem statement to the realization of the low-power monolithic IC

design for a wireless USB transceiver. The first chapter goes through the overall design

problem and proposed solution; to replace the complex tangle of wiring used to connect

consumer electronics, computer peripheral, and mobile devices with a high-bandwidth

wireless, low-power, low-cost wireless links. The second chapter goes through high-level

details for the wireless USB device: how the transceiver communicates with the USB

physical interface, how the device is going to package the data for wireless

communication and obviously the wireless transmission itself. The USB wireless

transceiver would need to transmit 4 bits, to cover all the USB states. This would imply

that a packet of 6 bits, including headers, would be needed to transmit at USB data

speeds. However, to enable the use of error correction, six USB transmissions are

buffered together prior to encoder, and 18 bits are encoded into 36 bits for each wireless

packet. Since a QPSK transmission scheme was chosen for the USB Wireless Device,

which in effect doubles the data that can be transmitted, in essence 18 bits are sent during

the course of six USB transmissions, so three QPSK symbols per USB transmission.

Therefore, the data for high-speed USB would need to be transmitted at 1.44 GHz

(480Mb/sec*3). The frequency of the carrier waves to carry these data packets was set to

3.6 GHz.

The wireless USB project then diverged into the design of 4 major components

for the wireless USB design: 1) USB Interface, Packet Generation, and Error Correction

Scheme 2) Clock Recovery Mechanism between the Transmitter and Receiver 3) low

noise amplifier (LNA), power amplifier (PA), and antenna [10] and 4) Frequency

37

Synthesizer for sine and cosine wave generation for the QPSK transmission scheme [4].

Emphasis was made on each of these major components to reduce the power dissipation

and area.

5.1 DIGITAL USB INTERFACE AND ERROR CORRECTION CIRCUITRY

A method to provide a simple interface with basic error correction between a USB

2.0 device and the QPSK wireless transmission algorithm has been presented. The

interface takes inputs from an attached USB host controller that are generated at a

maximum frequency of 480 MHz and creates buffers of six USB transmissions to be

encoded via a convolutional coder that employs a 1/3 rate code [11]. The two outputs of

the convolutional coder are the inputs to the QPSK, which modulates the data, which is

generated with a maximum frequency of 1.44 GHz, with a 3.6 GHz carrier wave [11].

On the receiving end, the decoder receives two streams of data from the QPSK

demodulator. The decoder decodes the data using the Viterbi algorithm, eventually

choosing the most-likely received data from four sets of saved data. The selected data

stream is then broadcast to the receiving end of the USB interface in six bit parcels,

which are generated off the 1x clock which has a maximum frequency of 480 MHz.

These parcels contain two header bits, data + and data – bits, as well as the s/d and chirp

bits [11]. These are converted inside the interface to the correct format and then sent on

to the host controller.

The overall interface is quite simple from a digital circuit standpoint. It consists

mostly of small pieces of logic to do the data conversion and determine when a packet is

received or transmitted. The largest portion of it is the counters used to detect a reset

condition. To do this, there must be one counter that can detect 2.5 us of a certain state

38

and another that detects 3 ms of the state [11]. These can be done with a 13-bit counter

and a 2-bit counter, if the low speed 1x clock with a frequency of 1.5 MHz is used [11].

In total, the digital interface consumes about 1 mW of power during transmit or

receive[11].

The transmit register is more complex than the top interface, but still rather

simple. It consists of 9 flip-flops running on the 3x clock (1.44 GHz), and 41 flip-flops

running on the 1x clock (480 MHz) [11]. It also contains 2 single bit precision adders to

perform the convolutional encoding. From simulations, this results in a power

consumption of 4.2 mW during transmit for the transmit register [11].

The receive register is the most complex portion of the digital interface. It

contains 253 flip-flops operating on the 3x clock which store the various paths, the

number of errors they contain, and the like [11]. It also contains 11 flops that operate on

the 1x clock and 18 flip-flops that essentially operate at 80 MHz which take care of the

interface between the top interface and the decoder [11]. Finally, it contains five 6-bit

adders to update the number of errors found in the stored paths, and three 5-bit

comparators to decide with of the paths contain the fewest errors. From simulations, a

power consumption 63 mW is seen during reception in the receive register [11].

The encoder and decoder’s primary interface is with the top level interface and

the QPSK modulator and demodulator as mentioned above. However, it also will not

perform any encoding nor decoding until it has received a signal from the clock recovery

mechanism that the PLL has locked.

39

5.2 CLOCK RECOVERY MECHANISM

The clock recovery scheme takes a very straight forward approach to solving this

problem. Using a QPSK transmit and receive scheme allows for the easy recovery of the

clock using standard analog integration techniques. By starting out with a receive clock

that is “close” to the same frequency that was transmitted, the clock recovery circuitry

can recover the data and the phase offset using integrators and mixers. The frame

recovery can also be realized using a standard integrator.

The phase offset recovered from the incoming wave can then be fed back to the

PLLs for use in helping the PLL to lock onto the transmitted frequency. There are two

PLLs used in this system, one to generate sine terms and one to generate cosine terms.

Each PLL receives a reference clock from the frequency synthesizer (One sine and one

cosine) that is used as a direct input into the phase detector. The phase detector then

compares the frequency and phase of the reference clock to the phase term generated by

the clock recovery circuitry and controls the VCO appropriately. The system requires a

start signal form the LNA circuitry that enables the PLL to start the locking sequence.

The transmitter will begin transmitting random data upon power up, so there will be

sufficient time to achieve lock.

Once the PLL has locked on frequency, the clock recovery circuitry will begin

transmitting data to the ECC block. Prior to that, the clock recovery circuitry will

transmit an enable signal to the ECC block letting it know that the incoming data stream

is valid and that the PLL is locked.

Since QPSK is fairly tolerant to jitter on the clock, the response time of the PLL is

not absolutely critical. This clock recovery mechanism will adjust to phase shifts every

cycle, but is limited by the response time of the PLL. Overall, the system will be able to

40

correct for phase shifts and large amounts of jitter while continuing to align to the frame

boundary.

5.3 LOW-NOISE AMPLIFIER, POWER AMPLIFIER, AND ANTENNA

The straightforward approach of the single ended low noise amplifier (LNA)

allowed for clean and simple input mechanism to receive the transmitted signal from the

antenna [10]. By using a single ended LNA, it was able to produce a signal output that

met the requirements for noise rejection as well as utilize a low power implementation.

The use of a direct down conversion scheme on the input architecture can keep the

number of off chip components to a minimum, continuing the trend of low power, low

cost implementation. The single ended LNA was critical to realizing these constraints.

The single ended LNA front end architecture consists of the antenna followed by

the off chip channel select bandpass filter. The signal gets received by the LNA on die

and further bandpass filtered to hone in on the fundamental 3.6 GHz signal. The main

mechanism through which the LNA achieves its gain at a given frequency while at the

same time attenuating other frequencies is tuned inductive resonance. The LNA tries to

minimize the amount of noise injected into the system at 3.6 GHz and minimize noise at

other frequencies. In that manner, it can achieve a very high signal to noise ratio with a

small, single stage of amplification. The overall LNA solution should also include sine

wave input detection circuitry to notify downstream components like the clock recovery

block that it is receiving a signal.

The power amplifier is essentially the reverse of the LNA. It tries to transmit a

given amount of power to the antenna at a desired frequency and not transmit at any other

frequencies. The necessity to deliver power to a load drives the amount of power

41

consumed. The design goals called for minimizing power consumed as well as off die

components needed. Again, the direct up conversion architecture enables the ease of

lowering component count helping us meet our constraints [10].

The Class C power amplifier presented here achieves a good balance of power

delivery and power consumption. By using a zero gate bias on the output the amplifier

can be largely sized to deliver the needed current to the load without consuming a large

static current [10]. The Class C amplifier seeks to minimize the conduction angle such

that the transistor acts as close to an ideal switch as possible. Essentially, there should be

zero current when there is a large voltage across the transistor and a large current when

there is a very small voltage across the transistor.

Details on Noise Contribution and Power:

PA noise transmitted 5 a HzV

PA Power Added Efficiency 18%

PA drain efficiency 48%

PA SFDR 55db

PA power consumed 33 dbmW

LNA SNR 70db

LNA noise injected 17 f HzV

LNA power consumed 15 dbmW

23 mW RMS power supplied to the Antenna.

5.4 FREQUENCY SYNTHESIZER

A multilevel abstraction approach has been presented for the design of a

frequency synthesizer that will produce the sine/cosine carrier waves used by the

42

transceiver for this wireless USB design [4]. Options for frequency synthesizers were

presented. While analog frequency synthesizers such as the PLL are most prevalent,

many new wireless applications prefer digital frequency synthesizers such as the DDFS

because they provide high frequency accuracy, temperature and time stability, as well as

being frequency agile and phase continuous. The best feature that is most often forgotten

is that digital frequency synthesizers do not need to be tuned, and hence could provide

lower test time and potentially lower costs.

Reference [4] also illustrates the system level consideration about which design of

digital frequency synthesizers to choose and analysis on optimal settings for the DDFS to

meet specifications for the design. The analysis shows that a 64 entry LUT, with 5 bits

output (excluding 1 bit for sign), can produce a SQNR of greater than 30dB and SFDR of

greater than 55dBc.

At a 100MHz operating frequency, at room temperature and using TSMC 0.18u

3.3V technology, each ROM for the folded ROM architecture produce an average power

of 3.5 mW, the 8-bit RCA adder produce an average power of 1.2 mW and the 2 8-bit

registers that store the phase offset produce an average power of 0.7 mW. Excluding the

power consumption of DAC, the total power consumption of the digital frequency

synthesizer is less than 10 mW [4].

5.5 SUMMARY

The transceiver presented can be used in two configurations: it can be attached to

a USB host that has its own power supply, or it can be attached to a device that is

powered by batteries. In the first case, the device must draw less than 200 mA of current

in order to be powered by the USB bus [3]. However, in the second case, when the

transceiver would be connected to battery powered devices such as digital cameras, it

43

would be nice if it could function continuously on a single AA lithium battery for an

entire day. In battery connected mode, the transceiver should only draw current during

transmit or receive. When the USB connection is idle, the current drawn should decrease

considerably.

When the device is transmitting, it is using the power amplifier, the DDFS, the

PLLs, the digital interface, the ECC encoder, and the QPSK modulator. The power

amplifier consumes 33 mW, the PLLs and clock recovery and modulator use 180 mW,

the digital interface 1 mW, and the ECC encoder uses 4.2 mW. The entire system will

consume about 218 mW when transmitting. This power consumption can be converted to

amperes by dividing by the voltage of 3.3V, resulting in a current consumption of 66 mA.

In the receiving state, the components used include the low noise amplifier, the PLLs, the

digital interface, the ECC decoder, and the QPSK demodulator. The LNA consumes 15

mW, the PLLs and clock recovery and modulator use 180 mW, the digital interface 1

mW, the ECC decoder uses 63 mW. This results in a total power consumption of 259

mW, or a current consumption of 78 mA.

Assuming the device is always on and half the time it is transmitting and the other

half it is receiving, the average current consumption would be about 72 mA. This easily

meets the constraints of using the USB bus for power (200 mA or less). Considering that

a single AA lithium battery has a capacity of about 2900 mAh, the transceiver could run

for more than 40 hours continuously in battery-connected mode. Since this device is

targeted for commodities such as digital cameras, that should be acceptable. The power

numbers presented here are for high-speed USB operation. The power consumption

would be significantly less for devices operating in full-speed or low-speed USB modes,

such as mice and keyboards, due to much lower frequency requirements.

xii

Appendices

A1 ACRONYM DEFINITIONS

ADC – Analog to Digital Converter

BER – Bit Error Rate

BPSK – Binary Phase Shift Keying

DAC – Digital to Analog Converter

DDFS – Direct Digital Frequency Synthesizer

ECC – Error Correcting Code

LNA – Low Noise Amplifier

LSB – Least Significant Bit

LUT – Look Up Table

MSB – Most Significant Bit

PA – Power Amplifier

PLL – Phase-Locked Loop

QPSK – Quadrature Phase Shift Keying

RCA – Ripple Carry Adder

ROM – Read Only Memory

SE0 – Single-Ended Zero

SNR – Signal to Noise Ratio

SQNR – Signal Quality to Noise Ratio

USB – Universal Serial Bus

VCO – Voltage Controlled Oscillator

xiii

A2 WIRELESS USB SCHEMATIC

A3 TEST ENVIRONMENT

xiv

A4 RECEIVE LOGIC

xv

A4 TRANSMIT LOGIC

xvi

A5 CONTROL LOGIC

xvii

A6 DATA I/O

xviii

A7 CLOCK RECOVER MODEL

xix

References

[1] Asghar, Saf, PhD. Personal interview. Feb. 2005. [2] Aziz, Adnan. “Comm Theory - QPSK Demodulator.” VSLI Communication

Systems. University of Texas, Austin Texas. Spring 2005. [3] Compaq, et al. Universal Serial Bus Specification. 1996. Revision 1.0 ed. N.p.:

n.p., 1996.

[4] Gokhale, Sanjeev. “Design of a Digital Frequency Synthesizer for Wireless USB.” Fall 2005.

[3] Jones, Douglas, and Swaroop Appadwedula. “Symbol-Timing Recovery for QPSK.” Digital Receivers. 11 Oct. 2004. Rice U. 27 Oct. 2005

- - -. “Symbol-Timing Recovery for QPSK.” Digital Receivers. 11 Oct. 2004. Rice U. [6] Lee, Thomas. The Design of CMOS Radio-Frequency Integrated Circuits. 1998.

2nd ed. Cambridge: Cambridge University Press, 2004.

[7] Mathworks, The. “Phase Shift Keying Simulation.” Matlab Version 7. Apr. 2004.

[8] McDermott, Mark. Personal Communication. Spring 2005.

[9] Microwind. “PLL Simulation.” Microwind 2.6a. Jan. 19, 2003

- - -. Microwind. “Differential Amplifier” Microwind 2.6a. Jan. 19, 2003

[10] Patent, Dimitry. “Wireless USB RF Transceiver Circuitry.” Fall 2005.

[11] Schneider, Jacob. “Error Correction Logic for Wireless USB” Fall 2005.

[12] Shawn, Searles, PhD. Personal interview. Oct. 2005. [13] Stewart, James. “Complex Exponentials.” Calculus: Concepts and Contexts. N.p.:

Brooks/Cole Publishing Company, 1998. A74.

xx

Vita

Floyd Dankert, “Dan”, was born in Bowling Green, Ohio to Floyd and Jane

Dankert. He graduated from Bowling Green High School. He served in the United

States Navy for four years and is a veteran of Operation Desert Shield. He graduated in

2001 from the University of Washington (Seattle) with a BSEE specializing is VLSI. He

currently is employed at Advanced Micro Devices where he serves as a Senior Design

Engineer on the custom circuit design team. He is a current member of the VFW. He has

a spouse Brook and a daughter Elizabeth.

Permanent address: 6417 Clairmont Drive Austin, TX 78749

This dissertation was typed by Floyd L. Dankert