µc/os ii · nayana rao university of north carolina at charlotte. introduction and features •...
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ECGR-6185
µC/OS II
Nayana RaoUniversity of North Carolina at Charlotte
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Introduction and Features
• Very small real time OS kernel: OS that enforces timing constraints
• Memory footprint is small ~ 20 KB
• OS source code is written in C-open source but not free for commercial use
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MULTITASKING
• Process of switching CPU and scheduling between several tasks
• Resources are shared
• Each task is an infinite loop
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KERNEL
• Responsible for managing tasks and initiate context switching
• Pre-emptive kernel
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SCHEDULING
• Preemptive priority driven real time scheduling
• 64 priority levels which means maximum allowed tasks = 64
• Priority inversion problem: When a task with lower priority holds a resource required by high priority task.
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Priority Inversion problem:
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Solution: Priority Inheritance
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MUTUAL EXCLUSION
Avoidance of simultaneous use of resources
• Interrupt Handlers: Enabling and disabling interrupts to manipulate and protect critical sections so that no other ISR or context switch occurs
• Semaphores: binary or counting
• If Deadlock-> Set timeout
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SYNCHRONIZATION AND INTERRUPTS
• Between two tasks or between task and ISR
• Interrupt informs the CPU of asynchronous events
• Interrupt latency is important and should be kept low to improve responsiveness Interrupt latency = max duration for which interrupts are disabled+ time to start executing first instruction in ISR
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µC/OS II File Structure
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Tasks
• Small piece of code that performs some function: infinite loop
• Several tasks controlled by a Task Control Block. Also maintains state of task
• Task information maintained by OS-Task’s Context
• Each task has a unique priority
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• Each task could be in 1 of 5 states: Dormant, Ready, Running, Waiting, ISR
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Dormant: Procedure residing on RAM/ROM. Not a task till it is called to execute
Ready: Not delayed or waiting. Contained in a ready list
Running: Task ready or schedule to run on the CPU
Waiting: Task is waiting for an event to occur eg: timeout or for semaphore
ISR: A task may be per empted by an ISR
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Example of Task
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A task may Delay itself for some clock cycles
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Clock Ticks
• Keeps track of timing and delays
• It is an interrupts that is triggered by a timer interrupt
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Task level Scheduling and Context Switching
Scheduler schedules highest priority task to run-Interrupts are disabled during scheduling so that new tasks are not added by
other interrupts to the ready list
Context Switching (handled at interrupt level) must save CPU registers of the pre-empted task to its stack and be able to restore highest priority task from its task
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µC/OS II and the Renesas µC
• µC/OS II can be loaded
• Initialize and start µC/OS II
• Build required application
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