cost-effective a/d flash 8-bit mcu with eeprom … · rev. 1.10 6 e te e 1 01 rev. 1.10 7 e te e 1...
TRANSCRIPT
Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004
Revision: V1.10 Date: �e�te��e� 1�� �01��e�te��e� 1�� �01�
Rev. 1.10 � �e�te��e� 1�� �01� Rev. 1.10 3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Table of Contents
Features ............................................................................................................ 6CPU Featu�es ......................................................................................................................... 6Pe�i�he�al Featu�es ................................................................................................................. 6
General Description ......................................................................................... 7Selection Table ................................................................................................. 7Block Diagram .................................................................................................. 8Pin Assignment ................................................................................................ 8Pin Description .............................................................................................. 10Absolute Maximum Ratings .......................................................................... 14D.C. Characteristics ....................................................................................... 15A.C. Characteristics ....................................................................................... 16ADC Electrical Characteristics ..................................................................... 17LVR Electrical Characteristics ...................................................................... 18LCD Electrical Characteristics ..................................................................... 18Power on Reset Electrical Characteristics .................................................. 18System Architecture ...................................................................................... 19
Clocking and Pi�elining ......................................................................................................... 1�P�og�a� Counte� ................................................................................................................... �0�tack ..................................................................................................................................... �1A�ith�etic and Logic Unit – ALU ........................................................................................... �1
Flash Program Memory ................................................................................. 22�t�uctu�e ................................................................................................................................ ����ecial Vecto�s ..................................................................................................................... ��Look-u� Ta�le ........................................................................................................................ ��Ta�le P�og�a� Exa��le ........................................................................................................ �3In Ci�cuit P�og�a��ing ......................................................................................................... ��On-Chi� De�ug �u��o�t – OCD� ......................................................................................... �5
RAM Data Memory ......................................................................................... 25�t�uctu�e ................................................................................................................................ �5Gene�al Pu��ose Data Me�o�y ............................................................................................ �5��ecial Pu��ose Data Me�o�y ............................................................................................. �6
Special Function Register Description ........................................................ 29Indi�ect Add�essing Registe�s – IAR0� IAR1 ......................................................................... ��Me�o�y Pointe�s – MP0� MP1 .............................................................................................. ��Bank Pointe� – BP ................................................................................................................. 30Accu�ulato� – ACC ............................................................................................................... 30P�og�a� Counte� Low Registe� – PCL .................................................................................. 30Look-u� Ta�le Registe�s – TBLP� TBLH ................................................................................ 30�tatus Registe� – �TATU� .................................................................................................... 31
Rev. 1.10 � �e�te��e� 1�� �01� Rev. 1.10 3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
EEPROM Data Memory .................................................................................. 32EEPROM Data Me�o�y �t�uctu�e ........................................................................................ 3�EEPROM Registe�s .............................................................................................................. 33Reading Data f�o� the EEPROM ........................................................................................ 3�W�iting Data to the EEPROM ................................................................................................ 35W�ite P�otection ..................................................................................................................... 35EEPROM Inte��u�t ................................................................................................................ 35P�og�a��ing Conside�ations ................................................................................................ 36
Oscillator ........................................................................................................ 37Oscillato� Ove�view ............................................................................................................... 37System Clock Configurations ................................................................................................ 37Inte�nal RC Oscillato� – HIRC ............................................................................................... 38Inte�nal 3�kHz Oscillato� – LIRC ........................................................................................... 38�u��le�enta�y Oscillato� ...................................................................................................... 38
Operating Modes and System Clocks ......................................................... 38�yste� Clocks ...................................................................................................................... 38�yste� O�e�ation Modes ...................................................................................................... 3�Cont�ol Registe� .................................................................................................................... �0O�e�ating Mode �witching .................................................................................................... ��NORMAL Mode to �LOW Mode �witching ........................................................................... �3�LOW Mode to NORMAL Mode �witching .......................................................................... ��Ente�ing the �LEEP0 Mode .................................................................................................. ��Ente�ing the �LEEP1 Mode .................................................................................................. �5Ente�ing the IDLE0 Mode ...................................................................................................... �5Ente�ing the IDLE1 Mode ...................................................................................................... �5�tand�y Cu��ent Conside�ations ........................................................................................... �6Wake-u� ................................................................................................................................ �6
Watchdog Timer ............................................................................................. 47Watchdog Ti�e� Clock �ou�ce .............................................................................................. �7Watchdog Ti�e� Cont�ol Registe� ......................................................................................... �7Watchdog Ti�e� O�e�ation ................................................................................................... �8
Reset and Initialisation .................................................................................. 49Reset Functions .................................................................................................................... 50Reset Initial Conditions ......................................................................................................... 53
Input/Output Ports ......................................................................................... 56Pull-high Resisto�s ................................................................................................................ 57Po�t A Wake-u� ..................................................................................................................... 58I/O Po�t Cont�ol Registe�s ..................................................................................................... 58Pin-sha�ed Functions ............................................................................................................ 5�I/O Pin �t�uctu�es .................................................................................................................. 6��yste� Clock out�ut �in CLO ............................................................................................... 65P�og�a��ing Conside�ations ................................................................................................ 65
Rev. 1.10 � �e�te��e� 1�� �01� Rev. 1.10 5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Timer Modules – TM ...................................................................................... 66Int�oduction ........................................................................................................................... 66TM O�e�ation ........................................................................................................................ 66TM Clock �ou�ce ................................................................................................................... 66TM Inte��u�ts ......................................................................................................................... 67TM Exte�nal Pins ................................................................................................................... 67TM In�ut/Out�ut Pin Cont�ol Registe� ................................................................................... 67P�og�a��ing Conside�ations ................................................................................................ 68
Standard Type TM – STM .............................................................................. 69�tanda�d TM O�e�ation ......................................................................................................... 6��tanda�d Ty�e TM Registe� Desc�i�tion ............................................................................... 70�tanda�d Ty�e TM O�e�ating Modes .................................................................................... 7�Co��a�e Out�ut Mode .......................................................................................................... 7�Ti�e�/Counte� Mode ............................................................................................................. 77PWM Out�ut Mode ................................................................................................................ 77�ingle Pulse Mode ................................................................................................................ 80Ca�tu�e In�ut Mode .............................................................................................................. 8�
Periodic Type TM – PTM ................................................................................ 83Pe�iodic TM O�e�ation .......................................................................................................... 83Pe�iodic Ty�e TM Registe� Desc�i�tion ................................................................................. 8�Pe�iodic Ty�e TM O�e�ating Modes ...................................................................................... 88Co��a�e Match Out�ut Mode ............................................................................................... 88Ti�e�/Counte� Mode ............................................................................................................. �1PWM Out�ut Mode ................................................................................................................ �1�ingle Pulse Out�ut Mode .................................................................................................... �3Ca�tu�e In�ut Mode .............................................................................................................. �5
Analog to Digital Converter .......................................................................... 97A/D Ove�view ........................................................................................................................ �7A/D Conve�te� Registe� Desc�i�tion ...................................................................................... �8A/D Conve�te� Data Registe�s – �ADOL� �ADOH ................................................................ �8A/D Conve�te� Cont�ol Registe�s – �ADC0� �ADC1� �ADC�� PA�R� PB�R ....................... ��A/D O�e�ation ..................................................................................................................... 10�A/D Conve�te� In�ut �ignal ................................................................................................. 103Conve�sion Rate and Ti�ing Diag�a� ................................................................................ 10��u��a�y of A/D Conve�sion �te�s ..................................................................................... 105P�og�a��ing Conside�ations .............................................................................................. 106A/D T�ansfe� Function ......................................................................................................... 106A/D P�og�a��ing Exa��les ............................................................................................... 107
Rev. 1.10 � �e�te��e� 1�� �01� Rev. 1.10 5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Interrupts ...................................................................................................... 109Inte��u�t Registe�s ............................................................................................................... 10�Inte��u�t O�e�ation ...............................................................................................................115Exte�nal Inte��u�t ..................................................................................................................117Multi-function Inte��u�t .........................................................................................................118A/D Conve�te� Inte��u�t ........................................................................................................118Ti�e Base Inte��u�ts ............................................................................................................118EEPROM Inte��u�t .............................................................................................................. 1�0TM Inte��u�ts ....................................................................................................................... 1�0Inte��u�t Wake-u� Function ................................................................................................. 1�0P�og�a��ing Conside�ations .............................................................................................. 1�1
SCOM Function for LCD .............................................................................. 122LCD o�e�ation ..................................................................................................................... 1��LCD Bias Cu��ent Cont�ol ................................................................................................... 1�3
Application Circuits ..................................................................................... 124Instruction Set .............................................................................................. 125
Int�oduction ......................................................................................................................... 1�5Inst�uction Ti�ing ................................................................................................................ 1�5Moving and T�ansfe��ing Data ............................................................................................. 1�5A�ith�etic O�e�ations .......................................................................................................... 1�5Logical and Rotate O�e�ation ............................................................................................. 1�6B�anches and Cont�ol T�ansfe� ........................................................................................... 1�6Bit O�e�ations ..................................................................................................................... 1�6Ta�le Read O�e�ations ....................................................................................................... 1�6Othe� O�e�ations ................................................................................................................. 1�6
Instruction Set Summary ............................................................................ 127Ta�le Conventions ............................................................................................................... 1�7
Instruction Definition ................................................................................... 129Package Information ................................................................................... 138
8-�in �OP (150�il) Outline Di�ensions ............................................................................. 13�10-�in M�OP Outline Di�ensions ...................................................................................... 1�016-�in N�OP (150�il) Outline Di�ensions ......................................................................... 1�1�0-�in DIP (300�il) Outline Di�ensions ............................................................................. 1���0-�in �OP (300�il) Outline Di�ensions ........................................................................... 1���0-�in ��OP (150�il) Outline Di�ensions ......................................................................... 1�5
Rev. 1.10 6 �e�te��e� 1�� �01� Rev. 1.10 7 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Note that 8-pin MCU package types are not marketed in the following countries: USA, UK, Germany, The Netherlands, France and Italy.
Features
CPU Features• OperatingVoltage
♦ fSYS=8MHz:2.2V~5.5V
• Upto0.5μsinstructioncyclewith8MHzsystemclockatVDD=5V
• Powerdownandwake-upfunctionstoreducepowerconsumption
• TwoOscillators♦ InternalRC--HIRC♦ Internal32kHz--LIRC
• Fullyintergratedinternal8MHzoscillatorrequiresnoexternalcomponents
• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP
• Allinstructionsexecutedinoneortwoinstructioncycles
• Tablereadinstructions
• 63powerfulinstructions
• Upto4-levelsubroutinenesting
• Bitmanipulationinstruction
Peripheral Features• FlashProgramMemory:1K×14/2K×15
• RAMDataMemory:64×8/96×8
• EEPROMMemory:32×8
• WatchdogTimerfunction
• Upto18bidirectionalI/Olines
• Softwarecontrolled4-SCOMlinesLCDdriverwith1/2bias(onlyavailableforHT66F004)
• Multiplepin-sharedexternalinterrupts
• MultipleTimerModulesfortimemeasure,comparematchoutput,captureinput,PWMoutput,singlepulseoutputfunctions
• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals
• Multi-channel12-bitresolutionA/Dconverter
• Lowvoltageresetfunction
• Widerangeofavailablepackagetypes
Rev. 1.10 6 �e�te��e� 1�� �01� Rev. 1.10 7 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
General DescriptionThedevicesareFlashMemorytype8-bithighperformanceRISCarchitecturemicrocontrollers.OfferinguserstheconvenienceofFlashMemorymulti-programmingfeatures, thesedevicesalsoincludeawide rangeof functionsandfeatures.Othermemory includesanareaofRAMDataMemoryaswellasanareaofEEPROMmemoryforstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.
Analogfeatures includeamulti-channel12-bitA/Dconverterfunction.MultipleandextremelyflexibleTimerModulesprovide timing,pulsegeneration,capture input,comparematchoutput,singlepulseoutputandPWMgenerationfunctions.ProtectivefeaturessuchasaninternalWatchdogTimerandLowVoltageResetcoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.
AfullchoiceofHIRCandLIRCoscillator functionsareprovided includinga fully integratedsystemoscillatorwhichrequiresnoexternalcomponentsforitsimplementation.
TheinclusionofflexibleI/Oprogrammingfeatures,Time-Basefunctionsalongwithmanyotherfeaturesensurethatthedeviceswillfindexcellentuseinapplicationssuchaselectronicmetering,environmentalmonitoring,handheldinstruments,householdappliances,electronicallycontrolledtools,motordrivinginadditiontomanyothers.
Selection TableMostfeaturesarecommontoalldevices,themainfeaturedistinguishingthemareProgramMemoryandDatamemorycapacity.Thefollowingtablesummarisesthemainfeaturesofeachdevice.
Part No. Program Memory
Data Memory
DataEEPROM I/O A/D
ConverterTimer
ModuleTime Base Stack R-Type
LCD Package
HT66F00� 1K×1� 6�×8 3�×8 8 1�-�it×� 10-�it �TM×1 � � — 8�OP/ 10M�OP
HT66F003 1K×1� 6�×8 3�×8 1� 1�-�it×� 10-�it �TM×110-�it PTM×1 � � — 16N�OP
HT66F00� �K×15 �6×8 3�×8 18 1�-�it×8 10-�it PTM×� � � ��COM16N�OP
�0DIP/�OP �0��OP/
Rev. 1.10 8 �e�te��e� 1�� �01� Rev. 1.10 � �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Block Diagram
8-bitRISCMCUCore
I/O
TimeBases
Low Voltage Reset
InterruptController
ResetCircuit
12-bit A/DConverter
RAM Data Memory
TimerModules
WatchdogTimer
Internal RCOscillators
Flash Program Memory
EEPROMData
Memory
Flash/EEPROM Programming Circuitry
Note:LCDfunctionisonlyavailableforHT66F004.
Pin Assignment
HT66F00210 MSOP-A
10�876
1�3�5
VDD/AVDDPA6/�TP0I/[�TCK0]
PA5/INT/�TP0B/AN3PA7/[INT]/�TCK0/RE�/ICPCK
PA�
V��/AV��PA0/[�TP0]/[�TP0I]/AN0/ICPDAPA1/[�TP0B]/AN1/VREFPA�/[INT]/�TP0/AN�/VREFOPA3/[INT]
HT66V00216 NSOP-A
16151�131�1110�
VDD/AVDDPA6/�TP0I/[�TCK0]
PA5/INT/�TP0B/AN3
PA�NCNC
OCD�CK
PA7/[INT]/�TCK0/RE�/ICPCK
V��/AV��
PA1/[�TP0B]/AN1/VREFPA�/[INT]/�TP0/AN�/VREFOPA3/[INT]NCNCOCD�DA
PA0/[�TP0]/[�TP0I]/AN0/ICPDA�3�5678
1
HT66F0028 SOP-A
VDD/AVDDPA6/�TP0I/[�TCK0]
PA5/INT/�TP0B/AN3PA7/[INT]/�TCK0/RE�/ICPCK
V��/AV��PA0/[�TP0]/[�TP0I]/AN0/ICPDAPA1/[�TP0B]/AN1/VREFPA�/[INT]/�TP0/AN�/VREFO
8765
1�3�
Rev. 1.10 8 �e�te��e� 1�� �01� Rev. 1.10 � �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
VDD/AVDD
PB�/PTCK0/AN�PA�/PTCK1/AN3PA5/AN�/VREFPA6/AN5/VREFOPA7/PTP1/AN6PB3/�COM3/AN7PB�/CLO/�COM�
HT66F004/HT66V00420 SOP-A/SSOP-A/DIP-A
V��/AV��PC0/�COM0PC1/�COM1
PC�/RE�PA0/PTP0/ICPDA/OCD�DA
PA1/PTP0IPA�/ICPCK/OCD�CK
PA3/PTP1IPB6/PTP1BPB5/PTP0B
PB0/INT0/AN0PB1/INT1/AN1
�01�181716151�131�11
1�3�5678�10
HT66F004/HT66V00416 NSOP-A
16151�131�1110�
�3�5678
1V��/AV��PC0/�COM0PC1/�COM1
PC�/RE�PA0/PTP0/ICPDA/OCD�DA
PA1/PTP0IPA�/ICPCK/OCD�CK
PA3/PTP1I
VDD/AVDD
PB�/PTCK0/AN�PA�/PTCK1/AN3PA5/AN�/VREFPA6/AN5/VREFOPA7/PTP1/AN6
PB0/INT0/AN0PB1/INT1/AN1
HT66F003/HT66V00316 NSOP-A
V��/AV��PA0/[�TP0I]/AN0/OCD�DA/ICPDA
PA1/AN1/VREFPA�/[INT]/[�TCK0]/AN�/OCD�CK/ICPCK
PA3/INT/�TCK0/AN3
VDD/AVDD
PA6/[PTCK1]/�TP0I/[�TP0]PA5/[INT]/PTP1I
PA7/[PTCK1]/[�TP0B]/RE�
PA�/[INT]/PTCK1/�TP0
PB�/PTP1BPB1/[PTCK1]/�TP0BPB0/[PTP1I]/VREFO
PB3/[PTP1]PB�/[PTP1B]PB5/PTP1
16151�131�1110�
�3�5678
1
Note:1.Bracketedpinnamesindicatenon-defaultpinoutremappinglocations.2.AVDD&VDDmeans theVDDandAVDDare thedoublebonding.VSS&AVSSmeans theVSSandAVSSarethedoublebonding.
3.TheOCDSDAandOCDSCKpinsaretheOCDSdedicatedpins
Rev. 1.10 10 �e�te��e� 1�� �01� Rev. 1.10 11 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Pin DescriptionWiththeexceptionofthepowerpinsandsomerelevanttransformercontrolpins,allpinsonthesedevicescanbereferencedby theirPortname,e.g.PA0,PA1etc,whichrefer to thedigital I/Ofunctionofthepins.HoweverthesePortpinsarealsosharedwithotherfunctionsuchastheAnalogtoDigitalConverter,TimerModulepinsetc.Thefunctionofeachpinislistedinthefollowingtable,howeverthedetailsbehindhoweachpinisconfigurediscontainedinothersectionsofthedatasheet.
HT66F002Pin Name Function OPT I/T O/T Description
PA0/[�TP0]/[�TP0I]/AN0/ICPDA
PA0PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
�TP0 PA�R — CMO� TM0 (�TM) out�ut
�TP0I PA�RIF�0 �T — TM0 (�TM) in�ut
AN0 PA�R AN — ADC in�ut channel 0 ICPDA — �T CMO� ICP Data Line
PA1/[�TP0B]/AN1/VREF
PA1PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
�TP0B PA�R — CMO� TM0 (�TM) inve�ting out�utAN1 PA�R AN — ADC in�ut channel 1
VREF PA�R AN — ADC VREF In�ut
PA�/[INT]/�TP0/AN�/VREFO
PA�PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
INT PA�RIF�0 �T — Exte�nal inte��u�t in�ut
�TP0 PA�R — CMO� TM0 (�TM) out�utAN� PA�R AN — ADC in�ut channel �
VREFO PA�R — AN ADC �efe�ence voltage out�ut
PA3/[INT]PA3
PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
INT PA�RIF�0 �T — Exte�nal inte��u�t in�ut
PA� PA� PAWUPAPU �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and
wake-u�
PA5/INT/�TP0B/AN3
PA5PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
INT PA�RIF�0 �T — Exte�nal inte��u�t in�ut
�TP0B PA�R — CMO� TM0 (�TM) inve�ting out�utAN3 PA�R AN — ADC in�ut channel 3
PA6/�TP0I/[�TCK0]
PA6 PAWUPAPU �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and
wake-u��TP0I IF�0 �T — TM0 (�TM) in�ut�TCK0 IF�0 �T — TM0 (�TM) clock in�ut
Rev. 1.10 10 �e�te��e� 1�� �01� Rev. 1.10 11 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Pin Name Function OPT I/T O/T Description
PA7/[INT]/�TCK0/RE�/ICPCK
PA7 PAWUPAPU �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and
wake-u�INT IF�0 �T — Exte�nal inte��u�t in�ut
�TCK0 IF�0 �T — TM0 (�TM) clock in�utRE� R�TC �T — Exte�nal �eset in�ut
ICPCK — �T CMO� ICP Clock LineVDD VDD — PWR — Digital �ositive �owe� su��lyAVDD AVDD — PWR — Analog �ositive �owe� su��lyV�� V�� — PWR — Digital negative �owe� su��lyAV�� AV�� — PWR — Analog negative �owe� su��lyOCD�CK OCD�CK — �T — On Chi� De�ug �yste� Clock Line (OCD� EV only)OCD�DA OCD�DA — �T CMO� On Chi� De�ug �yste� Data Line (OCD� EV only)
HT66F003Pin Name Function OPT I/T O/T Description
PA0/[�TP0I]/AN0/OCD�DA/ICPDA
PA0PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
�TP0I PA�RIF�0 �T — TM0 (�TM) in�ut
AN0 PA�R AN — ADC in�ut channel 0 OCD�DA — �T CMO� On Chi� De�ug �yste� Data Line (OCD� EV only)
ICPDA — �T CMO� ICP Data Line
PA1/AN1/VREFPA1
PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
AN1 PA�R AN — ADC in�ut channel 1 VREF PA�R AN — ADC VREF In�ut
PA�/[INT]/[�TCK0]/AN�/OCD�CK/ICPCK
PA�PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
INT PA�RIF�0 �T — Exte�nal inte��u�t in�ut
�TCK0 IF�0 �T — TM0 (�TM) clock in�utAN� PA�R AN — ADC in�ut channel �
OCD�CK — �T — On Chi� De�ug �yste� Clock Line (OCD� EV only)
ICPCK — �T CMO� ICP Clock Line
PA3/INT/�TCK0/AN3
PA3PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
INT PA�RIF�0 �T — Exte�nal inte��u�t in�ut
�TCK0 IF�0 �T — TM0 (�TM) clock in�utAN3 PA�R AN — ADC in�ut channel 3
PA�/[INT]/PTCK1/�TP0
PA�PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
INT PA�RIF�0 �T — Exte�nal inte��u�t in�ut
PTCK1 PA�RIF�0 �T — TM1 (PTM) clock in�ut
�TP0 PA�R — CMO� TM0 (�TM) out�ut
Rev. 1.10 1� �e�te��e� 1�� �01� Rev. 1.10 13 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Pin Name Function OPT I/T O/T Description
PA5/[INT]/PTP1I
PA5 PAWUPAPU �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and
wake-u�
INT PA�RIF�0 �T — Exte�nal inte��u�t in�ut
PTP1I IF�0 �T — TM1 (PTM) in�ut
PA6/[PTCK1]/�TP0I/[�TP0]
PA6PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
PTCK1 PA�RIF�0 �T — TM1 (PTM) clock in�ut
�TP0I PA�RIF�0 �T — TM0 (�TM) in�ut
�TP0 PA�R — CMO� TM0 (�TM) out�ut
PA7/[PTCK1]/[�TP0B]/RE�
PA7PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
PTCK1 PA�RIF�0 �T — TM1 (PTM) clock in�ut
�TP0B PA�R �T CMO� TM0 (�TM) inve�ting out�utRE� R�TC �T — Exte�nal �eset in�ut
PB0/[PTP1I]/VREFO
PB0 PBPUPB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
PTP1I PB�RIF�0 �T — TM1 (PTM) in�ut
VREFO PB�R — AN ADC �efe�ence voltage out�ut
PB1/[PTCK1]/�TP0B
PB1 PBPUPB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
PTCK1 PB�RIF�0 �T — TM1 (PTM) clock in�ut
�TP0B PB�R �T CMO� TM0 (�TM) inve�ting out�ut
PB�/PTP1BPB� PBPU
PB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
PTP1B PB�R �T CMO� TM1 (PTM) inve�ting out�ut
PB3/[PTP1]PB3 PBPU
PB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
PTP1 PB�R — CMO� TM1 (PTM) out�ut
PB�/[PTP1B]PB� PBPU
PB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
PTP1B PB�R — CMO� TM1 (PTM) inve�ting out�ut
PB5/PTP1PB5 PBPU
PB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
PTP1 PB�R — CMO� TM1 (PTM) out�utVDD VDD — PWR — Digital �ositive �owe� su��lyAVDD AVDD — PWR — Analog �ositive �owe� su��lyV�� V�� — PWR — Digital negative �owe� su��lyAV�� AV�� — PWR — Analog negative �owe� su��ly
Rev. 1.10 1� �e�te��e� 1�� �01� Rev. 1.10 13 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F004Pin Name Function OPT I/T O/T Description
PA0/PTP0/OCD�DA/ICPDA
PA0PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
PTP0 PA�R — CMO� PT0 out�utOCD�DA — �T CMO� On Chi� De�ug �yste� Data Line (OCD� EV only)
ICPDA — �T CMO� ICP Data Line
PA1/PTP0IPA1 PAWU
PAPU �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
PTP0I — �T — PTM0 in�ut
PA�/ICPCK/OCD�CK
PA� PAWUPAPU �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and
wake-u�ICPCK — �T CMO� ICP Clock Line
OCD�CK — �T — On Chi� De�ug �yste� Clock Line (OCD� EV only)
PA3/PTP1IPA3 PAWU
PAPU �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
PTP1I — �T — PTM1 in�ut
PA�/PTCK1/AN3
PA�PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
PTCK1 PA�R �T — PTM1 clock in�utAN3 PA�R AN — ADC in�ut channel 3
PA5/AN�/VREFPA5
PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
AN� PA�R AN — ADC in�ut channel �VREF PA�R AN — ADC VREF In�ut
PA6/AN5/VREFO
PA6PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
AN5 PA�R AN — ADC in�ut channel 5VREFO PA�R — AN ADC �efe�ence voltage out�ut
PA7/PTP1/AN6PA7
PAWUPAPUPA�R
�T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u� and wake-u�
PTP1 PA�R — CMO� PTM1 out�utAN6 PA�R AN — ADC in�ut channel 6
PB0/INT0/AN0PB0 PBPU
PB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
INT0 PB�R �T — Exte�nal inte��u�t in�utAN0 PB�R AN — ADC in�ut channel 0
PB1/INT1/AN1PB1 PBPU
PB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
INT1 PB�R �T — Exte�nal inte��u�t in�utAN1 PB�R AN — ADC in�ut channel 1
PB�/PTCK0/AN�
PB� PBPUPB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
PTCK0 PB�R �T — PTM0 clock in�utAN� PB�R AN — ADC in�ut channel �
Rev. 1.10 1� �e�te��e� 1�� �01� Rev. 1.10 15 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Pin Name Function OPT I/T O/T Description
PB3/�COM3/AN7
PB3 PBPUPB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
�COM3 �COMC — �COM LCD d�ive� out�ut fo� LCD �anel co��onAN7 PB�R AN — ADC in�ut channel 7
PB�/CLO/�COM�
PB� PBPUPB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
CLO PB�R — CMO� �yste� clock out�ut�COM� �COMC — �COM LCD d�ive� out�ut fo� LCD �anel co��on
PB5/PTP0BPB5 PBPU
PB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
PTP0B PB�R �T CMO� PTM0 inve�ting out�ut
PB6/PTP1BPB6 PBPU
PB�R �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
PTP1B PB�R �T CMO� PTM1 inve�ting out�ut
PC0/�COM0PC0 PCPU �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
�COM0 �COMC — �COM LCD d�ive� out�ut fo� LCD �anel co��on
PC1/�COM1PC1 PCPU �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
�COM1 �COMC — �COM LCD d�ive� out�ut fo� LCD �anel co��on
PC�/RE�PC1 PCPU
R�TC �T CMO� Gene�al �u��ose I/O. Registe� ena�led �ull-u�
RE� R�TC �T — Exte�nal �eset in�utVDD VDD — PWR — Digital �ositive �owe� su��lyAVDD AVDD — PWR — Analog �ositive �owe� su��lyV�� V�� — PWR — Digital negative �owe� su��lyAV�� AV�� — PWR — Analog negative �owe� su��ly
Legend:I/T:Inputtype; O/T:Outputtype; PWR:Power;OP:Optionalbyregisteroption SCOM:SoftwarecontrolledLCDCOMST:SchmittTriggerinput; CMOS:CMOSoutput; AN:Analogpin*:VDDis thedevicepowersupplywhileAVDDis theADCpowersupply.TheAVDDpin isbondedtogetherinternallywithVDD.
**:VSSisthedevicegroundpinwhileAVSSistheADCgroundpin.TheAVSSpinisbondedtogetherinternallywithVSS.
Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOLTotal..................................................................................................................................... 80mAIOHTotal....................................................................................................................................-80mATotalPowerDissipation......................................................................................................... 500mW
Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.
Rev. 1.10 1� �e�te��e� 1�� �01� Rev. 1.10 15 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
D.C. CharacteristicsTa = �5°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VDD O�e�ating Voltage (HIRC) — f�Y�=8MHz �.� — 5.5 V
IDD1O�e�ating Cu��ent�No��al Mode� f�Y�=fH (HIRC)
3V No load� fH=8MHz� ADC off� WDT ena�le� LVR ena�le
— 1.0 �.0 �A5V — �.0 3.0 �A
IDD�O�e�ating Cu��ent��low Mode� f�Y�=fL=LIRC
3V No load� f�Y�=LIRC� ADC off� WDT ena�le � LVR ena�le
— �0 30 μA5V — 30 60 μA
IDD3O�e�ating Cu��ent�No��al Mode� fH=8MHz (HIRC)
3V No load� f�Y�=fH/�� ADC off� WDT ena�le� LVR ena�le
— 1.0 1.5 �A5V — 1.5 �.0 �A3V No load� f�Y�=fH/�� ADC off�
WDT ena�le� LVR ena�le— 0.� 1.3 �A
5V — 1.3 1.8 �A3V No load� f�Y�=fH/8� ADC off�
WDT ena�le� LVR ena�le— 0.8 1.1 �A
5V — 1.1 1.6 �A3V No load� f�Y�=fH/16� ADC off�
WDT ena�le� LVR ena�le— 0.7 1.0 �A
5V — 1.0 1.� �A3V No load� f�Y�=fH/3�� ADC off�
WDT ena�le� LVR ena�le— 0.6 0.� �A
5V — 0.� 1.� �A3V No load� f�Y�=fH/6�� ADC off�
WDT ena�le� LVR ena�le— 0.5 0.8 �A
5V — 0.8 1.1 �A
IIDLE0IDLE0 Mode �tand�y Cu��ent(LIRC on)
3V No load� ADC off� WDT ena�le� LVR disa�le
— 1.3 3.0 μA
5V — 5.0 10 μA
IIDLE1IDLE1 Mode �tand�y Cu��ent(HIRC)
3V No load� ADC off� WDT ena�le� f�Y�=8MHz on
— 0.8 1.6 �A
5V — 1.0 �.0 �A
I�LEEP0�LEEP0 Mode �tand�y Cu��ent(LIRC off)
3V No load� ADC off� WDT disa�le� LVR disa�le
— 0.1 1.0 μA
5V — 0.3 �.0 μA
I�LEEP1�LEEP1 Mode �tand�y Cu��ent(LIRC on)
3V No load� ADC off� WDT ena�le� LVR disa�le
— 1.3 5.0 μA
5V — �.� 10 μA
VIL1In�ut Low Voltage fo� I/O Po�ts o� In�ut Pins exce�t RE� �in
5V — 0 — 1.5 V— — 0 — 0.�VDD V
VIH1In�ut High Voltage fo� I/O Po�ts o� In�ut Pins exce�t RE� �in
5V — 3.5 — 5.0 V— — 0.8VDD — VDD V
VIL� In�ut Low Voltage (RE�) — — 0 — 0.�VDD VVIH� In�ut High Voltage (RE�) — — 0.�VDD — VDD V
IOL I/O Po�t �ink Cu��ent3V VOL=0.1VDD 18 36 — �A5V VOL=0.1VDD �0 80 — �A
IOH I/O Po�t� �ou�ce Cu��ent3V VOH=0.�VDD -3 -6 — �A5V VOH=0.�VDD -7 -1� — �A
RPH Pull-high Resistance fo� I/O Po�ts3V — �0 60 100 kΩ5V — 10 30 50 kΩ
IOCD�
O�e�ating Cu��ent� No��al Mode� f�Y�=fH (HIRC) (fo� OCD� EV testing� connect to an e-Link)
3V No load� fH=8MHz� ADC off� WDT ena�le — 1.� �.0 �A
Rev. 1.10 16 �e�te��e� 1�� �01� Rev. 1.10 17 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
A.C. CharacteristicsTa = �5°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Condition
fCPU O�e�ating Clock �.�~5.5V — DC — 8 MHz
fHIRC �yste� Clock (HIRC)
3V/5V Ta = �5°C -�% 8 +�% MHz3V/5V Ta = 0°C to 70°C -5% 8 +5% MHz
�.�V~5.5V Ta = 0°C to 70°C -8% 8 +8% MHz�.�V~5.5V Ta = -�0°C to 85°C -1�% 8 +1�% MHz
fLIRC �yste� Clock (LIRC) �.�V~5.5V Ta = -�0°C to 85°C 8 3� 50 kHztTIMER xTCKn� xTPnI In�ut Pulse Width — — 0.3 — — μstRE� Exte�nal Reset Low Pulse Width — — 10 — — μstINT Inte��u�t Pulse Width — — 0.3 — — μstEERD EEPROM Read Ti�e — — — � � t�Y�
tEEWR EEPROM W�ite Ti�e — — — � 5 �s
t��T
�yste� �ta�t-u� Ti�e� Pe�iod(Wake-u� f�o� HALT� f�Y� off at HALT state)
—f�Y� =HIRC 16 — —
t�Y�f�Y� =LIRC � — —
tR�TD
�yste� Reset Delay Ti�e(Powe� On Reset� LVR �eset� WDT �/W �eset(WDTC)
— — �5 50 100 �s
�yste� Reset Delay Ti�e(RE� �eset� WDT no��al �eset) — — 8.3 16.7 33.3 �s
Note:1.tSYS=1/fSYS
2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.
Rev. 1.10 16 �e�te��e� 1�� �01� Rev. 1.10 17 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
ADC Electrical CharacteristicsTa = �5°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
AVDD A/D Conve�te� O�e�ating Voltage — — �.7 — 5.5 V
VADI A/D Conve�te� In�ut Voltage — — 0 — AVDD /VREF
V
VREF A/D Conve�te� Refe�ence Voltage3V
— � — AVDD V5V
DNL Diffe�ential Non-linea�ity�.7V
VREF=AVDD=VDD
tADCK =0.5μs -3 — +3 L�B3V5V
INL Integ�al Non-linea�ity�.7V
VREF=AVDD=VDD
tADCK =0.5μs -� — +� L�B3V5V
IADCAdditional Powe� Consu��tion if A/D Conve�te� is used
3V No load (tADCK =0.5μs ) — 1.0 �.0 �A5V No load (tADCK =0.5μs ) — 1.5 3.0 �A
tADCK A/D Conve�te� Clock Pe�iod �.7~5.5V — 0.5 — 10 μs
tADCA/D Conve�sion Ti�e (Include �a��le and Hold Ti�e)
�.7~5.5V 1�-�it ADC 16 — �0 tADCK
tAD� A/D Conve�te� �a��ling Ti�e �.7~5.5V — — � — tADCK
tON��T A/D Conve�te� On-to-�ta�t Ti�e �.7~5.5V — � — — μs
Rev. 1.10 18 �e�te��e� 1�� �01� Rev. 1.10 1� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
LVR Electrical Characteristics
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VDD O�e�ating Voltage — — 1.� — 5.5 VVLVR Low Voltage Reset Voltage — LVR Ena�le� �.1V o�tion -5% �.10 +5% VVBG Refe�ence Out�ut with Buffe� — TJ = +�5°C @3.15V -5% 1.0� +5% VtLVR Low Voltage Width to Reset — — 160 3�0 6�0 μs
LCD Electrical Characteristics
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
IBIA� VDD/� Bias Cu��ent fo� LCD 5V
I�EL[1:0]=00 17.5 �5.0 3�.5 μAI�EL[1:0]=01 35 50 65 μAI�EL[1:0]=10 70 100 130 μAI�EL[1:0]=11 1�0 �00 �60 μA
V�COM VDD/� Voltage fo� LCD COM Po�t �.�~5.5V No load 0.�75 0.5 0.5�5 VDD
Power on Reset Electrical CharacteristicsTa = �5°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VPOR VDD �ta�t Voltage to Ensu�e Powe�-on Reset — — — — 100 �VRRVDD VDD Rising Rate to Ensu�e Powe�-on Reset — — 0.035 — — V/�s
tPORMini�u� Ti�e fo� VDD �tays at VPOR to Ensu�e Powe�-on Reset — — 1 — — �s
� � � �
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� � � � �� � � �
Rev. 1.10 18 �e�te��e� 1�� �01� Rev. 1.10 1� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.ThedevicetakesadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersproviding increasedspeedofoperationandPeriodicperformance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcall instructions.An8-bitwideALUisusedinpracticallyall instructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.The internaldatapath issimplifiedbymovingdata throughtheAccumulatorandtheALU.Certain internalregistersare implemented in theDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthesedevicessuitableforlow-cost,high-volumeproductionforcontrollerapplications
Clocking and PipeliningThemainsystemclock,derivedfromeitheraHIRCorLIRCoscillator issubdivided intofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.
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System Clock and Pipelining
For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.
Rev. 1.10 �0 �e�te��e� 1�� �01� Rev. 1.10 �1 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
� � � � � � � � � � � � � � � � � � � � � � � � � � � �� � � � � � � � � � � � �
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� � � � � � � � � � � � � � �� � � � � � � � � � � � �
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Instruction Fetching
Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas“JMP”or“CALL” thatdemanda jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.
Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.
DeviceProgram Counter
Program CounterHigh byte PCL Register
HT66F00�/HT66F003 PC�~PC8 PCL7~PCL0HT66F00� PC10~PC8 PCL7~PCL0
Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.
Rev. 1.10 �0 �e�te��e� 1�� �01� Rev. 1.10 �1 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.
Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointer isdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresult inastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.
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Device Stack LevelsHT66F00�/HT66F003 �
HT66F00� �
Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:
• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA
• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA
• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC
• IncrementandDecrement:INCA,INC,DECA,DEC
• Branchdecision:JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI
Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthesedevicestheProgramMemoryareFlash type,whichmeans itcanbeprogrammedandre-programmeda largenumberof times,allowingtheuser theconvenienceofcodemodificationonthesamedevice.Byusingtheappropriateprogrammingtools,theseFlashdevicesofferuserstheflexibilitytoconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.
StructureTheProgramMemoryhasacapacityof1K×14or2K×15bits.TheProgramMemoryisaddressedbytheProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.
000H00�H
3FFH
Reset
Inte��u�t Vecto�
1� �its
HT66F00�
018H
Reset
Inte��u�t Vecto�
1� �its
HT66F003
01CH
Reset
Inte��u�t Vecto�
15 �its
HT66F00�
7FFH
Program Memory Structure
Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000Hisreservedforusebythesedevicesresetforprograminitialisation.Afteradevicereset isinitiated,theprogramwilljumptothislocationandbeginexecution.
Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressofthelookupdatatoberetrievedinthetablepointerregister,TBLP.Thisregisterdefinesthetotaladdressofthelook-uptable.Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe“TABRD[m]”or“TABRDL[m]”instructions,respectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas“0”.Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.
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Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“300H”whichreferstothestartaddressofthelastpagewithinthe1KwordsProgramMemoryofthedevice.Thetablepointerissetupheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“306H”or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthespecifiedpageifthe“TABRD[m]”instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRD[m]”instructionisexecuted.
Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.
Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2::mov a,06h ; initialise low table pointer - note that this address is referencedmov tblp,a ; to the last page or present page::tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address “306H” transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address “305H” transferred to tempreg2 and TBLH in this ; example the data “1AH” is transferred to tempreg1 and data “0FH” to ; register tempreg2::org 300h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh::
Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
In Circuit ProgrammingTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.
Holtek Write PinsMCU Programming Pins
FunctionHT66F002 HT66F003/
HT66F004ICPDA PA0 P�og�a��ing �e�ial DataICPCK PA7 PA� P�og�a��ing �e�ial ClockVDD VDD Powe� �u��lyV�� V�� G�ound
TheProgramMemoryandEEPROMdatamemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefortheclock.Twoadditionallinesarerequiredforthepowersupplyandground.Thetechnicaldetailsregardingthein-circuitprogrammingofthedevicearebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.
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HT66F002 HT66F003/HT66F004Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1korthecapacitance
of*mustbelessthan1nF.
Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
On-Chip Debug Support – OCDSThereisanEVchipwhichisusedtoemulatetheHT66F00xdeviceseries.ThisEVchipdevicealsoprovidesan“On-ChipDebug”functiontodebugthedeviceduringthedevelopmentprocess.TheEVchipandtheactualMCUdevicesarealmostfunctionallycompatibleexceptforthe“On-ChipDebug”function.UserscanusetheEVchipdevicetoemulatetherealchipdevicebehaviorbyconnecting theOCDSDAandOCDSCKpins to theHoltekHT-IDEdevelopment tools.TheOCDSDApinis theOCDSData/Address input/outputpinwhile theOCDSCKpinis theOCDSclockinputpin.WhenusersusetheEVchipfordebugging,otherfunctionswhicharesharedwiththeOCDSDAandOCDSCKpins in theactualMCUdevicewillhavenoeffect in theEVchip.However,thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpinsforICP.ForamoredetailedOCDSdescription,refertothecorrespondingdocumentnamed“Holteke-Linkfor8-bitMCUOCDSUser’sGuide”.
Holtek e-Link Pins EV Chip Pins Pin DescriptionOCD�DA OCD�DA On-chi� De�ug �u��o�t Data/Add�ess in�ut/out�utOCD�CK OCD�CK On-chi� De�ug �u��o�t Clock in�ut
VDD VDD Powe� �u��lyGND V�� G�ound
RAM Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.
StructureDividedintotwosections,thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.
TheoverallDataMemoryissubdividedintotwobanks.TheSpecialPurposeDataMemoryregistersareaccessibleinallbanks,withtheexceptionof theEECregisterataddress40H,whichisonlyaccessibleinBank1.SwitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.ThestartaddressoftheDataMemoryforalldevicesistheaddress00H.
General Purpose Data MemoryThereis64or96bytesofgeneralpurposedatamemorywhicharearrangedinBank0andBank1.Allmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.Byusingthebitoperationinstructions individualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.
Rev. 1.10 �6 �e�te��e� 1�� �01� Rev. 1.10 �7 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue“00H”.
Device Capacity Bank 0 Bank 1HT66F00�/HT66F003 6�×8 �0H~7FH �0H EEC �egiste� only
HT66F00� �6×8 �0H~�FH �0H EEC �egiste� only
00H IAR001H MP00�H IAR103H MP10�H05H ACC06H PCL07H TBLP08H TBLH0�H
INTC1
0AH �TATU�0BH0CH0DH0EH0FH10H
�MOD
11H
EEA
1�H
1�H18H
1BH1AH
1DH1CH
1FH1EH
13H1�H15H16H17H
INTEG
Unused
�TM0AL
PAPUPAWU
�0H�1H��H
��H�8H
�BH�AH
�DH�CH
�EH~
3FH
�3H��H�5H�6H�7H
BP
�TM0DL�TM0C1
�TM0DH
PAPAC
�TM0C0
INTC0
: Unused� �ead as “00”
EED
Unused
Unused
�TM0AHUnused
UnusedMFI0
UnusedUnused
IF�0WDTC
TBC�MOD1
PA�RR�TC
�ADC1�ADC0
�ADC�
�ADOL�ADOH
Unused
Unused
Bank0 & Bank1 Bank0 & Bank1
HT66F002 Special Purpose Data Memory Structure
Rev. 1.10 �6 �e�te��e� 1�� �01� Rev. 1.10 �7 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
00H IAR001H MP00�H IAR103H MP10�H05H ACC06H PCL07H TBLP08H TBLH0�H
INTC1
0AH �TATU�0BH0CH0DH0EH0FH10H
�MOD
11H
EEA
1�H
1�H18H
1BH1AH
1DH1CH
1FH1EH
13H1�H15H16H17H
INTEG
Unused
�TM0AL
PAPUPAWU
�0H�1H��H
��H�8H
�BH�AH
�DH�CH
�EH
�3H��H�5H�6H�7H
BP
�TM0DL�TM0C1
�TM0DH
PAPAC
�TM0C0
INTC0
: Unused� �ead as “00”
EED
Unused
Unused
�TM0AHUnused
UnusedMFI0
Unused
IF�0WDTC
TBC�MOD1
PA�RR�TC
�ADC1�ADC0
�ADC�
�ADOL�ADOH
Bank0 & Bank1 Bank0 & Bank1
PTM1AH
PTM1DHPTM1DL
PTM1AL
PTM1C1
PTM1RPL
PBPUPBCPB
33H3�H
35H3�H
37H36H
38H
�FH30H31H
PTM1RPH3�H
Unused
PTM1C0
Unused3AH
~3FH
MFI1
PB�R
HT66F003 Special Purpose Data Memory Structure
Rev. 1.10 �8 �e�te��e� 1�� �01� Rev. 1.10 �� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
00H IAR001H MP00�H IAR103H MP10�H05H ACC06H PCL07H TBLP08H TBLH0�H
INTC1
0AH �TATU�0BH0CH0DH0EH0FH10H
�MOD
11H
EEA
1�H
1�H18H
1BH1AH
1DH1CH
1FH1EH
13H1�H15H16H17H
INTEG
�COMC
PTM0DH
PAPUPAWU
�0H�1H��H
��H�8H
�BH�AH
�DH�CH
�EH
�3H��H�5H�6H�7H
BP
PTM0C1PTM0C0
PTM0DL
PAPAC
INTC0
: Unused� �ead as “00”
EED
Unused
Unused
PTM0ALUnused
UnusedMFI0
Unused
WDTC
TBC�MOD1
PA�RR�TC
�ADC1�ADC0
�ADC�
�ADOL�ADOH
Bank0 & Bank1 Bank0 & Bank1
PTM1AH
PTM1DHPTM1DL
PTM1AL
PTM1C1
PTM1RPL
PTM0RPHPTM0RPL
33H3�H
35H3�H
37H36H
38H
�FH30H31H
PTM1RPH3�H
PTM0AH
PTM1C0
PB�R
Unused
Unused
Unused
Unused
PCC
PBPUPBC
PC
PB
PCPU
3AH
3CH3BH
3DH3EH3FH
HT66F004 Special Purpose Data Memory Structure
Unused
EECGene�alPu��ose
Data Me�o�y
�0H
7FH
HT66F002/HT66F003 General Purpose Data Memory
Rev. 1.10 �8 �e�te��e� 1�� �01� Rev. 1.10 �� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection,howeverseveralregistersrequireaseparatedescriptioninthissection.
Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.
Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.
ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.
Indirect Addressing Program Exampledata .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ? code .section at 0 code´org00hstart: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM addressloop: clr IAR0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:
Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.
Rev. 1.10 30 �e�te��e� 1�� �01� Rev. 1.10 31 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Bank Pointer – BPForthisseriesofdevices,theDataMemoryisdividedintotwobanks,Bank0andBank1.SelectingtherequiredDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedtoselectDataMemoryBanks0~1.
TheDataMemoryisinitialisedtoBank0afterareset,exceptforaWDTtime-outresetinthePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.ItshouldbenotedthattheSpecialFunctionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinanybank.DirectlyaddressingtheDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.AccessingdatafromBank1mustbeimplementedusingIndirectAddressing.
BP Register Bit 7 6 5 4 3 2 1 0
Na�e — — — — — — — DMBP0R/W — — — — — — — R/WPOR — — — — — — — 0
Bit7~1 Unimplemented,readas"0"Bit0 DMBP0:SelectDataMemoryBanks
0:Bank01:Bank1
Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.
Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.
Look-up Table Registers – TBLP, TBLHThese twospecial functionregistersareused tocontroloperationof the look-up tablewhich isstoredintheProgramMemory.TBLPisthetablepointerandindicatethelocationwherethetabledata is located. Itsvaluemustbesetupbeforeanytablereadcommandsareexecuted. Itsvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHis thelocationwherethehighorderbyteof thetabledata isstoredaftera tablereaddatainstructionhasbeenexecuted.Notethat thelowerordertabledatabyteistransferredtoauserdefinedlocation.
Rev. 1.10 30 �e�te��e� 1�� �01� Rev. 1.10 31 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.
WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe“CLRWDT”or“HALT”instruction.ThePDFflagisaffectedonlybyexecutingthe“HALT”or“CLRWDT”instructionorduringasystempower-up.
TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.
• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.
• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.
• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.
• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.
• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.
• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.
Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.
Rev. 1.10 3� �e�te��e� 1�� �01� Rev. 1.10 33 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
STATUS RegisterBit 7 6 5 4 3 2 1 0
Na�e — — TO PDF OV Z AC CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 × × × ×
"×" unknownBit7~6 Unimplemented,readas"0"Bit5 TO:WatchdogTime-Outflag
0:Afterpoweruporexecutingthe"CLRWDT"or"HALT"instruction1:Awatchdogtime-outoccurred.
Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe"CLRWDT"instruction1:Byexecutingthe"HALT"instruction
Bit3 OV:Overflowflag0:nooverflow1:anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.
Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero
Bit1 AC:Auxiliaryflag0:noauxiliarycarry1:anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction
Bit0 C:Carryflag0:nocarry-out1:anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation
Cisalsoaffectedbyarotatethroughcarryinstruction.
EEPROM Data MemoryThesedevicescontainanareaof internalEEPROMDataMemory.EEPROM,whichstandsforElectricallyErasableProgrammableReadOnlyMemory, isby itsnatureanon-volatileformofmemory,withdataretentionevenwhenitspowersupplyisremoved.Byincorporatingthiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproduct identificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproduct informationtobestoreddirectlywithintheproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.
EEPROM Data Memory StructureTheEEPROMDataMemorycapacityis32×8bitsforthisseriesofdevices.UnliketheProgramMemoryandRAMDataMemory, theEEPROMDataMemory isnotdirectlymappedand isthereforenotdirectlyaccessible in thesamewayas theother typesofmemory.ReadandWriteoperationstotheEEPROMarecarriedoutinsinglebyteoperationsusingtwoaddressregistersandonedataregisterinBank0andasinglecontrolregisterinBank1.
Rev. 1.10 3� �e�te��e� 1�� �01� Rev. 1.10 33 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregisters,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewayasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbedirectlyaddresseddirectlyandcanonlybereadfromorwrittentoindirectlyusingtheMP1MemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinBank1,theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregister,BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.
EEPROM Control Registers List
NameBit
7 6 5 4 3 2 1 0EEA — — — D� D3 D� D1 D0EED D7 D6 D5 D� D3 D� D1 D0EEC — — — — WREN WR RDEN RD
EEA RegisterBit 7 6 5 4 3 2 1 0
Na�e — — — D� D3 D� D1 D0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0
Bit7~5 Unimplemented,readas“0”Bit4~0 DataEEPROMaddress
DataEEPROMaddressbit4~bit0
EED RegisterBit 7 6 5 4 3 2 1 0
Na�e D7 D6 D5 D� D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 DataEEPROMdataDataEEPROMdatabit7~bit0
Rev. 1.10 3� �e�te��e� 1�� �01� Rev. 1.10 35 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
EEC RegisterBit 7 6 5 4 3 2 1 0
Na�e — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0
Bit7~4 Unimplemented,readas"0"Bit3 WREN:DataEEPROMWriteEnable
0:Disable1:Enable
This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.
Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle
This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.
Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable
This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.
Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle
This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.
Note:TheWREN,WR,RDENandRDcannotbesetto“1”atthesametimeinoneinstruction.TheWRandRDcannotbesetto“1”atthesametime.
Reading Data from the EEPROM ToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.
Rev. 1.10 3� �e�te��e� 1�� �01� Rev. 1.10 35 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Writing Data to the EEPROMTheEEPROMaddressofthedatatobewrittenmustfirstbeplacedintheEEAregisterandthedataplacedintheEEDregister.TowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethightoenablethewritefunction.Afterthis,theWRbitintheEECregistermustbe immediatelysethighto initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbefore implementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.NotethatsettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallycleared tozeroby themicrocontroller, informing theuser that thedatahasbeenwritten to theEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.
Write ProtectionProtectionagainst inadvertentwriteoperation isprovided in severalways.After thedevicesarepowered-ontheWriteEnablebit in thecontrolregisterwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willbereset tozero,whichmeansthatDataMemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.
EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbit in therelevant interruptregister.WhenanEEPROMwritecycleends,theDEFrequestflagwillbeset.Iftheglobal,EEPROMInterruptareenabledandthestackisnotfull,asubroutinecalltotheEEPROMInterruptvector,willtakeplace.WhentheEEPROMInterruptisserviced,theEEPROMInterruptflagDEFwillbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.
Rev. 1.10 36 �e�te��e� 1�� �01� Rev. 1.10 37 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Programming ConsiderationsCaremustbetakenthatdataisnotinadvertentlywrittentotheEEPROM.ProtectioncanbePeriodicbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrol register exist.Althoughcertainlynotnecessary, considerationmightbegiven in theapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.Theglobal interruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.Notethatthedevicesshouldnotenter theIDLEorSLEEPmodeuntil theEEPROMreadorwriteoperationis totallycomplete.Otherwise,theEEPROMreadorwriteoperationwillfail.
Programming Examples• Reading data from the EEPROM - polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, 040H ; setup memory pointer MP1MOV MP1, A ; MP1 points to EEC registerMOV A, 01H ; setup Bank PointerMOV BP, ASET IAR1.1 ; set RDEN bit, enable read operationsSET IAR1.0 ; start Read Cycle - set RD bitBACK:SZ IAR1.0 ; check for read cycle endJMP BACKCLR IAR1 ; disable EEPROM writeCLR BPMOV A, EED ; move read data to registerMOV READ_DATA, A
• Writing Data to the EEPROM - polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, EEPROM_DATA ; user defined dataMOV EED, AMOV A, 040H ; setup memory pointer MP1MOV MP1, A ; MP1 points to EEC registerMOV A, 01H ; setup Bank PointerMOV BP, ACLR EMISET IAR1.3 ; set WREN bit, enable write operationsSET IAR1.2 ; start Write Cycle - set WR bit– executed immediately after ; set WREN bitSET EMIBACK:SZ IAR1.2 ; check for write cycle endJMP BACKCLR IAR1 ; disable EEPROM writeCLR BP
Rev. 1.10 36 �e�te��e� 1�� �01� Rev. 1.10 37 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
OscillatorVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughregisters.
Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfortheWatchdogTimerandTimeBaseInterrupts.Twofullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovidedtoformawiderangeofbothfastandslowsystemoscillators.Thehigherfrequencyoscillatorprovideshigherperformancebutcarrywithit thedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillator.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock, thesedeviceshavetheflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.
Type Name Freq.Inte�nal High ��eed RC HIRC 8MHzInte�nal Low ��eed RC LIRC 3�kHz
Oscillator Types
System Clock ConfigurationsThereare twomethodsofgeneratingthesystemclock,ahighspeedoscillatoranda lowspeedoscillator.Thehighspeedoscillatoristheinternal8MHzRCoscillator.Thelowspeedoscillatoristheinternal32kHzRCoscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.
HIRC P�escale�fH
LIRC
Low ��eed Oscillation
fH/�
fH/16
fH/6�
fH/8
fH/�
fH/3�
HLCLKCK��~CK�0 �its
f�Y�
fL
High ��eed Oscillation
System Clock Configurations
Rev. 1.10 38 �e�te��e� 1�� �01� Rev. 1.10 3� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Internal RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.The internalRCoscillator has a fixed frequency of8MHz.Device trimming during themanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethat theinfluenceof thepowersupplyvoltage, temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandattemperatureof25°Cdegrees,thefixedoscillationfrequencyoftheHIRCwillhaveatolerancewithin2%.
Internal 32kHz Oscillator – LIRCThe internal32kHzSystemOscillator is the lowfrequencyoscillator. It isa fully integratedRCoscillatorwitha typicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor itsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.
Supplementary OscillatorThelowspeedoscillator, inadditiontoprovidingasystemclocksource isalsousedtoprovideaclocksource to twootherdevicefunctions.Theseare theWatchdogTimerandtheTimeBaseInterrupts.
Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthesedeviceswithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.
System ClocksThesedeviceshavetwodifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byproviding theuserwithclockoptionsusing registerprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.
Themainsystemclock,cancomefromeitherahighfrequency,fH,oralowfrequency,fL,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromHIRCoscillator.ThelowspeedsystemclocksourcecanbesourcedfromtheinternalclockfL.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.
Thereisoneadditionalinternalclockfortheperipheralcircuits, theTimeBaseclock,fTBC.fTBCissourcedfromtheLIRCoscillators.ThefTBCclockisusedasasourcefortheTimeBaseinterruptfunctionsandfortheTMs.
Rev. 1.10 38 �e�te��e� 1�� �01� Rev. 1.10 3� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HIRC P�escale�fH
LIRC
Low ��eed Oscillation
fH/�
fH/16
fH/6�
fH/8
fH/�
fH/3�
HLCLKCK��~CK�0 �its
f�Y�
fLIRC
High ��eed Oscillation
WDT
f�Y�/�
fTB
Ti�e Base 0
Ti�e Base 1TBCK
fL
fTBC
IDLEN
System Clock Configurations
Note:WhenthesystemclocksourcefSYS isswitchedtofLfromfH, thehighspeedoscillationwillstoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.
System Operation ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingfourmodes,theSLEEP0,SLEEP1, IDLE0andIDLE1modesareusedwhen themicrocontrollerCPUisswitchedoff toconservepower.
OperatingMode
DescriptionCPU fSYS fLIRC fTBC
NORMAL �ode On fH~fH/6� On On�LOW �ode On fL On OnIDLE0 �ode Off Off On OnIDLE1 �ode Off On On On
�LEEP0 �ode Off Off Off Off�LEEP1 �ode Off Off On Off
NORMAL ModeAsthenamesuggests this isoneof themainoperatingmodeswhere themicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedthehighspeedoscillator.ThismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromthehighspeedoscillatorHIRC.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbitsintheSMODregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.
Rev. 1.10 �0 �e�te��e� 1�� �01� Rev. 1.10 �1 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
SLOW ModeThis isalsoamodewhere themicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.TheclocksourceusedwillbefromthelowspeedoscillatorLIRC.Runningthemicrocontrollerinthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.
SLEEP0 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisteris low.IntheSLEEP0modetheCPUwillbestopped,andthefLIRCclockwillbestoppedtoo,andtheWatchdogTimerfunctionisdisabled.
SLEEP1 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterislow.IntheSLEEP1modetheCPUwillbestopped.HoweverthefLIRCclockswillcontinuetooperateiftheWatchdogTimerfunctionisenabled.
IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheSMOD1registerislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchastheWatchdogTimerandTMs.IntheIDLE0Mode,thesystemoscillatorwillbestopped.
IDLE1 ModeTheIDLE1ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheSMOD1registerishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimerandTMs.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1Mode,theWatchdogTimerclock,fLIRC,willbeon.
Control RegisterAsingleregister,SMOD,isusedforoverallcontroloftheinternalclockswithinthedevice.
SMOD RegisterBit 7 6 5 4 3 2 1 0
Na�e CK�� CK�1 CK�0 — LTO HTO IDLEN HLCLKR/W R/W R/W R/W — R R R/W R/WPOR 0 0 0 — 0 0 1 1
Bit7~5 CKS2 ~ CKS0:ThesystemclockselectionwhenHLCLKis“0”000:fL(fLIRC)001:fL(fLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2
Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbetheLIRC,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.
Rev. 1.10 �0 �e�te��e� 1�� �01� Rev. 1.10 �1 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Bit4 Unimplemented,readas"0"Bit3 LTO:Lowspeedsystemoscillatorreadyflag
0:Notready1:Ready
Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillator isstableafterpoweronresetorawake-uphasoccurred.TheflagwillbelowwhenintheSLEEP0mode,butafterawake-uphasoccurredtheflagwillchangetoahighlevelafter1~2cyclesiftheLIRCoscillatorisused.
Bit2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready
Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.
Bit1 IDLEN:IDLEModeControl0:Disable1:Enable
This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.
Bit0 HLCLK:SystemClockSelection0:fH/2~fH/64orfL1:fH
Thisbit isusedtoselectif thefHclockorthefH/2~fH/64orfLclockisusedasthesystemclock.WhenthebitishighthefHclockwillbeselectedandiflowthefH/2~fH/64orfLclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefLclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.
SMOD1 Register Bit 7 6 5 4 3 2 1 0
Na�e F�Y�ON — — — R�TF LVRF — WRFR/W R/W — — — R/W R/W — R/WPOR 0 — — — 0 x — 0
“x” unknownBit7 FSYSON:fSYSControlinIDLEMode
0:Disable1:Enable
Bit6~4 Unimplemented,readas0Bit3 RSTF: ResetcausedbyRSTCsetting
0:Notactive1:Active
Thisbitcanbeclearto“0”,butcannotsetto“1”.Ifthisbitisset,onlyclearedbySoftwareorPORreset.
Bit2 LVRF:LVRfunctionresetflag0:Notactive1:Active
Thisbitcanbeclearto“0”,butcannotbesetto“1”.
Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Bit1 Unimplemented,readas0Bit0 WRF:WDTControlregistersoftwareresetflag
0:Notoccur1:Occurred
Thisbit isset to1by theWDTControlregistersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.
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Operating Mode SwitchingThedevicescanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselectthebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.
Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionoftheIDLENbitintheSMODregisterandFSYSONintheSMOD1register.
WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfL.IftheclockisfromthefL,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchastheTMs.
Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
NORMAL Mode to SLOW Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower, thesystemclockcanswitch to run in theSLOWModebysetting theHLCLKbitto“0”andsetting theCKS2~CKS0bitsto“000”or“001”intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.
TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequiresthisoscillator tobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.
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Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
SLOW Mode to NORMAL Mode Switching InSLOWModethesystemusesLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,where thehighspeedsystemoscillator isused, theHLCLKbit shouldbeset to“1”orHLCLKbit is“0”,butCKS2~CKS0isset to“010”,“011”,“100”,“101”,“110”or“111”.Asacertainamountoftimewillberequiredforthehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.
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Entering the SLEEP0 ModeThereisonlyonewayforthedevicestoentertheSLEEP0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDToff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• Thesystemclock,WDTclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandstopped.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Entering the SLEEP1 ModeThereisonlyonewayforthedevicestoentertheSLEEP1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTon.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,buttheWDTwillremainwiththeclocksourcecomingfromthefLIRCclock.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
Entering the IDLE0 ModeThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinSMOD1registerequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruc-tion,buttheTimeBaseclockwillbeon.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
Entering the IDLE1 ModeThereisonlyonewayforthedevicestoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinSMOD1registerequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• ThesystemclockandTimeBaseclockwillbeonandtheapplicationprogramwillstopatthe“HALT”instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
Rev. 1.10 �6 �e�te��e� 1�� �01� Rev. 1.10 �7 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicestoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode, thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesigner if thepowerconsumptionis tobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighor lowlevelasanyfloating inputpinscouldcreate internaloscillationsandresult in increasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbonbedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.
Caremustalsobe takenwith the loads,whichareconnected to I/Opins,whichare setupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSinputs.IntheIDLE1Modethesystemoscillator ison, if thesystemoscillator is fromthehighspeedsystemoscillator, theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.
Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:
• Anexternalreset
• AnexternalfallingedgeonPortA
• Asysteminterrupt
• AWDToverflow
If thesystemiswokenupbyanexternal reset, thedevicewillexperiencea full systemreset,however, If thesedevicesarewokenupbyaWDToverflow,aWatchdogTimer resetwillbeinitiated.Althoughbothofthesewake-upmethodswillinitiatearesetoperation,theactualsourceofthewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe“HALT”instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.
EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.
Rev. 1.10 �6 �e�te��e� 1�� �01� Rev. 1.10 �7 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.
Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalfLIRCclockwhichissuppliedbytheLIRCoscillator.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to215togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.TheWDTcanbeenabled/disabledusingtheWDTCregister.
Watchdog Timer Control RegisterAsingle register,WDTC,controls the required timeoutperiodaswell as theenable/disableoperation.TheWRFsoftwareresetflagwillbeindicatedintheSMOD1register.TheseregisterscontroltheoveralloperationoftheWatchdogTimer.
WDTC RegisterBit 7 6 5 4 3 2 1 0
Na�e WE� WE3 WE� WE1 WE0 W�� W�1 W�0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1
Bit7~3 WE4 ~ WE0:WDTfunctionsoftwarecontrol10101:WDTdisable01010:WDTenableOthervalues:ResetMCU
Whenthesebitsarechangedtoanyothervaluesbytheenvironmentalnoisetoresetthemicrocontroller,theresetoperationwillbeactivatedafter2~3LIRCclockcyclesandtheWRFbitwillbesetto1toindicatetheresetsource.
Bit2~0 WS2 ~ WS0:WDTTime-outperiodselection000:28/fLIRC001:29/fLIRC010:210/fLIRC011:211/fLIRC(default)100:212/fLIRC101:213/fLIRC110:214/fLIRC111:215/fLIRC
Thesethreebitsdeterminethedivisionratioof theWatchdogTimersourececlock,whichinturndeterminesthetimeoutperiod.
Rev. 1.10 �8 �e�te��e� 1�� �01� Rev. 1.10 �� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
SMOD1 RegisterBit 7 6 5 4 3 2 1 0
Na�e F�Y�ON — — — R�TF LVRF — WRFR/W R/W — — — R/W R/W — R/WPOR 0 — — — 0 x — 0
“x” unknownBit7 FSYSON:fSYSControlinIDLEMode
0:Disable1:Enable
Bit6~4 Unimplemented,readas0Bit3 RSTF: ResetcausedbyRSTCsetting
0:Notactive1:Active
Thisbitcanbeclearto“0”,butcannotsetto“1”.Ifthisbitisset,onlyclearbySoftwareorPORreset.
Bit2 LVRF:LVRfunctionresetflag0:Notactive1:Active
Thisbitcanbeclearto“0”,butcannotbesetto“1”.Bit1 Unimplemented,readas0Bit0 WRF:WDTControlregistersoftwareresetflag
0:Notoccur1:Occurred
Thisbit is set to1by theWDTControl register software resetandclearedby theapplicationprogram.Notethatthisbitcanonlybeclearedto0bytheapplicationprogram.
Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theclearWDTinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.WithregardtotheWatchdogTimerenable/disablefunction,therearefivebits,WE4~WE0,intheWDTCregistertoadditionalenable/disableandresetcontroloftheWatchdogTimer.
WE4 ~ WE0 Bits WDT Function10101B Disa�le01010B Ena�le
Any othe� value Reset MCU
Watchdog Timer Enable/Disable Control
Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.Fourmethodscanbeadoptedtoclear thecontentsof theWatchdogTimer.ThefirstisaWDTreset,whichmeansavalueotherthan01010Band10101BiswrittenintotheWE4~WE0bitlocations,thesecondisanexternalhardwarereset,whichmeansalowlevelontheexternalresetpin,thethirdisusingtheWatchdogTimersoftwareclearinstructionsandthefourthisviaaHALTinstruction.There isonlyonemethodofusingsoftware instruction toclear theWatchdogTimer.Thatistousethesingle“CLRWDT”instructiontocleartheWDT.
Rev. 1.10 �8 �e�te��e� 1�� �01� Rev. 1.10 �� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Themaximumtime-outperiodiswhenthe215divisionratioisselected.Asanexample,witha32kHzLIRCoscillatoras itssourceclock, thiswillgiveamaximumwatchdogperiodofaround1secondforthe215divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.
“CLR WDT”Inst�uction
11-stage Divide�
7-stage Divide�
WE�~WE0 �itsWDTC Registe� Reset MCU
LIRCfLIRC
8-to-1 MUX
CLR
W��~W�0(fLIRC/�1 ~ fLIRC/�11)
WDT Ti�e-out(�8/fLIRC ~ �15/fLIRC)
RE� �in �eset
“HALT”Inst�uction
Watchdog Timer
Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthatthedevicescanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.
Inaddition to thepower-onreset,situationsmayarisewhere it isnecessary toforcefullyapplyaresetconditionwhenthemicrocontroller isrunning.Oneexampleof this iswhereafterpowerhasbeenappliedandthemicrocontrollerisalreadyrunning,theRESlineisforcefullypulledlow.Insuchacase,knownasanormaloperationreset,someof themicrocontrollerregistersremainunchangedallowing themicrocontroller toproceedwithnormaloperationafter thereset line isallowedtoreturnhigh.
Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.
Rev. 1.10 50 �e�te��e� 1�� �01� Rev. 1.10 51 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Reset FunctionsThereareseveralwaysinwhichamicrocontrollerresetcanoccur, througheventsoccurringbothinternallyandexternally:
Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainotherregistersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.
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Note:tRSTDispower-ondelay,typicaltime=50msPower-On Reset Timing Chart
RES Pin ResetAlthoughthemicrocontrollerhasaninternalRCresetfunction,if theVDDpowersupplyrisetimeisnot fastenoughordoesnotstabilisequicklyatpower-on, the internal reset functionmaybeincapableofprovidingproperresetoperation.Forthisreasonit isrecommendedthatanexternalRCnetworkisconnectedtotheRESpin,whoseadditionaltimedelaywillensurethattheRESpinremainslowforanextendedperiodtoallowthepowersupplytostabilise.Duringthistimedelay,normaloperationof themicrocontrollerwillbe inhibited.After theRESlinereachesacertainvoltagevalue,theresetdelaytimetRSTDisinvokedtoprovideanextradelaytimeafterwhichthemicrocontrollerwillbeginnormaloperation.TheabbreviationSSTinthefiguresstandsforSystemStart-upTimer.
FormostapplicationsaresistorconnectedbetweenVDDandtheRESpinandacapacitorconnectedbetweenVSSandtheRESpinwillprovideasuitableexternalresetcircuit.AnywiringconnectedtotheRESpinshouldbekeptasshortaspossibletominimizeanystraynoiseinterference.ForapplicationsthatoperatewithinanenvironmentwheremorenoiseispresenttheEnhancedResetCircuitshownisrecommended.
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Note:“*”ItisrecommendedthatthiscomponentisaddedforaddedESDprotection“**”Itisrecommendedthatthiscomponentisaddedinenvironmentswherepowerlinenoiseissignificant
External RES Circuit
Rev. 1.10 50 �e�te��e� 1�� �01� Rev. 1.10 51 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
MoreinformationregardingexternalresetcircuitsislocatedinApplicationNoteHA0075EontheHoltekwebsite.
PullingtheRESPinlowusingexternalhardwarewillalsoexecuteadevicereset.Inthiscase,asinthecaseofotherresets,theProgramCounterwillresettozeroandprogramexecutioninitiatedfromthispoint.
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Note:tRSTDispower-ondelay,typicaltime=16.7msRES Reset Timing Chart
• RSTC External Reset Register – HT66F002/HT66F003
Bit 7 6 5 4 3 2 1 0Na�e R�TC7 R�TC6 R�TC5 R�TC� R�TC3 R�TC� R�TC1 R�TC0R/W R/W R/W R/W R/W R R R/W R/WPOR 0 1 0 1 0 1 0 1
Bit7~0 RSTC7 ~ RSTC0:PA7/RESselection01010101:configuredasPA7pinorotherfunction10101010:configuredasRESpinOtherValues:MCUreset(resetwillbeactiveafter2~3LIRCclockfordebouncetime)
AllresetwillresetthisregisterasPORvalueexceptWDTtimeoutHardwarewarmreset.
• RSTC External Reset Register – HT66F004
Bit 7 6 5 4 3 2 1 0Na�e R�TC7 R�TC6 R�TC5 R�TC� R�TC3 R�TC� R�TC1 R�TC0R/W R/W R/W R/W R/W R R R/W R/WPOR 0 1 0 1 0 1 0 1
Bit7~0 RSTC7 ~ RSTC0:PC2/RESselection01010101:ConfiguredasPC2pinorotherfunction10101010:ConfiguredasRESpinOtherValues:MCUreset(resetwillbeactiveafter2~3LIRCclockfordebouncetime)
AllresetwillresetthisregisterasPORvalueexceptWDTtimeoutHardwarewarmreset.
Low Voltage Reset – LVRThemicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedeviceandprovideanMCUresetshouldthevaluefallbelowacertainpredefinedlevel.TheLVRfunctionisalwaysenabledduringthenormalandslowmodeswithaspecificLVRvoltageVLVR.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery, theLVRwillautomaticallyreset thedeviceinternallyandtheLVRFbitintheSMOD1registerwillalsobesetto1.ForavalidLVRsignal,alowvoltage,i.e.,avoltagein therangebetween0.9V~VLVRmustexistforgreater thanthevaluetLVRspecifiedin theA.C.characteristics. If the lowvoltagestatedoesnotexceedthisvalue, theLVRwill ignore the lowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRis2.1V,theLVRwillresetthedeviceafter2~3LIRCclockcycles.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceenterstheSLEEP/IDLEmode.
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Note:tRSTDispower-ondelay,typicaltime=50msLow Voltage Reset Timing Chart
Rev. 1.10 5� �e�te��e� 1�� �01� Rev. 1.10 53 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
• SMOD1 Register
Bit 7 6 5 4 3 2 1 0Na�e F�Y�ON — — — R�TF LVRF — WRFR/W R/W — — — R/W R/W — R/WPOR 0 — — — 0 x — 0
“x” unknownBit7 FSYSON:fSYSControlinIDLEMode
DescribeelsewhereBit6~4 Unimplemented,readas0Bit3 RSTF: ResetcausedbyRSTCsetting
0:Notactive1:Active
Thisbitcanbeclearto“0”,butcannotsetto“1”.Ifthisbitisset,onlyclearbySoftwareorPORreset.
Bit2 LVRF:LVRfunctionresetflag0:Notactive1:Active
Thisbitcanbeclearto“0”,butcannotbesetto“1”.Bit1 Unimplemented,readas0Bit0 WRF:WDTControlregistersoftwareresetflag
Describeelsewhere
Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperationisthesameasanLVRresetexceptthattheWatchdogtime-outflagTOwillbesetto“1”.
� � � � � � � � � � � �
� � � � � � � � � � � �
� � � � � � � � � � � � �
Note:tRSTDispower-ondelay,typicaltime=16.7msWDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto“0”andtheTOflagwillbesetto“1”.RefertotheA.C.CharacteristicsfortSSTdetails.
� � � �
� � � � � � � � � � � �
� � � � � � � � � � � � �
WDT Time-out Reset during SLEEP or IDLE Timing Chart
Rev. 1.10 5� �e�te��e� 1�� �01� Rev. 1.10 53 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:
TO PDF RESET Conditions0 0 Powe�-on �esetu u LVR �eset du�ing NORMAL o� �LOW Mode o�e�ation1 u WDT ti�e-out �eset du�ing NORMAL o� �LOW Mode o�e�ation1 1 WDT ti�e-out �eset du�ing IDLE o� �LEEP Mode o�e�ation
Note:“u”standsforunchanged
Thefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.
Item Condition After RESETP�og�a� Counte� Reset to ze�oInte��u�ts All inte��u�ts will �e disa�ledWDT Clea� afte� �eset� WDT �egins countingTi�e� Modules Ti�e� Modules will �e tu�ned offIn�ut/Out�ut Po�ts I/O �o�ts will �e setu� as in�uts and AN0~AN3 as A/D in�ut �ins�tack Pointe� �tack Pointe� will �oint to the to� of the stack
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HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs, it isimportanttoknowwhatconditionthemicrocontroller is inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.Notethatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.
Register
HT66F002
HT66F003
HT66F004
Reset(Power On)
WDT Time-out(Normal
Operation)
RES Reset(Normal
Operation)
RES Reset(HALT)
WDT Time-out(HALT)*
P�og�a� Counte� ● ● ● 0 0 0 H 0 0 0 H 0 0 0 H 0 0 0 H 0 0 0 H
MP0 ● ● ● 1 x x x x x x x 1 x x x x x x x 1 x x x x x x x 1 x x x x x x x 1 u u u u u u uMP1 ● ● ● 1 x x x x x x x 1 x x x x x x x 1 x x x x x x x 1 x x x x x x x 1 u u u u u u uBP ● ● ● - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - uACC ● ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u uPCL ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP ● ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u uTBLH ● ● ● - - x x x x x x - - u u u u u u - - u u u u u u - - u u u u u u - - u u u u u u�TATU� ● ● ● - - 0 0 x x x x - - 1 u u u u u - - u u u u u u - - 0 1 u u u u - - 1 1 u u u u�MOD ● ● ● 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 u u u - u u u uINTEG ● ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uINTC0 ● ● ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u u
INTC1● - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - u u u - u u u
● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u
MFI0● ● - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u
● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI1 ● - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uPA ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAC ● ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAPU ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAWU ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u
IF�0● - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u
● 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 u u u u u - u uWDTC ● ● 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u uTBC ● ● ● 0 0 1 1 - 1 1 1 0 0 1 1 - 1 1 1 0 0 1 1 - 1 1 1 0 0 1 1 - 1 1 1 u u u u – u u u�MOD1 ● ● ● 0 - - - 0 x - 0 0 - - - 0 x - 0 0 - - - 0 x - 0 0 - - - 0 x - 0 u - - - u u - u�COMC ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uEEA ● ● ● - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u uEED ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u�ADOL(ADRF�=0) ● ● ● x x x x - - - - x x x x - - - - x x x x - - - - x x x x - - - - u u u u - - - -
�ADOL(ADRF�=1) ● ● ● x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u
�ADOH(ADRF�=0) ● ● ● x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u
�ADOH(ADRF�=1) ● ● ● - - - - x x x x - - - - x x x x - - - - x x x x - - - - x x x x - - - - u u u u
�ADC0● ● 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 u u u u - - u u
● 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 u u u u - u u u�ADC1 ● ● ● 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 u u u - - u u u
Rev. 1.10 5� �e�te��e� 1�� �01� Rev. 1.10 55 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Register
HT66F002
HT66F003
HT66F004
Reset(Power On)
WDT Time-out(Normal
Operation)
RES Reset(Normal
Operation)
RES Reset(HALT)
WDT Time-out(HALT)*
�ADC� ● ● ● 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 u u - - u u u uR�TC ● ● ● 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 u u u u u u u uPA�R ● ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u
PB�R● - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u u
● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u u�TM0C0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u�TM0C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u�TM0DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u�TM0DH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u�TM0AL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u�TM0AH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM0C0 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM0C1 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM0DL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM0DH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM0AL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM0AH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM0RPL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM0RPH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM1C0 ● ● 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -PTM1C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM1DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM1DH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM1AL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM1AH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM1RPL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM1RPH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u
PB● - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u u
● - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - u u u u u u u
PBC● - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u u
● - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - u u u u u u u
PBPU● - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u u
● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uPC ● - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - u u uPCC ● - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - u u uPCPU ● - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u uEEC ● ● ● - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u
Note:"*"standsforwarmreset"-"notimplement"u"standsfor"unchanged""x"standsfor"unknown"
Rev. 1.10 56 �e�te��e� 1�� �01� Rev. 1.10 57 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.
Thedevicesprovidebidirectional input/output lines labeledwithportnamesPA~PC.TheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.
I/O Control Register List• HT66F002
RegisterName
Bit7 6 5 4 3 2 1 0
PA D7 D6 D5 D� D3 D� D1 D0PAC D7 D6 D5 D� D3 D� D1 D0
PAPU D7 D6 D5 D� D3 D� D1 D0PAWU D7 D6 D5 D� D3 D� D1 D0PA�R PA�7 PA�6 PA�5 PA�� PA�3 PA�� PA�1 PA�0IF�0 — — �TCK0P� �TP0IP� — — INTP�1 INTP�0
• HT66F003
RegisterName
Bit7 6 5 4 3 2 1 0
PA D7 D6 D5 D� D3 D� D1 D0PAC D7 D6 D5 D� D3 D� D1 D0
PAPU D7 D6 D5 D� D3 D� D1 D0PAWU D7 D6 D5 D� D3 D� D1 D0
PB — — D5 D� D3 D� D1 D0PBC — — D5 D� D3 D� D1 D0
PBPU — — D5 D� D3 D� D1 D0PA�R PA�7 PA�6 PA�5 PA�� PA�3 PA�� PA�1 PA�0PB�R — — PB�5 PB�� PB�3 PB�� PB�1 PB�0IF�0 PTCK1P�1 PTCK1P�0 �TCK0P� �TP0IP� PTP1IP� — INTP�1 INTP�0
Rev. 1.10 56 �e�te��e� 1�� �01� Rev. 1.10 57 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
• HT66F004
RegisterName
Bit7 6 5 4 3 2 1 0
PA D7 D6 D5 D� D3 D� D1 D0PAC D7 D6 D5 D� D3 D� D1 D0
PAPU D7 D6 D5 D� D3 D� D1 D0PAWU D7 D6 D5 D� D3 D� D1 D0
PB — D6 D5 D� D3 D� D1 D0PBC — D6 D5 D� D3 D� D1 D0
PBPU — D6 D5 D� D3 D� D1 D0PC — — — — — D� D1 D0
PCC — — — — — D� D1 D0PCPU — — — — — D� D1 D0PA�R PA�7 PA�6 PA�5 PA�� PA�3 PA�� PA�1 PA�0PB�R — PB�6 PB�5 PB�� PB�3 PB�� PB�1 PB�0
Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternalresistor.Toeliminatetheneedfortheseexternalresistors,allI/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregisterPAPU~PCPU,andareimplementedusingweakPMOStransistors.
PAPU RegisterBit 7 6 5 4 3 2 1 0
Na�e D7 D6 D5 D� D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 I/OPortAbit7~bit0Pull-HighControl0:Disable1:Enable
PBPU Register – HT66F003Bit 7 6 5 4 3 2 1 0
Na�e — — D5 D� D3 D� D1 D0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0
Bit7~6 Unimplemented,readas0Bit5~0 I/OPortBbit5~bit0Pull-HighControl
0:Disable1:Enable
PBPU Register – HT66F004 Bit 7 6 5 4 3 2 1 0
Na�e — D6 D5 D� D3 D� D1 D0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0
Bit7 Unimplemented,readas0Bit6~0 I/OPortBbit6~bit0Pull-HighControl
0:Disable1:Enable
Rev. 1.10 58 �e�te��e� 1�� �01� Rev. 1.10 5� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
PCPU Register – HT66F004 Bit 7 6 5 4 3 2 1 0
Na�e — — — — — D� D1 D0R/W — — — — — R/W R/W R/WPOR — — — — — 0 0 0
Bit7~3 Unimplemented,readas0Bit2~0 I/OPortCbit2~bit0Pull-HighControl
0:Disable1:Enable
Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.
PAWU RegisterBit 7 6 5 4 3 2 1 0
Na�e D7 D6 D5 D� D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 I/OPortAbit7~bit0WakeUpControl0:Disable1:Enable
I/O Port Control RegistersEach I/Oporthas itsowncontrol registerknownasPAC~PCC, to control the input/outputconfiguration.With thesecontrol registers, eachCMOSoutputor inputcanbe reconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oports isdirectlymappedtoabit in itsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.
PAC RegisterBit 7 6 5 4 3 2 1 0
Na�e D7 D6 D5 D� D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1
Bit7~0 I/OPortAbit7~bit0Input/OutputControl0:Output1:Input
Rev. 1.10 58 �e�te��e� 1�� �01� Rev. 1.10 5� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
PBC Register – HT66F003Bit 7 6 5 4 3 2 1 0
Na�e — — D5 D� D3 D� D1 D0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 1 1 1 1 1 1
Bit7~6 Unimplemented,readas0Bit5~0 I/OPortBbit5~bit0Input/OutputControl
0:Output1:Input
PBC Register – HT66F004
Bit 7 6 5 4 3 2 1 0
Na�e — D6 D5 D� D3 D� D1 D0
R/W — R/W R/W R/W R/W R/W R/W R/W
POR — 1 1 1 1 1 1 1
Bit7 Unimplemented,readas0Bit6~0 I/OPortBbit6~bit0Input/OutputControl
0:Output1:Input
PCC Register – HT66F004
Bit 7 6 5 4 3 2 1 0
Na�e — — — — — D� D1 D0
R/W — — — — — R/W R/W R/W
POR — — — — — 1 1 1
Bit7~3 Unimplemented,readas0Bit2~0 I/OPortCbit2~bit0Input/OutputControl
0:Output1:Input
Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyof thesedifficultiescanbeovercome.Thewayinwhichthepinfunctionofeachpinisselectedisdifferentforeachfunctionandapriorityorderisestablishedwheremore thanonepinfunction isselectedsimultaneously.Additionally thereareaPASRandaPBSRregister toestablishcertainpinfunctions.Generallyspeaking, theanalogfunctionhashigherprioritythanthedigitalfunction.However,ifmorethantwoanalogfunctionsareenabledandtheanalogsignalinputcomesfromthesameexternalpin,theanaloginputwillbeinternallyconnectedtoalloftheseactiveanalogfunctionalmodules.
Rev. 1.10 60 �e�te��e� 1�� �01� Rev. 1.10 61 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Pin-shared RegistersThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.
• PASR Register – HT66F002
Bit 7 6 5 4 3 2 1 0Na�e PA�7 PA�6 PA�5 PA�� PA�3 PA�� PA�1 PA�0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~6 PAS7~PAS6: Pin-SharedControlBits00:PA5/INT01:STP0B10:PA5/INT11:AN3
Bit5~4 PAS5~PAS4: Pin-SharedControlBits00:PA2/INT01:STP010:VREFO11:AN2
Bit3~2 PAS3~PAS2: Pin-SharedControlBits00:PA101:STP0B10:VREF11:AN1
Bit1~0 PAS1~PAS0: Pin-SharedControlBits00:PA0/STP0I01:STP010:PA0/STP0I11:AN0
• PASR Register – HT66F003
Bit 7 6 5 4 3 2 1 0Na�e PA�7 PA�6 PA�5 PA�� PA�3 PA�� PA�1 PA�0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 PAS7: Pin-SharedControlBit0:PA7/PTCK11:STP0B
Note:PAS7isvalidwhenRSTC=55HBit6 PAS6: Pin-SharedControlBit
0:PA6/PTCK1/STP0I1:STP0
Bit5 PAS5: Pin-SharedControlBit0:PA4/INT/PTCK11:STP0
Bit4 PAS4: Pin-SharedControlBit0:PA3/INT/STCK01:AN3
Rev. 1.10 60 �e�te��e� 1�� �01� Rev. 1.10 61 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Bit3 PAS3: Pin-SharedControlBit0:PA2/INT/STCK01:AN2
Bit2~1 PAS2~PAS1: Pin-SharedControlBits0X:PA110:VREF11:AN1
Bit0 PAS0:Pin-SharedControlBit0:PA0/STP0I1:AN0
• PASR Register – HT66F004
Bit 7 6 5 4 3 2 1 0Na�e PA�7 PA�6 PA�5 PA�� PA�3 PA�� PA�1 PA�0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~6 PAS7~PAS6:Pin-SharedControlBit00:PA701:PTP110:PA711:AN6
Bit5~4 PAS5~PAS4:Pin-SharedControlBit0X:PA610:VREFO11:AN5
Bit3~2 PAS3~ PAS2:Pin-SharedControlBit0X:PA510:VREF11:AN4
Bit1 PAS1:Pin-SharedControlBits0:PA4/PTCK11:AN3
Bit0 PAS0:Pin-SharedControlBit0:PA01:PTP0
Rev. 1.10 6� �e�te��e� 1�� �01� Rev. 1.10 63 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
• PBSR Register – HT66F003
Bit 7 6 5 4 3 2 1 0Na�e — — PB�5 PB�� PB�3 PB�� PB�1 PB�0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0
Bit7~6 Unimplemented,readas“0”Bit5 PBS5: Pin-SharedControlBit
0:PB51:PTP1
Bit4 PBS4: Pin-SharedControlBit0:PB41:PTP1B
Bit3 PBS3: Pin-SharedControlBit0:PB31:PTP1
Bit2 PBS2: Pin-SharedControlBit0:PB21:PTP1B
Bit1 PBS1: Pin-SharedControlBits0:PB1/PTCK11:STP0B
Bit0 PBS0:Pin-SharedControlBit0:PB0/PTP1I1:VREFO
• PBSR Register – HT66F004
Bit 7 6 5 4 3 2 1 0Na�e — PB�6 PB�5 PB�� PB�3 PB�� PB�1 PB�0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0
Bit7 Unimplemented,readas“0”Bit6 PBS6:Pin-SharedControlBit
0:PB61:PTP1B
Bit5 PBS5:Pin-SharedControlBit0:PB51:PTP0B
Bit4 PBS4:Pin-SharedControlBit0:PB41:CLO
Note:PBS4isvalidwhenCOM2EN=0Bit3 PBS3:Pin-SharedControlBit
0:PB31:AN7
Note:PBS3isvalidwhenCOM3EN=0Bit2 PBS2:Pin-SharedControlBit
0:PB2/PTCK01:AN2
Bit1 PBS1:Pin-SharedControlBits0:PB1/INT11:AN1
Bit0 PBS0:Pin-SharedControlBit0:PB0/INT01:AN0
Rev. 1.10 6� �e�te��e� 1�� �01� Rev. 1.10 63 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
• IFS0 Register – HT66F002
Bit 7 6 5 4 3 2 1 0Na�e — — �TCK0P� �TP0IP� — — INTP�1 INTP�0R/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0
Bit7~6 Unimplemented,readas"0"Bit5 STCK0PS:STCK0PinRemappingControl
0:STCK0onPA7(default)1:STCK0onPA6
Bit4 STP0IPS:STP0IPinRemappingControl0:STP0IonPA6(default)1:STP0IonPA0
Bit3~2 Unimplemented,readas"0"Bit1~0 INTPS1, INTPS0:INTPinRemappingControl
00:INTonPA5(default)01:INTonPA210:INTonPA311:INTonPA7
• IFS0 Register – HT66F003
Bit 7 6 5 4 3 2 1 0Na�e PTCK1P�1 PTCK1P�0 �TCK0P� �TP0IP� PTP1IP� — INTP�1 INTP�0R/W R/W R/W R/W R/W R/W — R/W R/WPOR 0 0 0 0 0 — 0 0
Bit7~6 PTCK1PS1, PTCK1PS0:PTCK1PinRemappingControl00:PTCK1onPA4(default)01:PTCK1onPA610:PTCK1onPA711:PTCK1onPB1
Bit5 STCK0PS:STCK0PinRemappingControl0:STCK0onPA3(default)1:STCK0onPA2
Bit4 STP0IPS: STP0IPinRemappingControl0:STP0IonPA6(default)1:STP0IonPA0
Bit3 PTP1IPS: PTP1IPinRemappingControl0:PTP1IonPA5(default)1:PTP1IonPB0
Bit2 Unimplemented,readas"0"Bit1~0 INTPS1, INTPS0:INTPinRemappingControl
00:INTonPA3(default)01:INTonPA210:INTonPA411:INTonPA5
Rev. 1.10 6� �e�te��e� 1�� �01� Rev. 1.10 65 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.
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Generic Input/Output Structure
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A/D Input/Output Structure
Rev. 1.10 6� �e�te��e� 1�� �01� Rev. 1.10 65 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
System Clock output pin CLOThedeviceHT66F004providesasystemclockoutputpinCLO.MCUsystemclockcanoutputtotheCLOpinbysettingpin-sharedcontrolregisterbitPBS4to1.Thehighestoutputfrequencyis8MHzinthisdevice.Pleasenotethatwhenthenoiseproblemisanimportantissue,itisbetternottouseCLOoutputfunction.
Programming ConsiderationsWithintheuserprogram,oneof thefirst thingstoconsider isport initialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoan inputstate, the levelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregistersarethenprogrammedtosetupsomepinsasoutputs, theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregistersarefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbits in theportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.
PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.
Rev. 1.10 66 �e�te��e� 1�� �01� Rev. 1.10 67 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasure time.To implement timerelatedfunctions thedevices includeseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwoindividual interrupts.Theadditionof inputandoutputpins foreachTMensures thatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividualStandardandPeriodicTMsections.
IntroductionThedevicescontainoneortwoTMsdependinguponwhichdeviceisselectedwitheachTMhavingareferencenameofTM0~TM1.EachindividualTMcanbecategorisedasacertaintype,namelyStandardTypeTMorPeriodicTypeTM.Althoughsimilarinnature,thedifferentTMtypesvaryintheirfeaturecomplexity.ThecommonfeaturestotheStandardandPeriodicTMswillbedescribedin thissectionandthedetailedoperationwillbedescribedincorrespondingsections.ThemainfeaturesanddifferencesbetweenthetwotypesofTMsaresummarisedintheaccompanyingtable.
Function STM PTMTi�e�/Counte� √ √I/P Ca�tu�e √ √Co��a�e Match Out�ut √ √PWM Channels 1 1�ingle Pulse Out�ut 1 1PWM Align�ent Edge EdgePWM Adjust�ent Pe�iod & Duty Duty o� Pe�iod Duty o� Pe�iod
TM Function Summary
Device TM0 TM1HT66F00� 10-�it �TM —HT66F003 10-�it �TM 10-�it PTMHT66F00� 10-�it PTM 10-�it PTM
TM Name/Type Reference
TM OperationThetwodifferenttypesofTMsofferadiverserangeoffunctions,fromsimpletimingoperationstoPWMsignalgeneration.ThekeytounderstandinghowtheTMoperatesistoseeitintermsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.
TM Clock SourceTheclocksourcewhichdrivesthemaincounterineachTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingthexTnCK2~xTnCK0bitsinthexTMcontrolregisters.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH, thefTBCclocksourceortheexternalxTCKnpin.ThexTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.
Rev. 1.10 66 �e�te��e� 1�� �01� Rev. 1.10 67 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
TM InterruptsTheStandardandPeriodic typeTMseachhas twointernal interrupts, the internalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerated,itcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.
TM External PinsEachof theTMs, irrespectiveofwhat type,has twoTMinputpins,with the labelxTCKnandxTPnI.TheTMinputpinxTCKn,isessentiallyaclocksourcefortheTMandisselectedusingthexTnCK2~xTnCK0bitsinthexTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThisexternalTMinputpinissharedwithotherfunctionsbutwillbeconnectedtotheinternalTMifselectedusingthexTnCK2~xTnCK0bits.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.
TheotherTMinputpin,xTPnI,isthecaptureinputwhoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedgesandtheactiveedgetransitiontypeisselectedusingthexTnIO1andxTnIO0bitsinthexTMnC1register.
TheTMseachhave twooutputpinswith the labelxTPn andxTPnB.When theTMis in theCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalxTPnoutputpinisalsothepinwheretheTMgeneratesthePWMoutputwaveform.AstheTMoutputpinsarepin-sharedwithotherfunction,theTMoutputfunctionmustfirstbesetupusingregisters.AsinglebitinoneoftheregistersdeterminesifitsassociatedpinistobeusedasanexternalTMoutputpinorifitistohaveanotherfunction.ThenumberofoutputpinsforeachTMtypeisdifferent,thedetailsareprovidedintheaccompanyingtable.
Device TM0 TM1
HT66F00� �TCK0� �TP0I�TP0� �TP0B —
HT66F003 �TCK0� �TP0I�TP0� �TP0B
PTCK1� PTP1IPTP1� PTP1B
HT66F00� PTCK0� PTP0IPTP0� PTP0B
PTCK1� PTP1IPTP1� PTP1B
TM Input/Output Pins
TM Input/Output Pin Control RegisterSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingone register,witha singlebit ineach registercorresponding toaTMinput/outputpin.ConfiguringtheselectionbitscorrectlywillsetupthecorrespondingpinasaTMinput/output.Thedetailsofthepin-sharedfunctionselectionaredescribedinthepin-sharedfunctionsection.
STM
STP0
STCK0
Ca�tu�e In�ut
TCK In�ut
Out�ut
STP0I
STP0BInve�ting Out�ut
STM Function Pin Control Block Diagram
Rev. 1.10 68 �e�te��e� 1�� �01� Rev. 1.10 6� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
PTM
PTPn
PTCKn
Ca�tu�e In�ut
TCK In�ut
Out�ut
PTPnI
PTPnBInve�ting Out�ut
PTM Function Pin Control Block Diagram
Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAregister,andCCRPregisterpairforPeriodicTimerModule,allhavea lowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.As theCCRAregisterandCCRPregistersare implemented in thewayshown in thefollowingdiagramandaccessing the register iscarriedoutCCRP lowbyte registerusing the followingaccessprocedures.AccessingtheCCRAorCCRPlowbyteregisterwithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.
Data Bus
8-�it Buffe�
�TM0DH�TM0DL
�TM0AH�TM0AL
�TM CCRA Registe� (Read/W�ite)
�TM Counte� Registe� (Read only)
Data Bus
8-�it Buffe�
PTMnDHPTMnDL
PTMnAHPTMnAL
PTM CCRA Registe� (Read/W�ite)
PTM Counte� Registe� (Read only)
PTMnRPHPTMnRPL
PTM CCRP Registe� (Read/W�ite)
Thefollowingstepsshowthereadandwriteprocedures:
• WritingDatatoCCRAorPTMCCRP♦ Step1.WritedatatoLowByteSTM0ALPTMnALorPTMnRPL
– notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighByteSTM0AHPTMnAHorPTMnRPH
– heredata iswrittendirectly to thehighbyteregistersandsimultaneouslydata is latchedfromthe8-bitbuffertotheLowByteregisters.
• ReadingDatafromtheCounterRegistersandCCRAorPTMCCRP♦ Step1.ReaddatafromtheHighByteSTM0DH,STM0AHPTMnDH,PTMnAHorPTMnRPH
– heredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.
♦ Step2.ReaddatafromtheLowByteSTM0DL,STM0ALPTMnDL,PTMnALorPTMnRPL– thisstepreadsdatafromthe8-bitbuffer.
Rev. 1.10 68 �e�te��e� 1�� �01� Rev. 1.10 6� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Standard Type TM – STMTheStandardTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheStandardTMcanbecontrolledwithtwoexternalinputpinsandcandrivetwoexternaloutputpins.
Device TM Type TM Name TM Input Pin TM Output PinHT66F00�HT66F003 10-�it �TM �TM �TCK0� �TP0I �TP0� �TP0B
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Standard Type TM Block Diagram
Standard TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPis3-bitwidewhosevalueiscomparedwiththehighest3bitsinthecounterwhiletheCCRAisthe10bitsandthereforecompareswithallcounterbits.
Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclearthecounterbychangingtheST0ONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.
Rev. 1.10 70 �e�te��e� 1�� �01� Rev. 1.10 71 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Standard Type TM Register DescriptionOveralloperationof theStandardTMiscontrolledusingseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthreeCCRPbits.
Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0�TM0C0 �T0PAU �T0CK� �T0CK1 �T0CK0 �T0ON �T0RP� �T0RP1 �T0RP0�TM0C1 �T0M1 �T0M0 �T0IO1 �T0IO0 �T0OC �T0POL �T0DPX �T0CCLR�TM0DL D7 D6 D5 D� D3 D� D1 D0�TM0DH — — — — — — D� D8�TM0AL D7 D6 D5 D� D3 D� D1 D0�TM0AH — — — — — — D� D8
10-bit Standard TM Register List
STM0C0 RegisterBit 7 6 5 4 3 2 1 0
Na�e �T0PAU �T0CK� �T0CK1 �T0CK0 �T0ON �T0RP� �T0RP1 �T0RP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
bit7 ST0PAU:STMCounterPauseControl0:Run1:Pause
Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheSTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.
bit6~4 ST0CK2~ST0CK0:SelectSTMCounterclock000:fSYS/4001:fSYS
010:fH/16011:fH/64100:fTBC101:fTBC110:STCK0risingedgeclock111:STCK0fallingedgeclock
ThesethreebitsareusedtoselecttheclocksourcefortheSTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.
bit3 ST0ON:STMCounterOn/OffControl0:Off1:On
Thisbitcontrolstheoverallon/offfunctionoftheSTM.Settingthebithighenablesthecounter torun,clearingthebitdisables theSTM.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theSTMwhichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheSTMisintheCompareMatchOutputModeorthePWMoutputModeorSinglePulseOutputModethentheSTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheST0OCbit,whentheST0ONbitchangesfromlowtohigh.
Rev. 1.10 70 �e�te��e� 1�� �01� Rev. 1.10 71 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
bit2~0 ST0RP2~ ST0RP0:STMCCRP3-bitregister,comparedwiththeSTMCounterbit9~bit7ComparatorPMatchPeriod000:1024STM0clocks001:128STM0clocks010:256STM0clocks011:384STM0clocks100:512STM0clocks101:640STM0clocks110:768STM0clocks111:896STM0clocks
ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtocleartheinternalcounteriftheST0CCLRbitissettozero.SettingtheST0CCLRbittozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.
STM0C1 RegisterBit 7 6 5 4 3 2 1 0
Na�e �T0M1 �T0M0 �T0IO1 �T0IO0 �T0OC �T0POL �T0DPX �T0CCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
bit7~6 ST0M1~ ST0M0:SelectSTM0OperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMoutputModeorSinglePulseOutputMode11:Timer/CounterMode
ThesebitssetuptherequiredoperatingmodefortheSTM.ToensurereliableoperationtheSTMshouldbeswitchedoffbeforeanychangesaremade to theST0M1andST0M0bits.IntheTimer/CounterMode,theSTMoutputpinstateisundefined.
bit5~4 ST0IO1~ ST0IO0:SelectSTM0functionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput
PWMoutputMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput
CaptureInputMode00:InputcaptureatrisingedgeofSTP0I01:InputcaptureatfallingedgeofSTP0I10:Inputcaptureatfalling/risingedgeofSTP0I11:Inputcapturedisabled
Timer/counterMode:Unused
ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.
Rev. 1.10 7� �e�te��e� 1�� �01� Rev. 1.10 73 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
IntheCompareMatchOutputMode,theST0IO1~ST0IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.WhentheST0IO1~ST0IO0 bitsarebothzero,thennochangewill takeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheST0OCbit.Notethat theoutput levelrequestedbytheST0IO1~ST0IO0bitsmustbedifferentfromtheinitialvaluesetupusingtheST0OCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.After theTMoutputpinchangesstate itcanbereset to itsinitiallevelbychangingtheleveloftheST0ONbitfromlowtohigh.InthePWMMode,theST0IO1andST0IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytochangethevaluesoftheST0IO1andST0IO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheST0IO1andST0IO0bitsarechangedwhentheTMisrunning.
bit3 ST0OC:STM0OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh
PWMoutputMode/SinglePulseOutputMode0:Activelow1:Activehigh
This is theoutputcontrolbit for theSTMoutputpin. ItsoperationdependsuponwhetherSTMisbeingusedintheCompareMatchOutputModeorinthePWMoutputMode/SinglePulseOutputMode.IthasnoeffectiftheSTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheSTMoutputpinbeforeacomparematchoccurs.InthePWMoutputModeitdeterminesif thePWMsignal isactivehighoractivelow.IntheSinglePulseOutputModeitdeterminesthelogicleveloftheSTMoutputpinwhentheST0ONbitchangesfromlowtohigh.
bit2 ST0POL:STM0OutputpolarityControl0:Non-invert1:Invert
ThisbitcontrolsthepolarityoftheSTM0outputpin.WhenthebitissethightheSTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheSTMisintheTimer/CounterMode.
bit1 ST0DPX:STM0PWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period
Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.
bit0 ST0CCLR:SelectSTM0Counterclearcondition0:STM0ComparatorPmatch1:STM0ComparatorAmatch
Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardSTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtocleartheinternalcounter.WiththeST0CCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheST0CCLRbitisnotusedinthePWMoutputmode,SinglePulseorInputCaptureMode.
Rev. 1.10 7� �e�te��e� 1�� �01� Rev. 1.10 73 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
STM0DL Register Bit 7 6 5 4 3 2 1 0
Na�e D7 D6 D5 D� D3 D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0
Bit7~0 STM0CounterLowByteRegisterbit7~bit0STM010-bitCounterbit7~bit0
STM0DH Register Bit 7 6 5 4 3 2 1 0
Na�e — — — — — — D� D8R/W — — — — — — R RPOR — — — — — — 0 0
bit7~2 Unimplemented,readas"0"bit1~0 STM0CounterHighByteRegisterbit1~bit0
STM010-bitCounterbit9~bit8
STM0AL RegisterBit 7 6 5 4 3 2 1 0
Na�e D7 D6 D5 D� D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
bit7~0 STM0CCRALowByteRegisterbit7~bit0STM010-bitCounterbit7~bit0
STM0AH RegisterBit 7 6 5 4 3 2 1 0
Na�e — — — — — — D� D8R/W — — — — — — R RPOR — — — — — — 0 0
bit7~2 Unimplemented,readas"0"bit1~0 STM0CCRAHighByteRegisterbit1~bit0
STM010-bitCounterbit9~bit8
Rev. 1.10 7� �e�te��e� 1�� �01� Rev. 1.10 75 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Standard Type TM Operating ModesTheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheST0M1andST0M0bitsintheSTM0C1register.
Compare Output ModeTo select thismode, bitsST0M1andST0M0 in theSTM0C1 register, shouldbe set to00respectively. In thismodeonce thecounter isenabledand running itcanbeclearedby threemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheST0CCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothSTMA0FandSTMP0FinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.
IftheST0CCLRbitintheSTM0C1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonly theSTMA0Finterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenST0CCLRishighnoSTMP0F interrupt request flagwillbegenerated. In theCompareMatchOutputMode,theCCRAcannotbesetto"0".IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,value,howeverheretheSTMA0Finterruptrequestflagwillnotbegenerated.
Asthenameofthemodesuggests,afteracomparisonismade,theSTMoutputpin,willchangestate.TheSTMoutputpinconditionhoweveronlychangesstatewhenanSTMA0FinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheSTMP0Finterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheSTMoutputpin.ThewayinwhichtheSTMoutputpinchangesstatearedeterminedbytheconditionoftheST0IO1andST0IO0bitsintheSTM0C1register.TheSTMoutputpincanbeselectedusingtheST0IO1andST0IO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionoftheSTMoutputpin,whichissetupaftertheST0ONbitchangesfromlowtohigh,issetupusingtheST0OCbit.NotethatiftheST0IO1andST0IO0bitsarezerothennopinchangewilltakeplace.
Rev. 1.10 7� �e�te��e� 1�� �01� Rev. 1.10 75 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
CCRA
CCRP
0x3FF
Counte� ove�flow
CCRA Int.Flag �TMA0F
CCRP Int.Flag �TMP0F
CCRP > 0Counte� clea�ed �y CCRP value
�TM O/P Pin
�T0ON
Pause
Counte�Reset
Out�ut Pin set to Initial LevelLow if �T0OC= 0
Out�ut Togglewith �TMA0F flag
He�e �T0IO[1:0] = 11Toggle Out�ut �elect
Now �T0IO[1:0] = 10 Active High Out�ut �elect
Out�ut not affected �y�TMA0F flag. Re�ains Highuntil �eset �y �T0ON �it
�T0CCLR = 0; �T0M[1:0] = 00
�T0PAU
Resu�e
�to�
Ti�e
CCRP > 0
CCRP = 0
�T0POL
Out�ut PinReset to initial value
Out�ut inve�tswhen �T0POL is high
Out�ut cont�olled�y othe� �in - sha�ed function
Counte� Value
Compare Match Output Mode – ST0CCLR = 0Note:1.WithST0CCLR=0aComparatorPmatchwillclearthecounter
2.TheTMoutputpincontrolledonlybytheSTMA0Fflag
3.TheoutputpinresettoinitialstatebyaST0ONbitrisingedge
Rev. 1.10 76 �e�te��e� 1�� �01� Rev. 1.10 77 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
CCRA
CCRP
0x3FF
CCRA Int.Flag �TMP0F
CCRP Int.Flag �TMA0F
CCRA > 0 Counte� clea�ed �y CCRA value
�TM O/P Pin
�T0ON
Pause Counte� Reset
Out�ut Pin set to Initial LevelLow if �T0OC= 0
Out�ut Togglewith �TMA0F flag
He�e �T0IO[1:0] = 11Toggle Out�ut �elect
Now �T0IO[1:0] = 10 Active High Out�ut �elect
Out�ut not affected �y�TMA0F flag. Re�ains Highuntil �eset �y �T0ON �it
�T0CCLR = 1; �T0M[1:0] = 00
�T0PAU
Resu�e
�to�
Ti�e
CCRA = 0
�T0POL
Out�ut PinReset to initial value
Out�ut inve�tswhen �T0POL is high
Out�ut cont�olled�y othe� �in-sha�ed function
Counte� Value
Out�ut doesnot change
No �TMA0F flaggene�ated on
CCRA ove�flow
CCRA = 0Counte� ove�flow
�TMP0F notgene�ated
Compare Match Output Mode – ST0CCLR = 1Note:1.WithST0CCLR=1aComparatorAmatchwillclearthecounter
2.TheTMoutputpincontrolledonlybytheSTMA0Fflag
3.TheoutputpinresettoinitialstatebyaST0ONrisingedge
4.TheSTMP0FflagisnotgeneratedwhenST0CCLR=1
Rev. 1.10 76 �e�te��e� 1�� �01� Rev. 1.10 77 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Timer/Counter ModeTo select thismode, bitsST0M1andST0M0 in theSTM0C1 register shouldbe set to 11respectively.TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputModegenerating thesameinterruptflags.Theexception is that in theTimer/CounterModetheSTMoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheSTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunctionbysettingpin-sharefunctionregister.
PWM Output ModeToselectthismode,bitsST0M1andST0M0intheSTM0C1registershouldbesetto10respectivelyandalsotheST0IO1andST0IO0bitsshouldbesetto10respectively.ThePWMfunctionwithintheSTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheSTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.
AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMoutputmode,theST0CCLRbithasnoeffectasthePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrol thedutycycle.Whichregister isusedtocontroleitherfrequencyordutycycleisdeterminedusingtheST0DPXbit intheSTM0C1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.
Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheST0OCbitintheSTM0C1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoST0IO1andST0IO0bitsareusedtoenablethePWMoutputortoforcetheSTMoutputpintoafixedhighorlowlevel.TheST0POLbitisusedtoreversethepolarityofthePWMoutputwaveform.
10-bit STM, PWM Output Mode, Edge-aligned Mode, ST0DPX=0
CCRP 001b 010b 011b 100b 101b 110b 111b 000b
Pe�iod 1�8 �56 38� 51� 6�0 768 8�6 10��
Duty CCRA
IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128,
TheSTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.
IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.
10-bit STM, PWM Output Mode, Edge-aligned Mode, ST0DPX=1
CCRP 001b 010b 011b 100b 101b 110b 111b 000b
Pe�iod CCRA
Duty 1�8 �56 38� 51� 6�0 768 8�6 10��
ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeSTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.
Rev. 1.10 78 �e�te��e� 1�� �01� Rev. 1.10 7� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
CCRP
CCRA
Counte�Value Counte� Clea�ed�y CCRP
CCRA Int.Flag �TMA0F
CCRP Int.Flag �TMP0F
�TM O/P Pin(�T0OC=1)
�T0ON
PWM Duty Cycleset �y CCRA
PWM Pe�iodset �y CCRP
Counte� �to� If �T0ON �it low
Counte� �eset when �T0ON �etu�ns high
PWM �esu�es o�e�ationOut�ut cont�olled �y
Othe� �in-sha�ed function
Ti�e
�T0DPX=0;�T0M[1:0]=10
�T0POL
Out�ut Inve�tsWhen �T0POL = 1
�T0PAU
Resu�ePause
�TM O/P Pin(�T0OC=0)
PWM Output Mode – ST0DPX = 0Note:1.HereST0DPX=0-CounterclearedbyCCRP
2.AcounterclearsetsPWMPeriod
3.TheinternalPWMfunctioncontinuesrunningevenwhenST0IO[1:0]=00or01
4.TheST0CCLRbithasnoinfluenceonPWMoperation
Rev. 1.10 78 �e�te��e� 1�� �01� Rev. 1.10 7� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
CCRA
CCRP
Counte�Value Counte� Clea�ed �y CCRA
CCRP Int.Flag �TMP0F
CCRA Int.Flag �TMA0F
�TM O/P Pin(�T0OC=1)
�T0ON
PWM Duty Cycleset �y CCRP
PWM Pe�iodset �y CCRA
Counte� �to� If �T0ON �it low
Counte� �eset when �T0ON �etu�ns high
PWM �esu�es o�e�ationOut�ut cont�olled �y
Othe� �in-sha�ed function
Ti�e
�T0DPX=1;�T0M[1:0]=10
�T0POL
Out�ut Inve�tsWhen �T0POL = 1
�T0PAU
Resu�ePause
�TM O/P Pin(�T0OC=0)
PWM Output Mode – ST0DPX = 1Note:1.HereST0DPX=1-CounterclearedbyCCRA
2.AcounterclearsetsPWMPeriod
3.TheinternalPWMfunctioncontinuesevenwhenST0IO[1:0]=00or01
4.TheST0CCLRbithasnoinfluenceonPWMoperation
Rev. 1.10 80 �e�te��e� 1�� �01� Rev. 1.10 81 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Single Pulse ModeTo select thismode, bitsST0M1andST0M0 in theSTM0C1 register shouldbe set to 10respectivelyandalsotheST0IO1andST0IO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheSTMoutputpin.
ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheST0ONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,theST0ONbitcanalsobemade toautomaticallychangefromlowtohighusing theexternalSTCK0pin,whichwillinturninitiatetheSinglePulseoutput.WhentheST0ONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheST0ONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheST0ONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.
�/W Co��and �ET“�T0ON”
o��TCK0 Pin
T�ansition
T�ailing Edge
�/W Co��and CLR“�T0ON”
o�CCRA Co��a�e Match
�TP0/�TP0B Out�ut Pin
Pulse Width = CCRA Value
Leading Edge
�T0ON �it0 → 1
�T0ON �it1 → 0
Single Pulse Generation
Rev. 1.10 80 �e�te��e� 1�� �01� Rev. 1.10 81 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Counte� Value
CCRP
CCRA
�T0ON
�T0PAU
�T0POL
CCRP Int. Flag �TMP0F
CCRA Int. Flag �TMA0F
�TM O/P Pin(�T0OC=1)
Ti�e
Counte� sto��ed �y CCRA
PauseResu�e Counte� �to�s
�y softwa�e
Counte� Reset when �T0ON �etu�ns high
�T0M [1:0] = 10 ; �T0IO [1:0] = 11
Pulse Width set �y CCRA
Out�ut Inve�tswhen �T0POL = 1
No CCRP Inte��u�ts gene�ated
�TM O/P Pin(�T0OC=0)
�TCK0 �in
�oftwa�e T�igge�
Clea�ed �y CCRA �atch
�TCK0 �in T�igge�
Auto. set �y �TCK0 �in
�oftwa�e T�igge�
�oftwa�e Clea�
�oftwa�e T�igge��oftwa�e
T�igge�
Single Pulse ModeNote:1.CounterstoppedbyCCRAmatch
2.CCRPisnotused
3.ThepulseistriggeredbysettingtheST0ONbithigh
4.IntheSinglePulseMode,ST0IO[1:0]mustbesetto“11”andcannotbechanged.
HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheST0ONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaSTMinterrupt.ThecountercanonlyberesetbacktozerowhentheST0ONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheST0CCLRandST0DPXbitsarenotusedinthisMode.
Rev. 1.10 8� �e�te��e� 1�� �01� Rev. 1.10 83 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Capture Input ModeToselectthismodebitsST0M1andST0M0intheSTM0C1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheSTP0I,whoseactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheST0IO1andST0IO0bitsintheSTM0C1register.ThecounterisstartedwhentheST0ONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.Whentherequirededge transitionappearson theSTP0I thepresentvalue in thecounterwillbelatchedintotheCCRAregistersandaSTMinterruptgenerated.IrrespectiveofwhateventsoccurontheSTP0IthecounterwillcontinuetofreerununtiltheST0ONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aSTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheST0IO1andST0IO0bitscanselecttheactivetriggeredgeontheSTP0Itobearisingedge,fallingedgeorbothedgetypes.IftheST0IO1andST0IO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheSTP0I,howeveritmustbenotedthatthecounterwillcontinuetorun.
TheST0CCLRandST0DPXbitsarenotusedinthisMode.
Counte� Value
YY
CCRP
�T0ON
�T0PAU
CCRP Int. Flag �TMP0F
CCRA Int. Flag �TMA0F
CCRA Value
Ti�e
Counte� clea�ed �y CCRP
PauseResu�e
Counte� Reset
�T0M [1:0] = 01
�TM ca�tu�e �in �TP0I
XX
Counte� �to�
�T0IO [1:0] Value
XX YY XX YY
Active edge Active
edgeActive edge
00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disa�le Ca�tu�e
Capture Input ModeNote:1.ST0M[1:0]=01andactiveedgesetbytheST0IO[1:0]bits
2.ATMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.TheST0CCLRandST0DPXbitsarenotused4.Nooutputfunction–ST0OCandST0POLbitsarenotused5.CCRPdetermines thecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.
Rev. 1.10 8� �e�te��e� 1�� �01� Rev. 1.10 83 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Periodic Type TM – PTMThePeriodicTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.ThePeriodicTMcanalsobecontrolledwithtwoexternalinputpinsandcandrivetwoexternaloutputpins.
Device Name TM Input Pin TM Output Pin
HT66F003 10-�it PTM PTCK1� PTP1I PTP1�PTP1B
HT66F00� 10-�it PTM PTCK0� PTP0IPTCK1� PTP1I
PTP0�PTP0BPTP1�PTP1B
Periodic TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearetwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwiththeCCRAandCCRPregisters.
Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclearthecounterbychangingthePTnONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.ThePeriodicTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontroltheoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.
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Periodic Type TM Block Diagram (n=0 or 1)
Rev. 1.10 8� �e�te��e� 1�� �01� Rev. 1.10 85 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Periodic Type TM Register DescriptionOveralloperationofthePeriodicTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whiletworead/writeregisterpairsexisttostoretheinternal10-bitCCRAandCCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.
Register Name
Bit
7 6 5 4 3 2 1 0
PTMnC0 PTnPAU PTnCK� PTnCKn PTnCK0 PTnON — — —
PTMnCn PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCK� PTnCCLR
PTMnDL D7 D6 D5 D� D3 D� D1 D0
PTMnDH — — — — — — D� D8
PTMnAL D7 D6 D5 D� D3 D� D1 D0
PTMnAH — — — — — — D� D8
PTMnRPL D7 D6 D5 D� D3 D� D1 D0
PTMnRPH — — — — — — D� D8
10-bit Periodic TM Register List (n=0 or 1)
PTMnC0 Register
Bit 7 6 5 4 3 2 1 0
Na�e PTnPAU PTnCK� PTnCK1 PTnCK0 PTnON — — —
R/W R/W R/W R/W R/W R/W — — —
POR 0 0 0 0 0 — — —
Bit7 PTnPAU:PTMCounterPauseControl0:run1:pause
Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.
Bit6~4 PTnCK2~PTnCK0:SelectPTMCounterclock000:fSYS/4001:fSYS
010:fH/16011:fH/64100:fTBC101:fTBC110:PTCKnrisingedgeclock111:PTCKnfallingedgeclock
ThesethreebitsareusedtoselecttheclocksourcefortheTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefTBCisanotherinternalclock,thedetailsofwhichcanbefoundintheoscillatorsection.
Rev. 1.10 8� �e�te��e� 1�� �01� Rev. 1.10 85 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Bit3 PTnON:PTMCounterOn/OffControl0:Off1:On
Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheTMOutputcontrolbit,whenthebitchangesfromlowtohigh.
Bit2~0 Unimplemented,readas“0”
PTMnC1 Register
Bit 7 6 5 4 3 2 1 0
Na�e PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCK� PTnCCLR
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit7~6 PTnM1~ PTnM0:SelectPTMOperationMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode
ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremade to thePTnM1andPTnM0bits.IntheTimer/CounterMode,thePTMoutputpinstateisundefined.
Bit5~4 PTnIO1~ PTnIO0:SelectPTMoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput
PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput
CaptureInputMode00:InputcaptureatrisingedgeofPTPnI01:InputcaptureatfallingedgeofPTPnI10:Inputcaptureatfalling/risingedgeofPTPnI11:Inputcapturedisabled
Timer/counterModeUnused
ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.
Rev. 1.10 86 �e�te��e� 1�� �01� Rev. 1.10 87 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
In theCompareMatchOutputMode, thePTnIO1andPTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccurs fromtheComparatorA.When thesebitsarebothzero,thennochangewill takeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingthePTnOCbit.NotethattheoutputlevelrequestedbythePT1IO1andPTnIO0bitsmustbedifferentfromtheinitialvaluesetupusingthePTnOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstate,itcanberesettoitsinitiallevelbychangingthelevelofthePTnONbitfromlowtohigh.InthePWMMode,thePTnIO1andPTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytochangethevaluesofthePTnIO1andPTnIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurifthePTnIO1andPTnIO0bitsarechangedwhentheTMisrunning.
Bit3 PTnOC:PTPn/PTPnBOutputcontrolbitCompareMatchOutputMode0:initiallow1:initialhigh
PWMMode/SinglePulseOutputMode0:Activelow1:Activehigh
This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode/SinglePulseOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalisactivehighoractivelow.
Bit2 PTnPOL:PTPn/PTPnBOutputpolarityControl0:non-invert1:invert
ThisbitcontrolsthepolarityofthePTPn/PTPnBoutputpin.WhenthebitissethightheTMoutputpinwillbe invertedandnot invertedwhenthebit iszero.IthasnoeffectiftheTMisintheTimer/CounterMode.
Bit1 PTnCKS:PTMcapturetriggersourceselect0:FromPTPnI1:FromPTCKnpin
Bit0 PTnCCLR:SelectPTMCounterclearcondition0:PTMComparatrorPmatch1:PTMComparatrorAmatch
Thisbit isused toselect themethodwhichclears thecounter.Remember that thePeriodicTMcontains twocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtocleartheinternalcounter.WiththePTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.ThePTnCCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.
Rev. 1.10 86 �e�te��e� 1�� �01� Rev. 1.10 87 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
PTMnDL Register
Bit 7 6 5 4 3 2 1 0
Na�e D7 D6 D5 D� D3 D� D1 D0
R/W R R R R R R R R
POR 0 0 0 0 0 0 0 0
Bit7~0 PTMnDL:PTMCounterLowByteRegisterbit7~bit0PTM10-bitCounterbit7~bit0
PTMnDH Register
Bit 7 6 5 4 3 2 1 0
Na�e — — — — — — D� D8
R/W — — — — — — R R
POR — — — — — — 0 0
Bit7~2 Unimplemented,readas“0”Bit1~0 PTMnDH:PTMCounterHighByteRegisterbit1~bit0
PTM10-bitCounterbit9~bit8
PTMnAL Register
Bit 7 6 5 4 3 2 1 0
Na�e D7 D6 D5 D� D3 D� D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit7~0 PTMnAL:PTMCCRALowByteRegisterbit7~bit0PTM10-bitCCRAbit7~bit0
PTMnAH Register
Bit 7 6 5 4 3 2 1 0
Na�e — — — — — — D� D8
R/W — — — — — — R/W R/W
POR — — — — — — 0 0
Bit7~2 Unimplemented,readas“0”Bit1~0 PTMnAH:PTMCCRAHighByteRegisterbit1~bit0
PTM10-bitCCRAbit9~bit8
PTMnRPL Register
Bit 7 6 5 4 3 2 1 0
Na�e D7 D6 D5 D� D3 D� D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit7~0 PTMnRPL:PTMCCRPLowByteRegisterbit7~bit0PTM10-bitCCRPbit7~bit0
Rev. 1.10 88 �e�te��e� 1�� �01� Rev. 1.10 8� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
PTMnRPH Register
Bit 7 6 5 4 3 2 1 0
Na�e — — — — — — D� D8
R/W — — — — — — R/W R/W
POR — — — — — — 0 0
Bit7~2 Unimplemented,readas"0"Bit1~0 PTMnRPH:PTMCCRPHighByteRegisterbit1~bit0
PTM10-bitCCRPbit9~bit8
Periodic Type TM Operating ModesThePeriodicTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingthePTnM1andPTnM0bitsinthePTMnC1register.
Compare Match Output ModeToselect thismode,bitsPTnM1andPTnM0in thePTMnC1register, shouldbeallcleared to00respectively.In thismodeoncethecounter isenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhenthePTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HereboththePTMAnFandPTMPnFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.
IfthePTnCCLRbitinthePTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonly thePTMAnFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenPTnCCLRishighnoPTMPnF interrupt request flagwillbegenerated. In theCompareMatchOutputMode,theCCRAcannotbesetto“0”.IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,value,howeverherethePTMAnFinterruptrequestflagwillnotbegenerated.
Asthenameofthemodesuggests,afteracomparisonismade,theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaPTMAnFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.ThePTMPnFinterruptrequestflag,generatedfromacomparematchfromComparatorP,willhavenoeffectontheTMoutputpin.ThewayinwhichtheTMoutputpinchangesstatearedeterminedbytheconditionofthePTnIO1andPTnIO0bits in thePTMnC1register.TheTMoutputpincanbeselectedusing thePTnIO1andPTnIO0bits togohigh, togo lowor to togglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionoftheTMoutputpin,whichissetupafterthePTnONbitchangesfromlowtohigh,issetupusingthePTnOCbit.Notethatif thePTnIO1,PTnIO0bitsarezerothennopinchangewilltakeplace.
Rev. 1.10 88 �e�te��e� 1�� �01� Rev. 1.10 8� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Counte� Value
0x3FF
CCRP
CCRA
PTnON
PTnPAU
PTnPOL
CCRP Int. Flag PTMPnF
CCRA Int. Flag PTMAnF
PTM O/P Pin
Ti�e
CCRP=0
CCRP > 0
Counte� ove�flowCCRP > 0Counte� clea�ed �y CCRP value
Pause
Resu�e
�to�
Counte� Resta�t
PTnCCLR = 0; PTnM [1:0] = 00
Out�ut �in set to initial Level Low if PTnOC=0
Out�ut Toggle with PTMAnF flag
Note PTnIO [1:0] = 10 Active High Out�ut selectHe�e PTnIO [1:0] = 11
Toggle Out�ut select
Out�ut not affected �y PTMAnF flag. Re�ains High until �eset �y PTnON �it
Out�ut PinReset to Initial value
Out�ut cont�olled �y othe� �in-sha�ed function
Out�ut Inve�tswhen PTnPOL is high
Compare Match Output Mode – PTnCCLR = 0 (n=0 or 1)Note:1.WithPTnCCLR=0–aComparatorPmatchwillclearthecounter
2.TheTMoutputpiniscontrolledonlybythePTMAnFflag
3.TheoutputpinisresettoinitialstatebyaPTnONbitrisingedge
Rev. 1.10 �0 �e�te��e� 1�� �01� Rev. 1.10 �1 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Counte� Value
0x3FF
CCRP
CCRA
PTnON
PTnPAU
PTnPOL
CCRP Int. Flag PTMPnF
CCRA Int. Flag PTMAnF
PTM O/P Pin
Ti�e
CCRA=0
CCRA = 0Counte� ove�flowCCRA > 0 Counte� clea�ed �y CCRA value
Pause
Resu�e
�to� Counte� Resta�t
PTnCCLR = 1; PTnM [1:0] = 00
Out�ut �in set to initial Level Low if PTnOC=0
Out�ut Toggle with PTMAnF flag
Note PTnIO [1:0] = 10 Active High Out�ut selectHe�e PTnIO [1:0] = 11
Toggle Out�ut select
Out�ut not affected �y TnAF flag. Re�ains High until �eset �y PTnON �it
Out�ut PinReset to Initial value
Out�ut cont�olled �y othe� �in-sha�ed function
Out�ut Inve�tswhen PTnPOL is high
PTMPnF not gene�ated
No PTMAnF flag gene�ated on CCRA ove�flow
Out�ut does not change
Compare Match Output Mode – PTnCCLR = 1 (n=0 or 1)Note:1.WithPTnCCLR=1–aComparatorAmatchwillclearthecounter
2.TheTMoutputpiniscontrolledonlybythePTMAnFflag
3.TheoutputpinisresettoinitialstatebyaPTnONrisingedge
4.ThePTMPnFflagisnotgeneratedwhenPTnCCLR=1
Rev. 1.10 �0 �e�te��e� 1�� �01� Rev. 1.10 �1 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Timer/Counter ModeToselect thismode,bitsPTnM1andPTnM0 in thePTMnC1register shouldallbe set to11respectively.TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputModegenerating thesameinterruptflags.Theexception is that in theTimer/CounterModetheTMoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.
PWM Output ModeToselectthismode,bitsPTnM1andPTnM0inthePTMnC1registershouldbesetto10respectivelyandalsothePTnIO1andPTnIO0bitsshouldbesetto10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.
AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMmode,thePTnCCLRbithasnoeffectasthePWMperiod.BothoftheCCRPandCCRAregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.
Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.ThePTnOCbitinthePTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoPTnIO1andPTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.ThePTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.
10-bit PWM Mode, Edge-aligned ModeCCRP CCRP = 0~1024
Pe�iod CCRP=0 : �e�iod= 10�� clocksCCRP=1~10�3: �e�iod=1~10�3 clocks
Duty CCRA
IffSYS=16MHz,PTMclocksourceselectfSYS/4,CCRP=100bandCCRA=128,
ThePTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%
IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.
Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Counte� Value
CCRP
CCRA
PTnON
PTnPAU
PTnPOL
CCRP Int. Flag PTMPnF
CCRA Int. Flag PTMAnF
PTM O/P Pin(PTnOC=1)
Ti�e
Counte� clea�ed �y CCRP
Pause Resu�e Counte� �to� if PTnON �it low
Counte� Reset when PTnON �etu�ns high
PTnDPX = 0; PTnM [1:0] = 10
PWM Duty Cycle set �y CCRA
PWM �esu�es o�e�ation
Out�ut cont�olled �y othe� �in-sha�ed function Out�ut Inve�ts
When PTnPOL = 1PWM Pe�iod set �y CCRP
PTM O/P Pin(PTnOC=0)
PWM Output Mode (n=0 or 1)Note:1.HereCounterclearedbyCCRP
2.AcounterclearsetsthePWMPeriod
3.TheinternalPWMfunctioncontinuesrunningevenwhenPTnIO[1:0]=00or01
4.ThePTnCCLRbithasnoinfluenceonPWMoperation
Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Single Pulse Output ModeToselectthismode,therequiredbitpairs,PTnM1andPTnM0shouldbesetto10respectivelyandalsothecorrespondingPTnIO1andPTnIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.
ThetriggerforthepulseoutputleadingedgeisalowtohightransitionofthePTnONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,thePTnONbitcanalsobemade toautomaticallychangefromlowtohighusing theexternalPTCKnpin,whichwillinturninitiatetheSinglePulseoutput.WhenthePTnONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.ThePTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhenthePTnONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.
HoweveracomparematchfromComparatorAwillalsoautomaticallyclearthePTnONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateTMinterrupts.ThecountercanonlyberesetbacktozerowhenthePTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.ThePTnCCLRbitisalsonotused.
�/W Co��and �ET“PTnON”
o�PTCKn Pin
T�ansition
T�ailing Edge
�/W Co��and CLR“PTnON”
o�CCRA Co��a�e Match
PTPn/PTPnB Out�ut Pin
Pulse Width = CCRA Value
Leading Edge
PTnON �it0 → 1
PTnON �it1 → 0
Single Pulse Generation (n=0 or 1)
Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Counte� Value
CCRP
CCRA
PTnON
PTnPAU
PTnPOL
CCRP Int. Flag PTMPnF
CCRA Int. Flag PTMAnF
PTM O/P Pin(PTnOC=1)
Ti�e
Counte� sto��ed �y CCRA
PauseResu�e Counte� �to�s
�y softwa�e
Counte� Reset when PTnON �etu�ns high
PTnM [1:0] = 10 ; PTnIO [1:0] = 11
Pulse Width set �y CCRA
Out�ut Inve�tswhen PTnPOL = 1
No CCRP Inte��u�ts gene�ated
PTM O/P Pin(PTnOC=0)
PTCKn �in
�oftwa�e T�igge�
Clea�ed �y CCRA �atch
PTCKn �in T�igge�
Auto. set �y PTCKn �in
�oftwa�e T�igge�
�oftwa�e Clea�
�oftwa�e T�igge��oftwa�e
T�igge�
Single Pulse Mode Note:1.CounterstoppedbyCCRA
2.CCRPisnotused
3.ThepulseistriggeredbythePTCKnpinorbysettingthePTnONbithigh
4.APTCKnpinactiveedgewillautomaticallysetthePTnONbithigh
5.IntheSinglePulseMode,PTnIO[1:0]mustbesetto“11”andcannotbechanged.
Rev. 1.10 �� �e�te��e� 1�� �01� Rev. 1.10 �5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Capture Input ModeToselectthismodebitsPTnM1andPTnM0inthePTMnC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedonthePTPnIorPTCKnpin,selectedbythePTnCKSbitinthePTMnC1register.Theinputpinactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingthePTnIO1andPTnIO0bitsinthePTMnC1register.ThecounterisstartedwhenthePTnONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.
WhentherequirededgetransitionappearsonthePTPnIorPTCKnpin thepresentvalue in thecounterwillbelatchedintotheCCRAregisterandaTMinterruptgenerated.IrrespectiveofwhateventsoccuronthePTPnIorPTCKnpinthecounterwillcontinuetofreerununtilthePTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;in thiswaytheCCRPvaluecanbeusedtocontrol themaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.ThePTnIO1andPTnIO0bitscanselecttheactivetriggeredgeonthePTPnIorPTCKnpintobearisingedge,fallingedgeorbothedgetypes.IfthePTnIO1andPTnIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensonthePTPnIorPTCKnpin,howeveritmustbenotedthatthecounterwillcontinuetorun.
AsthePTPnIorPTCKnpinispinsharedwithotherfunctions,caremustbetakenifthePTMisintheCaptureInputMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.ThePTnCCLR,PTnOCandPTnPOLbitsarenotusedinthisMode.
Rev. 1.10 �6 �e�te��e� 1�� �01� Rev. 1.10 �7 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Counte� Value
YY
CCRP
PTnON
PTnPAU
CCRP Int. Flag PTMPnF
CCRA Int. Flag PTMAnF
CCRA Value
Ti�e
Counte� clea�ed �y CCRP
PauseResu�e
Counte� Reset
PTnM [1:0] = 01
PTM ca�tu�e �in PTPnIo� PTCKn
XX
Counte� �to�
PTnIO [1:0] Value
XX YY XX YY
Active edge Active
edgeActive edge
00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disa�le Ca�tu�e
Capture Input Mode (n=0 or 1)Note:1.PTnM[1:0]=01andactiveedgesetbythePTnIO[1:0]bits
2.ATMCaptureinputpinactiveedgetransferscountervaluetoCCRA
3.ThePTnCCLRbitisnotused
4.Nooutputfunction–PTnOCandPTnPOLbitsarenotused
5.CCRPdetermines thecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero
Rev. 1.10 �6 �e�te��e� 1�� �01� Rev. 1.10 �7 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Analog to Digital ConverterTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.
A/D OverviewThedevicescontainamulti-channelanalog todigital converterwhichcandirectly interfacetoexternalanalogsignals, suchas that fromsensorsorothercontrolsignalsandconvert thesesignalsdirectlyintoa12-bitdigitalvalue.TheexternalorinternalanalogsignaltobeconvertedisdeterminedbytheSAINSandSACSbitfields.Notethatwhentheinternalanalogsignalistobeconverted, thepin-sharedcontrolbitsshouldalsobeproperlyconfiguredexcept theSAINSandSACSbit fields.Moredetailedinformationabout theA/Dinputsignal isdescribedin the“A/DConverterControlRegisters”and“A/DConverterInputSignal”sectionsrespectively.
Part No. Input Channels A/D Channel Select Bits Input Pins
HT66F00�/HT66F003 � �AIN��~�AIN�0��AC�1~�AC�0 AN0~AN3
HT66F00� 8 �AIN��~�AIN�0��AC��~�AC�0 AN0~AN7
TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.
AN0AN5AN6AN7
1�-�it �AR ADC
ENADC
�ADOH[7:0]�ADOL[7:0]
ADBZ
�AINT
�AC�[�:0]
VBG(1.0�V)
VREFVRI
Divide� f�Y�
�ACK�[�:0]
AVDD
�AVR�[3:0]
VR
VREFO
�AIN�[�:0]
�APIN
VREFO
ENOPAPA�R
OPA
MUX
Pin-sha�ed selection
AVDD
VR
A/D Converter Structure
Rev. 1.10 98 September 19, 2014 Rev. 1.10 99 September 19, 2014
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
A/D Converter Register DescriptionOverall operation of the A/D converter is controlled using five registers. A read only register pair exists to store the ADC data 12-bit value. The remaining three registers are control registers which setup the operating and control function of the A/D converter.
NameBit
7 6 5 4 3 2 1 0SADOL (ADRFS=0) D3 D2 D1 D0 — — — —
SADOL (ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0
SADOH (ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4
SADOH (ADRFS=1) — — — — D11 D10 D9 D8
SADC0 START ADBZ ENADC ADRFS — — SACS1 SACS0SADC1 SAINS2 SAINS1 SAINS0 — — SACK2 SACK1 SACK0SADC2 ENOPA VBGEN — — SAVRS3 SAVRS2 SAVRS1 SAVRS0
A/D Converter Register List – HT66F002/HT66F003
NameBit
7 6 5 4 3 2 1 0SADOL (ADRFS=0) D3 D2 D1 D0 — — — —
SADOL (ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0
SADOH (ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4
SADOH (ADRFS=1) — — — — D11 D10 D9 D8
SADC0 START ADBZ ENADC ADRFS — SACS2 SACS1 SACS0SADC1 SAINS2 SAINS1 SAINS0 — — SACKS2 SACKS1 SACKS0SADC2 ENOPA VBGEN — — SAVRS3 SAVRS2 SAVRS1 SAVRS0
A/D Converter Register List – HT66F004
A/D Converter Data Registers – SADOL, SADOHAs the devices contain an internal 12-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as SADOH, and a low byte register, known as SADOL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the SADC0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. Note that the A/D converter data register contents will not be cleared to zero if the A/D converter is disabled.
ADRFSSADOH SADOL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 00 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 01 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A/D Data Registers
Rev. 1.10 98 September 19, 2014 Rev. 1.10 99 September 19, 2014
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
A/D Converter Control Registers – SADC0, SADC1, SADC2, PASR, PBSRTo control the function and operation of the A/D converter, several control registers known as SADC0, SADC1 and SADC2 are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter busy status. The SACS2~SACS0 bits in the SADC0 register are used to determine which external channel input is selected to be converted. The SAINS2~SAINS0 bits in the SADC1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. If the SAINS2~SAINS0 bits are set to “000”, the external analog channel input is selected to be converted and the SACS2~SACS0 bits can determine which external channel is selected to be converted. If the SAINS2~SAINS0 bits are set to “001~011”, the AVDD voltage is selected to be converted. If the SAINS2~SAINS0 bits are set to “101~111”, the OPA output voltage is selected to be converted. When VREF or VBG is selected as ADC input or ADC reference voltage, the OPA needs to be enabled by setting ENOPA to 1.
Note that when the programs select external signal and internal signal as an ADC input signal simultaneously, then the hardware will only choose the internal signal as an ADC input. In addition, if the programs select external reference voltage VREF and the internal reference voltage VBG as ADC reference voltage, then the hardware will only choose the internal reference voltage VBG as an ADC reference voltage input.
The pin-shared function control registers, named PASR and PBSR, contain the corresponding pin-shared selection bits which determine which pins on Port A and Port B are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an A/D input.
Rev. 1.10 100 �e�te��e� 1�� �01� Rev. 1.10 101 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
SADC0 Register – HT66F002/HT66F003Bit 7 6 5 4 3 2 1 0
Na�e �TART ADBZ ENADC ADRF� — — �AC�1 �AC�0R/W R/W R R/W R/W — — R/W R/WPOR 0 0 0 0 — — 0 0
Bit7 START:StarttheA/Dconversion0→1→0:StartA/Dconversion0→1:ResettheA/DconverterandsetADBZto01→0:StartA/DconversionandsetADBZto1
Bit6 ADBZ:ADCbusyflag0:A/Dconversionendedornoconversion1:A/Disbusy
Bit5 ENADC:ADCenable/disablecontrolregister0:ADCdisable1:ADCenable
Bit4 ADRFS:A/Doutputdataformatselectionbit0:ADCoutputdataformat→SADOH=D[11:4];SADOL=D[3:0]1:ADCoutputdataformat→SADOH=D[11:8];SADOL=D[7:0]
Bit3~2 Unimplemented,readas"0"Bit1~0 SACS1~SACS0:ADCinputchannelsselection
00:ADCinputchannelcomesfromAN001:ADCinputchannelcomesfromAN110:ADCinputchannelcomesfromAN211:ADCinputchannelcomesfromAN3
SADC0 Register – HT66F004Bit 7 6 5 4 3 2 1 0
Na�e �TART ADBZ ENADC ADRF� — �AC�� �AC�1 �AC�0R/W R/W R R/W R/W — R/W R/W R/WPOR 0 0 0 0 — 0 0 0
Bit7 START:StarttheA/Dconversion0→1→0:StartA/Dconversion0→1:ResettheA/DconverterandsetADBZto01→0:StartA/DconversionandsetADBZto1
Bit6 ADBZ:ADCbusyflag0:A/Dconversionendedornoconversion1:A/Disbusy
Bit5 ENADC:ADCenable/disablecontrolregister0:ADCdisable1:ADCenable
Bit4 ADRFS:A/Doutputdataformatselectionbit0:ADCoutputdataformat→SADOH=D[11:4];SADOL=D[3:0]1:ADCoutputdataformat→SADOH=D[11:8];SADOL=D[7:0]
Bit3~2 Unimplemented,readas“0”Bit1~0 SACS2~SACS0:ADCinputchannelsselection
000:ADCinputchannelcomesfromAN0001:ADCinputchannelcomesfromAN1010:ADCinputchannelcomesfromAN2011:ADCinputchannelcomesfromAN3100:ADCinputchannelcomesfromAN4101:ADCinputchannelcomesfromAN5110:ADCinputchannelcomesfromAN6111:ADCinputchannelcomesfromAN7
Rev. 1.10 100 �e�te��e� 1�� �01� Rev. 1.10 101 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
SADC1 RegisterBit 7 6 5 4 3 2 1 0
Na�e �AIN�� �AIN�1 �AIN�0 — — �ACK�� �ACK�1 �ACK�0R/W R/W R/W R/W — — R/W R/W R/WPOR 0 0 0 — — 0 0 0
Bit7~5 SAINS2~SAINS0:InternalADCinputchannelselectionbit000:ADCinputonlycomesfromexternalpin001:ADCinputalsocomesfromAVDD
010:ADCinputalsocomesfromAVDD/2011:ADCinputalsocomesfromAVDD/4101:ADCinputalsocomesfromVR
110:ADCinputalsocomesfromVR/2111:ADCinputalsocomesfromVR/4OtherValues:sameas000
Note:VRisOPAoutputvoltage.VRcanbeoneofVREF/VREF×2/VREF×3/VREF×4/VBG×2/VBG×3/VBG×4.
Bit4~3 Unimplemented,readas"0"Bit2~0 SACKS2~SACKS0:ADCclockrateselectionbit
000:SACLK=fSYS
001:SACLK=fSYS/2010:SACLK=fSYS/4011:SACLK=fSYS/8100:SACLK=fSYS/16101:SACLK=fSYS/32110:SACLK=fSYS/64111:SACLK=fSYS/128
Rev. 1.10 10� �e�te��e� 1�� �01� Rev. 1.10 103 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
SADC2 RegisterBit 7 6 5 4 3 2 1 0
Na�e ENOPA VBGEN — — �AVR�3 �AVR�� �AVR�1 �AVR�0R/W R/W R/W — — R/W R/W R/W R/WPOR 0 0 — — 0 0 0 0
Bit7 ENOPA:OPAenable/disablecontrolregister0:OPAdisable1:OPAenable
Bit6 VBGEN:Bandgapbufferdisable/enablecontrolbit0:Bandgapbufferdisable1:Bandgapbufferenable
Bit5~4 Unimplemented,readas"0"Bit3~0 SAVRS3~SAVRS0:ADCreferencevoltageselectionbit
0000:ADCreferencevoltagecomesfromAVDD
0001:ADCreferencevoltagecomesfromVREF
0010:ADCreferencevoltagecomesfromVREF×20011:ADCreferencevoltagecomesfromVREF×30100:ADCreferencevoltagecomesfromVREF×41001:Inhibittouse1010:ADCreferencevoltagecomesfromVBG×21011:ADCreferencevoltagecomesfromVBG×31100:ADCreferencevoltagecomesfromVBG×4OtherValues:sameas0000
Note:(1)WhenSelectVREForVREF×2orVREF×3orVREF×4asADCreferencevoltage,HT66F002:pinsharecontrolbits(PAS3,PAS2)is(1,0)toselectVREFasinput.HT66F003:pinsharecontrolbits(PAS2,PAS1)is(1,0)toselectVREFasinput.HT66F004:pinsharecontrolbits(PAS3,PAS2)is(1,0)toselectVREFasinput
(2)VBG=1.04V(3)WhenSAVRS3=1,OPAselectsVBGasinput.(4) If theprogramsselectexternal referencevoltageVREFand the internal
referencevoltageVBGasADCreferencevoltage,thenthehardwarewillonlychoosetheinternalreferencevoltageVBGasanADCreferencevoltageinput.
A/D OperationTheSTARTbitisusedtostartandresettheA/Dconverter.Whenthemicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,theADBZbitintheSADC0registerwillbeclearedtozeroandtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigitalconverter.
TheADBZbit intheSADC0registerisusedtoindicatewhethertheanalogtodigitalconversionprocess is inprocessornot.When theA/Dconverter is resetbysetting theSTARTbit fromlowtohigh, theADBZflagwillbeclearedto0.Thisbitwillbeautomaticallyset to“1”bythemicrocontrollerafteranA/Dconversion issuccessfully initiated.When theA/Dconversion iscomplete,theADBZwillbeclearedto0.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andiftheinterruptsareenabled,anappropriateinternalinterruptsignalwillbegenerated.ThisA/DinternalinterruptsignalwilldirecttheprogramflowtotheassociatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontrollercanbeusedtopolltheADBZbitintheSADC0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.
Rev. 1.10 10� �e�te��e� 1�� �01� Rev. 1.10 103 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsSACK2~SACK0,therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.AstherecommendedvalueofpermissibleA/Dclockperiod, tADCK, isfrom0.5μsto10μs,caremustbetakenforsystemclockfrequencies.Forexample, if thesystemclockoperatesatafrequencyof4MHz,theSACK2~SACK0bitsshouldnotbesetto000Bor11xB.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.
Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theENADCbitintheSADC0register.ThisbitmustbesethightopowerontheA/Dconverter.WhentheENADCbit issethigh topoweron theA/Dconverter internalcircuitryacertaindelay,asindicatedinthetimingdiagram,mustbeallowedbeforeanA/Dconversionisinitiated.EvenifnopinsareselectedforuseasA/Dinputsbyconfiguringthecorrespondingpin-sharedcontrolbits,iftheENADCbitishighthensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheENADCissetlowtoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.
ThereferencevoltagesupplytotheA/DConvertercanbesuppliedfromeithertheinternalADCpowerorfromanexternalreferencesourcessuppliedonpinVREForVBGvoltage.ThedesiredselectionismadeusingtheSAVRS3~SAVRS0bits.AstheVREFpinispin-sharedwithotherfunctions,whentheVREFpinisselectedasthereferencevoltagesupplypin,theVREFpin-sharedfunctioncontrolbitsshouldbeproperlyconfiguredtodisableotherpinfunctions.WhenVREForVBGisselectedbyADCinputorADCreferencevoltage,theOPAneedstobeenabledbysettingENOPA=1.
Reference SAVRS[3:0] Description
AVDD 0000 ADC Refe�ence Voltage co�es f�o� AVDD
VREF 0001 ADC Refe�ence Voltage co�es f�o� Exte�nal VREF
VREF×� 0010 ADC Refe�ence Voltage co�es f�o� Exte�nal VREF×�VREF×3 0011 ADC Refe�ence Voltage co�es f�o� Exte�nal VREF×3VREF×� 0100 ADC Refe�ence Voltage co�es f�o� Exte�nal VREF×�VBG×� 1010 ADC Refe�ence Voltage co�es f�o� VBG×�VBG×3 1011 ADC Refe�ence Voltage co�es f�o� VBG×3VBG×� 1100 ADC Refe�ence Voltage co�es f�o� VBG×�
A/D Converter Reference Voltage Selection
A/D Converter Input SignalAlloftheA/Danaloginputpinsarepin-sharedwiththeI/OpinsonPortAandPortBaswellasotherfunctions.ThecorredpondingselectionbitsforeachI/OpininthePASRandPBSRregisters,determinewhether theinputpinsaresetupasA/Dconverteranaloginputsorwhether theyhaveotherfunctions.If thepin-sharedfunctioncontrolbitsconfigureitscorrespondingpinasanA/Danalogchannelinput, thepinwillbesetuptobeanA/Dconverterexternalchannelinputandtheoriginalpinfunctionsdisabled.Inthisway,pinscanbechangedunderprogramcontroltochangetheir functionbetweenA/Dinputsandother functions.Allpull-highresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnected if thepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputinthePACandPBCportcontrolregistertoenabletheA/Dinputaswhenthepin-sharedfunctioncontrolbitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.
TheA/Dconverterhas itsownreferencevoltagepin,VREF,however thereferencevoltagecanalsobesuppliedfromthepowersupplypin,achoicewhichismadethroughtheSAVRS[3:0]intheSADC2register.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueofVREF.
Rev. 1.10 10� �e�te��e� 1�� �01� Rev. 1.10 105 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Conversion Rate and Timing DiagramAcompleteA/Dconversioncontains twoparts,data samplinganddataconversion.ThedatasamplingwhichisdefinedastADStakes4A/Dclockcyclesandthedataconversiontakes12A/Dclockcycles.Thereforeatotalof16A/DclockcyclesforanA/DconversionwhichisdefinedastADCarenecessary.
MaximumsingleA/Dconversionrate=A/Dclockperiod/16
However, there isausagelimitationonthenextA/Dconversionafter thecurrentconversioniscomplete.WhenthecurrentA/Dconversioniscomplete, theconverteddigitaldatawillbestoredintheA/DdataregisterpairandthenlatchedafterhalfanA/Dclockcycle.IftheSTARTbitissetto1inhalfanA/DclockcycleaftertheendofA/Dconversion,theconverteddigitaldatastoredintheA/Ddataregisterpairwillbechanged.Therefore,itisrecommendedtoinitiatethenextA/DconversionafteracertainperiodgreaterthanhalfanA/Dclockcycle attheendofcurrentA/Dconversion.
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A/D Conversion Timing
Rev. 1.10 10� �e�te��e� 1�� �01� Rev. 1.10 105 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.
• Step1SelecttherequiredA/DconversionfrequencybySACKS2~SACKS0
• Step2EnabletheADCbysetENADC=1
• Step3SelectwhichpinswillbeconfigureasADCanaloginputs
• Step4IfinputcomesfromI/O,setSAINS[2:0]=000andthensetSACSbitfieldstocorrespondingPADinputIfinputcomesfrominternalinput,setSAINS[2:0]tocorrespondinginternalinputsource
• Step5SelectreferencevoltagecomesfromexternalVREF,AVDDorVBGbySAVRS[3:0]Note:(1)IfselectVREFasreferencevoltage,(PAS3,PAS2)=(1,0)forHT66F002/HT66F004(2)IfselectVREFasreferencevoltage,(PAS2,PAS1)=(1,0)forHT66F003
• Step6SelectADCoutputdataformatbyADRFS
• Step7IfADCinterruptisused,theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconverterinterruptbits,ADE,mustbothsethighinadvance.
• Step8TheA/DconvertprocedurecannowbeinitializedbysetSTARTfromlowtohighandthenlowagain
• Step9IfADCisunderconversion,ADBZ=1.AfterA/Dconversionprocessiscompleted,theADBZflagwillgolow,andthenoutputdatacanbereadfromSADOHandSADOLregisters.If theADCinterrupt isenabledandthestack isnotfull,datacanbeacquiredby interruptserviceprogram.AnotherwaytogettheA/DoutputdataispollingtheADBZflag.
Rev. 1.10 106 �e�te��e� 1�� �01� Rev. 1.10 107 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,byclearing theENADCbit in theSADC0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.
A/D Transfer FunctionAsthedevicescontaina12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequaltotheVDDorVREFvoltage,thisgivesasinglebitanaloginputvalueofVDDorVREFdividedby4096.
1LSB=(AVDDorVREF)/4096
TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:
A/Dinputvoltage=A/Doutputdigitalvalue×(AVDDorVREF)/4096
Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVDDorVREFlevel.
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Ideal A/D Transfer Function
Rev. 1.10 106 �e�te��e� 1�� �01� Rev. 1.10 107 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
A/D Programming ExamplesThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheADBZbit intheSADC0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.
Example: using an EOCB polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a,0BHmov SADC1,a ; select fSYS/8 as A/D clock and switch off the bandgap reference voltageset ENADCmov a,03h ; setup PASR to configure pin AN0mov PASR,amov a,20hmov SADC0,a ; enable and connect AN0 channel to A/D converter:start_conversion:clr START ; high pulse on start bit to initiate conversionset START ; reset A/Dclr START ; start A/Dpolling_EOC:sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversionjmp polling_EOC ; continue pollingmov a,SADOL ; read low byte conversion result valuemov SADOL_buffer,a ; save result to user defined registermov a,SADOH ; read high byte conversion result valuemov SADOH_buffer,a ; save result to user defined register::jmp start_conversion ; start next a/d conversion
Rev. 1.10 108 �e�te��e� 1�� �01� Rev. 1.10 10� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Example: using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a,0BHmov SADC1,a ; select fSYS/8 as A/D clock and switch off the bandgap reference voltageset ENADCmov a,03h ; setup PASR to configure pin AN0mov PASR,amov a,20hmov SADC0,a ; enable and connect AN0 channel to A/D converterStart_conversion:clr START ; high pulse on START bit to initiate conversionset START ; reset A/Dclr START ; start A/Dclr ADF ; clear ADC interrupt request flagset ADE ; enable ADC interruptset EMI ; enable global interrupt::; ADC interrupt service routineADC_ISR:mov acc_stack,a ; save ACC to user defined memorymov a,STATUSmov status_stack,a ; save STATUS to user defined memory::mov a,SADOL ; read low byte conversion result valuemov SADOL_buffer,a ; save result to user defined registermov a,SADOH ; read high byte conversion result valuemov SADOH_buffer,a ; save result to user defined register::EXIT_INT_ISR:mov a,status_stackmov STATUS,a ; restore STATUS from user defined memorymov a,acc_stack ; restore ACC from user defined memoryreti
Rev. 1.10 108 �e�te��e� 1�� �01� Rev. 1.10 10� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontroller todirectattentiontotheirrespectiveneeds.Thedevicescontainseveralexternalinterruptsandinternal interruptsfunctions.Theexternal interruptsaregeneratedbytheactionoftheexternalINT0~INT1andINTpin,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchastheTMs,TimeBase,EEPROMandtheA/Dconverter.
Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.Thenumberofregistersdependsuponthedevicechosenbutfall intothreecategories.ThefirstistheINTC0~INTC1registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI1registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEGregistertosetuptheexternalinterrupttriggeredgetype.
Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.
Function Enable Bit Request Flag NotesGlo�al EMI — —INT Pin INTE INTF —
A/D Conve�te� ADE ADF —Multi-function MF0E MF0F —
Ti�e Base TBnE TBnF n=0 o� 1EEPROM DEE DEF —
TM�TMA0E �TMA0F
—�TMP0E �TMP0F
Interrupt Register Bit Naming Conventions – HT66F002
Function Enable Bit Request Flag NotesGlo�al EMI — —INT Pin INTE INTF —
A/D Conve�te� ADE ADF —Multi-function MFnE MFnF n=0 o� 1
Ti�e Base TBnE TBnF n=0 o� 1EEPROM DEE DEF —
TM
�TMA0E �TMA0F
—�TMP0E �TMP0FPTMA1E PTMA1FPTMP1E PTMP1F
Interrupt Register Bit Naming Conventions – HT66F003
Rev. 1.10 110 �e�te��e� 1�� �01� Rev. 1.10 111 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Function Enable Bit Request Flag NotesGlo�al EMI — —
INTn Pin INTnE INTnF n=0 o� 1A/D Conve�te� ADE ADF —Multi-function MF0E MF0F —
Ti�e Base TBnE TBnF n=0 o� 1EEPROM DEE DEF —
TMPTMAnE PTMAnF
n=0 o� 1PTMPnE PTMPnF
Interrupt Register Bit Naming Conventions – HT66F004
Interrupt Register Contents• HT66F002
Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0INTEG — — — — — — INT0�1 INT0�0INTC0 — TB1F TB0F INTF TB1E TB0E INTE EMIINTC1 — ADF DEF MF0F — ADE DEE MF0EMFI0 — — �TMA0F �TMP0F — — �TMA0E �TMP0E
• HT66F003
Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0INTEG — — — — — — INT0�1 INT0�0INTC0 — TB1F TB0F INTF TB1E TB0E INTE EMIINTC1 MF1F ADF DEF MF0F MF1E ADE DEE MF0EMFI0 — — �TMA0F �TMP0F — — �TMA0E �TMP0EMFI1 — — PTMA1F PTMP1F — — PTMA1E PTMP1E
• HT66F004
Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0INTEG — — — — INT1�1 INT1�0 INT0�1 INT0�0INTC0 — TB1F TB0F INT0F TB1E TB0E INT0E EMIINTC1 INT1F ADF DEF MF0F INT1E ADE DEE MF0EMFI0 PTMA1F PTMP1F PTMA0F PTMP0F PTMA1E PTMP1E PTMA0E PTMP0E
INTEG Register – HT66F002/HT66F003Bit 7 6 5 4 3 2 1 0
Na�e — — — — — — INT0�1 INT0�0R/W — — — — — — R/W R/WPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas"0"Bit1~0 INT0S1, INT0S0:DefinesINTinterruptactiveedge
00:DisableInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt
Rev. 1.10 110 �e�te��e� 1�� �01� Rev. 1.10 111 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
INTEG Register – HT66F004Bit 7 6 5 4 3 2 1 0
Na�e — — — — INT1�1 INT1�0 INT0�1 INT0�0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0
Bit7~4 Unimplemented,readas“0”Bit3~2 INT1S1, INT1S0:DefinesINT1interruptactiveedge
00:DisableInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt
Bit1~0 INT0S1, INT0S0:DefinesINT0interruptactiveedge00:DisableInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt
INTC0 Register – HT66F002/HT66F003Bit 7 6 5 4 3 2 1 0
Na�e — TB1F TB0F INTF TB1E TB0E INTE EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0
Bit7 Unimplemented,readas"0"Bit6 TB1F :TimeBase1InterruptRequestFlag
0:Norequest1:Interruptrequest
Bit5 TB0F:TimeBase0InterruptRequestFlag0:Norequest1:Interruptrequest
Bit4 INTF:INTInterruptRequestFlag0:Norequest1:Interruptrequest
Bit3 TB1E :TimeBase1InterruptControl0:Disable1:Enable
Bit2 TB0E:TimeBase0InterruptControl0:Disable1:Enable
Bit1 INTE:INTInterruptControl0:Disable1:Enable
Bit0 EMI:GlobalInterruptControl0:Disable1:Enable
Rev. 1.10 11� �e�te��e� 1�� �01� Rev. 1.10 113 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
INTC0 Register – HT66F004Bit 7 6 5 4 3 2 1 0
Na�e — TB1F TB0F INT0F TB1E TB0E INT0E EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0
Bit7 Unimplemented,readas“0”Bit6 TB1F:TimeBase1InterruptRequestFlag
0:Norequest1:Interruptrequest
Bit5 TB0F:TimeBase0InterruptRequestFlag0:Norequest1:Interruptrequest
Bit4 INT0F:INT0InterruptRequestFlag0:Norequest1:Interruptrequest
Bit3 TB1E :TimeBase1InterruptControl0:Disable1:Enable
Bit2 TB0E:TimeBase0InterruptControl0:Disable1:Enable
Bit1 INT0E:INT0InterruptControl0:Disable1:Enable
Bit0 EMI:GlobalInterruptControl0:Disable1:Enable
INTC1 Register – HT66F002Bit 7 6 5 4 3 2 1 0
Na�e — ADF DEF MF0F — ADE DEE MF0ER/W — R/W R/W R/W — R/W R/W R/WPOR — 0 0 0 — 0 0 0
Bit7 Unimplemented,readas"0"Bit6 ADF:A/DConverterInterruptRequestFlag
0:Norequest1:Interruptrequest
Bit5 DEF:DataEEPROMInterruptRequestFlag0:Norequest1:Interruptrequest
Bit4 MF0F:Multi-function0InterruptRequestFlag0:Norequest1:Interruptrequest
Bit3 Unimplemented,readas"0"Bit2 ADE:A/DConverterInterruptControl
0:Disable1:Enable
Bit1 DEE:DataEEPROMInterruptControl0:Disable1:Enable
Bit0 MF0E:Multi-function0InterruptControl0:Disable1:Enable
Rev. 1.10 11� �e�te��e� 1�� �01� Rev. 1.10 113 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
INTC1 Register – HT66F003Bit 7 6 5 4 3 2 1 0
Na�e MF1F ADF DEF MF0F MF1E ADE DEE MF0ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 MF1F:Multi-function1InterruptRequestFlag0:Norequest1:Interruptrequest
Bit6 ADF:A/DConverterInterruptRequestFlag0:Norequest1:Interruptrequest
Bit5 DEF:DataEEPROMInterruptRequestFlag0:Norequest1:Interruptrequest
Bit4 MF0F:Multi-function0InterruptRequestFlag0:Norequest1:Interruptrequest
Bit3 MF1E:Multi-function1InterruptControl0:Disable1:Enable
Bit2 ADE:A/DConverterInterruptControl0:Disable1:Enable
Bit1 DEE:DataEEPROMInterruptControl0:Disable1:Enable
Bit0 MF0E:Multi-function0InterruptControl0:Disable1:Enable
INTC1 Register – HT66F004Bit 7 6 5 4 3 2 1 0
Na�e INT1F ADF DEF MF0F INT1E ADE DEE MF0ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 INT1F:INT1InterruptRequestFlag0:Norequest1:Interruptrequest
Bit6 ADF:A/DConverterInterruptRequestFlag0:Norequest1:Interruptrequest
Bit5 DEF:DataEEPROMInterruptRequestFlag0:Norequest1:Interruptrequest
Bit4 MF0F:Multi-function0InterruptRequestFlag0:Norequest1:Interruptrequest
Bit3 INT1E:INT1InterruptControl0:Disable1:Enable
Bit2 ADE:A/DConverterInterruptControl0:Disable1:Enable
Rev. 1.10 11� �e�te��e� 1�� �01� Rev. 1.10 115 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Bit1 DEE:DataEEPROMInterruptControl0:Disable1:Enable
Bit0 MF0E:Multi-function0InterruptControl0:Disable1:Enable
MFI0 Register – HT66F002/HT66F003Bit 7 6 5 4 3 2 1 0
Na�e — — �TMA0F �TMP0F — — �TMA0E �TMP0ER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0
Bit7~6 Unimplemented,readas"0"Bit5 STMA0F:STMComparatorAmatchinterruptrequestflag
0:Norequest1:Interruptrequest
Bit4 STMP0F:STMComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit3~2 Unimplemented,readas"0"Bit1 STMA0E:STMComparatorAmatchinterruptcontrol
0:Disable1:Enable
Bit0 STMP0E:STMComparatorPmatchinterruptcontrol0:Disable1:Enable
MFI0 Register – HT66F004Bit 7 6 5 4 3 2 1 0
Na�e PTMA1F PTMP1F PTMA0F PTMP0F PTMA1E PTMP1E PTMA0E PTMP0ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 PTMA1F:TM1ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit6 PTMP1F:TM1ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit5 PTMA0F:TM0ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit4 PTMP0F:TM0ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit3 PTMA1E:TM1ComparatorAmatchinterruptcontrol0:Disable1:Enable
Bit2 PTMP1E:TM1ComparatorPmatchinterruptcontrol0:Disable1:Enable
Rev. 1.10 11� �e�te��e� 1�� �01� Rev. 1.10 115 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Bit1 PTMA0E:TM0ComparatorAmatchinterruptcontrol0:Disable1:Enable
Bit0 PTMP0E:TM0ComparatorPmatchinterruptcontrol0:Disable1:Enable
MFI1 Register – HT66F003 onlyBit 7 6 5 4 3 2 1 0
Na�e — — PTMA1F PTMP1F — — PTMA1E PTMP1ER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0
Bit7~6 Unimplemented,readas"0"Bit5 PTMA1F:PTMComparatorAmatchinterruptrequestflag
0:Norequest1:Interruptrequest
Bit4 PTMP1F:PTMComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit3~2 Unimplemented,readas"0"Bit1 PTMA1E:PTMComparatorAmatchinterruptcontrol
0:Disable1:Enable
Bit0 PTMP1E:PTMComparatorPmatchinterruptcontrol0:Disable1:Enable
Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparatorPorComparatorAmatchorA/Dconversioncompletionetc, therelevant interruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.
Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha“RETI”,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.
Rev. 1.10 116 �e�te��e� 1�� �01� Rev. 1.10 117 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagrams with theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.
Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.
INT Pin
Ti�e Base 0
INTF
TB0F
INTE
TB0E
EMI 0�H
EMI 08H
EEPROM DEF DEE
0CH
10H
1�H
18H
1CH
Inte��u�t Na�e
Request Flags
Ena�le Bits
Maste� Ena�le Vector
EMI auto disa�led in I�R
P�io�ityHigh
LowM. Funct. 1 MF1F MF1E
Inte��u�ts contained within Multi-Function Inte��u�ts
xxE Ena�le Bits
xxF Request Flag� auto �eset in I�R
LegendxxF Request Flag� no auto �eset in I�R
EMI
EMI
EMI
�TM P �TMP0F �TMP0E
�TM A �TMA0F �TMA0EEMI
EMITi�e Base 1 TB1F TB1E
M. Funct. 0 MF0F MF0E
A/D ADF ADE
PTM P PTMP1F PTMP1E
PTM A PTMA1F PTMA1E
HT66F003 only
Inte��u�tNa�e
RequestFlags
Ena�leBits
Interrupt Structure – HT66F002/HT66F003
Rev. 1.10 116 �e�te��e� 1�� �01� Rev. 1.10 117 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
INT0 Pin
Ti�e Base 0
INT0F
TB0F
INT0E
TB0E
EMI 0�H
EMI 08H
EEPROM DEF DEE
0CH
10H
1�H
18H
1CH
Inte��u�t Na�e
Request Flags
Ena�le Bits
Maste� Ena�le Vector
EMI auto disa�led in I�R
P�io�ityHigh
LowINT1 Pin INT1F INT1E
Inte��u�ts contained within Multi-Function Inte��u�ts
xxE Ena�le Bits
xxF Request Flag� auto �eset in I�R
LegendxxF Request Flag� no auto �eset in I�R
EMI
EMI
EMI
PTM0 P PTMP0F PTMP0E
PTM0 A PTMA0F PTMA0E EMI
EMITi�e Base 1 TB1F TB1E
M. Funct. 0 MF0F MF0E
A/D ADF ADE
PTM1 P PTMP1F PTMP1E
PTM1 A PTMA1F PTMA1E
Inte��u�tNa�e
RequestFlags
Ena�leBits
Interrupt Structure – HT66F004
External InterruptTheexternal interrupt iscontrolledbysignal transitionson thepins INTandINT0~INT1.Anexternal interruptrequestwill takeplacewhentheexternal interruptrequestflag,INTnF, isset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternal interruptpin.Toallowtheprogramtobranchtotheinterruptvectoraddress, theglobalinterruptenablebit,EMI,andtheexternalinterruptenablebit,INTnE,mustfirstbeset.Additionallythecorrect interruptedgetypemustbeselectedusingtheINTEGregister toenable theexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinsarepin-sharedwith I/Opins, theycanonlybeconfiguredasexternal interruptpinsbysetting thepin-sharedregisters.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whenthe interrupt isserviced, theexternal interrupt request flag, INTnF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableother interrupts.Notethat thepull-highresistorselectionontheexternalinterruptpinwillremainvalidevenifthepinisusedasanexternalinterruptinput.
TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.
Rev. 1.10 118 �e�te��e� 1�� �01� Rev. 1.10 11� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Multi-function InterruptWithinthesedevicesthereareuptotwoMulti-functioninterrupts.Unliketheother independentinterrupts, theseinterruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheTMInterrupts.
AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflags,MF0F~MF1Fareset.TheMulti-functioninterruptflagswillbesetwhenanyoftheirincludedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecalltooneoftheMulti-functioninterruptvectorswilltakeplace.Whentheinterruptisserviced,therelatedMulti-Functionrequestflag,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.
However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhentheinterruptisserviced,therequestflagsfromtheoriginalsourceoftheMulti-functioninterrupts,namelytheTMInterrupts,willnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.
A/D Converter InterruptThedevicescontainanA/Dconverterwhichhasitsownindependentinterrupt.TheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwill takeplacewhentheA/DConverterInterruptrequestflag,ADF, isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.
Time Base InterruptsThefunctionoftheTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappens their respective interrupt request flags,TB0ForTB1Fwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebits,TB0EorTB1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecall totheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TB0ForTB1F,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.
ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.TheirclocksourcesoriginatefromtheinternalclocksourcefTB.ThisfTB inputclockpasses throughadivider, thedivisionratioofwhich isselectedbyprogrammingtheappropriatebits in theTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTB,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,asshownintheSystemOperatingModesection.
Rev. 1.10 118 �e�te��e� 1�� �01� Rev. 1.10 11� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
TBC RegisterBit 7 6 5 4 3 2 1 0
Na�e TBON TBCK TB11 TB10 — TB0� TB01 TB00R/W R/W R/W R/W R/W — R/W R/W R/WPOR 0 0 1 1 — 1 1 1
Bit7 TBON:TB0andTB1Controlbit0:Disable1:Enable
Bit6 TBCK:SelectfTBClock0:fTBC1:fSYS/4
Bit5~4 TB11 ~ TB10:SelectTimeBase1Time-outPeriod00:4096/fTB
01:8192/fTB
10:16384/fTB
11:32768/fTB
Bit3 Unimplemented,readas"0"Bit2~0 TB02 ~ TB00:SelectTimeBase0Time-outPeriod
000:256/fTB
001:512/fTB
010:1024/fTB
011:2048/fTB
100:4096/fTB
101:8192/fTB
110:16384/fTB
111:32768/fTB
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Time Base Interrupt
Rev. 1.10 1�0 �e�te��e� 1�� �01� Rev. 1.10 1�1 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
EEPROM InterruptAnEEPROMInterruptrequestwilltakeplacewhentheEEPROMInterruptrequestflag,DEF,isset,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andEEPROMInterruptenablebit,DEE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecalltotherespectiveEEPROMInterruptvector,willtakeplace.WhentheEEPROMInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,andtheEEPROMinterruptrequestflag,DEF,willalsobeautomaticallycleared.
TM InterruptsTheTMseachhastwointerrupts.AlloftheTMinterruptsarecontainedwithintheMulti-functionInterrupts.Foreachof theTMs thereare twointerruptrequestflagsxTMPnFandxTMAnFandtwoenablebitsxTMPnEandxTMAnE.ATMinterruptrequestwill takeplacewhenanyof theTMrequestflagsareset,asituationwhichoccurswhenaTMcomparatorPorcomparatorAmatchsituationhappens.
Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtherespectiveTMInterruptenablebit,andassociatedMulti-functioninterruptenablebit,MFnF,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecall to therelevantTMInterruptvector locations,will takeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.
Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpin,alowpowersupplyvoltageorcomparatorinputchangemaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.
Rev. 1.10 1�0 �e�te��e� 1�� �01� Rev. 1.10 1�1 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.
Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptserviceroutineisexecuted,asonlytheMulti-functioninterruptrequestflags,MF0F~MF1F,willbeautomaticallycleared, the individualrequestflagfor thefunctionneeds tobeclearedbytheapplicationprogram.
It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.
Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.
AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.
Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.
Rev. 1.10 1�� �e�te��e� 1�� �01� Rev. 1.10 1�3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
SCOM Function for LCDTheHT66F004devicehas thecapabilityofdrivingexternalLCDpanels.ThecommonpinsforLCDdriving,SCOM0~SCOM3,arepinsharedwithcertainpinontheI/Oports.TheLCDsignalsaregeneratedusingtheapplicationprogram.
LCD operationAnexternalLCDpanelcanbedrivenusingthisdevicebyconfiguringtheI/Opinsascommonpins.TheLCDdriverfunctioniscontrolledusingtheSCOMCregisterwhichinadditiontocontrollingtheoverallon/offfunctionalsocontrolsthebiasvoltagesetupfunction.ThisenablestheLCDCOMdrivertogeneratethenecessaryVDD/2voltagelevelsforLCD1/2biasoperation.
TheSCOMENbit in theSCOMCregister is theoverallmastercontrol for theLCDdriver.TheLCDSCOMnpinisselectedtobeusedforLCDdrivingbythecorrespondingpin-sharedfunctionselectionbits.NotethatthePortControlregisterdoesnotneedtofirstsetupthepinsasoutputstoenabletheLCDdriveroperation.
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LCD COM Bias
Rev. 1.10 1�� �e�te��e� 1�� �01� Rev. 1.10 1�3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
LCD Bias Current ControlTheLCDCOMdriverenablesarangeofselectionstobeprovidedtosuit therequirementoftheLCDpanelwhicharebeingused.Thebiasresistorchoice is implementedusingtheISEL1andISEL0bitsintheSCOMCregister.
SCOMCBit 7 6 5 4 3 2 1 0
Na�e — I�EL1 I�EL0 �COMEN COM3EN COM�EN COM1EN COM0ENR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0
Bit7 Unimplemented,readas“0”Bit6~5 ISEL1~ISEL0:SelectresistorforRtypeLCDbiascurrent(VDD=5V)
00:2×100kΩ(1/2Bias),IBIAS=25μA01:2×50kΩ(1/2Bias),IBIAS=50μA10:2×25kΩ(1/2Bias),IBIAS=100μA11:2×12.5kΩ(1/2Bias),IBIAS=200μA
Bit4 SCOMEN:LCDcontrolbit0:Disable1:Enable
WhenSCOMENisset,itwillturnontheDCpathofresistortogenerate1/2VDDbiasvoltage.
Bit3 COM3EN:PB3/AN7orSCOM3selection0:PB3/AN71:SCOM3
Bit2 COM2EN:PB4/CLOorSCOM2selection0:PB4/CLO1:SCOM2
Bit1 COM1EN:PC1orSCOM1selection0:PC11:SCOM1
Bit0 COM0EN:PC0orSCOM0selection0:PC01:SCOM0
Rev. 1.10 1�� �e�te��e� 1�� �01� Rev. 1.10 1�5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Application Circuits
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HT66F002
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HT66F003
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HT66F004Note:"*"RecommendedcomponentforaddedESDprotection.
"**"Recommendedcomponentinenvironmentswherepowerlinenoiseissignificant.
Rev. 1.10 1�� �e�te��e� 1�� �01� Rev. 1.10 1�5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Instruction Set
IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.
Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.
Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe"CLRPCL"or"MOVPCL,A".Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.
Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.
Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.
Rev. 1.10 1�6 �e�te��e� 1�� �01� Rev. 1.10 1�7 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.
Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction"RET"inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.
Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe"SET[m].i"or"CLR[m].i" instructionsrespectively.Thefeatureremovestheneedforprogrammers tofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.
Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemory tobesetasa tablewheredatacanbedirectlystored.Asetofeasy touse instructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.
Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe"HALT"instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.
Rev. 1.10 1�6 �e�te��e� 1�� �01� Rev. 1.10 1�7 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.
Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress
Mnemonic Description Cycles Flag AffectedArithmeticADD A�[�] Add Data Me�o�y to ACC 1 Z� C� AC� OVADDM A�[�] Add ACC to Data Me�o�y 1Note Z� C� AC� OVADD A�x Add i��ediate data to ACC 1 Z� C� AC� OVADC A�[�] Add Data Me�o�y to ACC with Ca��y 1 Z� C� AC� OVADCM A�[�] Add ACC to Data �e�o�y with Ca��y 1Note Z� C� AC� OV�UB A�x �u�t�act i��ediate data f�o� the ACC 1 Z� C� AC� OV�UB A�[�] �u�t�act Data Me�o�y f�o� ACC 1 Z� C� AC� OV�UBM A�[�] �u�t�act Data Me�o�y f�o� ACC with �esult in Data Me�o�y 1Note Z� C� AC� OV�BC A�[�] �u�t�act Data Me�o�y f�o� ACC with Ca��y 1 Z� C� AC� OV�BCM A�[�] �u�t�act Data Me�o�y f�o� ACC with Ca��y� �esult in Data Me�o�y 1Note Z� C� AC� OVDAA [�] Deci�al adjust ACC fo� Addition with �esult in Data Me�o�y 1Note CLogic OperationAND A�[�] Logical AND Data Me�o�y to ACC 1 ZOR A�[�] Logical OR Data Me�o�y to ACC 1 ZXOR A�[�] Logical XOR Data Me�o�y to ACC 1 ZANDM A�[�] Logical AND ACC to Data Me�o�y 1Note ZORM A�[�] Logical OR ACC to Data Me�o�y 1Note ZXORM A�[�] Logical XOR ACC to Data Me�o�y 1Note ZAND A�x Logical AND i��ediate Data to ACC 1 ZOR A�x Logical OR i��ediate Data to ACC 1 ZXOR A�x Logical XOR i��ediate Data to ACC 1 ZCPL [�] Co��le�ent Data Me�o�y 1Note ZCPLA [�] Co��le�ent Data Me�o�y with �esult in ACC 1 ZIncrement & DecrementINCA [�] Inc�e�ent Data Me�o�y with �esult in ACC 1 ZINC [�] Inc�e�ent Data Me�o�y 1Note ZDECA [�] Dec�e�ent Data Me�o�y with �esult in ACC 1 ZDEC [�] Dec�e�ent Data Me�o�y 1Note ZRotateRRA [�] Rotate Data Me�o�y �ight with �esult in ACC 1 NoneRR [�] Rotate Data Me�o�y �ight 1Note NoneRRCA [�] Rotate Data Me�o�y �ight th�ough Ca��y with �esult in ACC 1 CRRC [�] Rotate Data Me�o�y �ight th�ough Ca��y 1Note CRLA [�] Rotate Data Me�o�y left with �esult in ACC 1 NoneRL [�] Rotate Data Me�o�y left 1Note NoneRLCA [�] Rotate Data Me�o�y left th�ough Ca��y with �esult in ACC 1 CRLC [�] Rotate Data Me�o�y left th�ough Ca��y 1Note C
Rev. 1.10 1�8 �e�te��e� 1�� �01� Rev. 1.10 1�� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Mnemonic Description Cycles Flag AffectedData MoveMOV A�[�] Move Data Me�o�y to ACC 1 NoneMOV [�]�A Move ACC to Data Me�o�y 1Note NoneMOV A�x Move i��ediate data to ACC 1 NoneBit OperationCLR [�].i Clea� �it of Data Me�o�y 1Note None�ET [�].i �et �it of Data Me�o�y 1Note NoneBranchJMP add� Ju�� unconditionally � None�Z [�] �ki� if Data Me�o�y is ze�o 1Note None�ZA [�] �ki� if Data Me�o�y is ze�o with data �ove�ent to ACC 1Note None�Z [�].i �ki� if �it i of Data Me�o�y is ze�o 1Note None�NZ [�].i �ki� if �it i of Data Me�o�y is not ze�o 1Note None�IZ [�] �ki� if inc�e�ent Data Me�o�y is ze�o 1Note None�DZ [�] �ki� if dec�e�ent Data Me�o�y is ze�o 1Note None�IZA [�] �ki� if inc�e�ent Data Me�o�y is ze�o with �esult in ACC 1Note None�DZA [�] �ki� if dec�e�ent Data Me�o�y is ze�o with �esult in ACC 1Note NoneCALL add� �u��outine call � NoneRET Retu�n f�o� su��outine � NoneRET A�x Retu�n f�o� su��outine and load i��ediate data to ACC � NoneRETI Retu�n f�o� inte��u�t � NoneTable ReadTABRD [�] Read table (specific page) to TBLH and Data Memory �Note NoneTABRDC [�] Read ta�le (cu��ent �age) to TBLH and Data Me�o�y �Note NoneTABRDL [�] Read ta�le (last �age) to TBLH and Data Me�o�y �Note NoneMiscellaneousNOP No o�e�ation 1 NoneCLR [�] Clea� Data Me�o�y 1Note None�ET [�] �et Data Me�o�y 1Note NoneCLR WDT Clea� Watchdog Ti�e� 1 TO� PDFCLR WDT1 P�e-clea� Watchdog Ti�e� 1 TO� PDFCLR WDT� P�e-clea� Watchdog Ti�e� 1 TO� PDF�WAP [�] �wa� ni��les of Data Me�o�y 1Note None�WAPA [�] �wa� ni��les of Data Me�o�y with �esult in ACC 1 NoneHALT Ente� �owe� down �ode 1 TO� PDF
Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.
2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the"CLRWDT1"and"CLRWDT2"instructions theTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDF flagsareclearedafterboth "CLRWDT1"and"CLRWDT2"instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.
Rev. 1.10 1�8 �e�te��e� 1�� �01� Rev. 1.10 1�� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Instruction Definition
ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C
ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C
ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C
ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C
ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C
AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z
AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z
ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z
Rev. 1.10 130 �e�te��e� 1�� �01� Rev. 1.10 131 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None
CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None
CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None
CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF
CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF
CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF
CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z
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HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z
DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C
DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z
DECA[m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z
HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF
INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z
INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z
Rev. 1.10 13� �e�te��e� 1�� �01� Rev. 1.10 133 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None
MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None
MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None
MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None
NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None
OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z
OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z
ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z
RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None
Rev. 1.10 13� �e�te��e� 1�� �01� Rev. 1.10 133 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None
RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None
RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None
RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None
RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C
RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C
RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None
Rev. 1.10 13� �e�te��e� 1�� �01� Rev. 1.10 135 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None
RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C
RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C
SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C
SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C
SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None
Rev. 1.10 13� �e�te��e� 1�� �01� Rev. 1.10 135 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None
SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None
SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None
SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None
SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None
SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None
SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C
Rev. 1.10 136 �e�te��e� 1�� �01� Rev. 1.10 137 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C
SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C
SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None
SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None
SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None
SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None
SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None
Rev. 1.10 136 �e�te��e� 1�� �01� Rev. 1.10 137 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z
XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z
XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z
Rev. 1.10 138 �e�te��e� 1�� �01� Rev. 1.10 13� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Package Information
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• Cartoninformation
Rev. 1.10 138 �e�te��e� 1�� �01� Rev. 1.10 13� �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
8-pin SOP (150mil) Outline Dimensions
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SymbolDimensions in inch
Min. Nom. Max.A — 0.�36 B�C —
B — 0.15� B�C —
C 0.01� — 0.0�0C’ — 0.1�3 B�C —D — — 0.06�E — 0.050 B�C —F 0.00� — 0.010G 0.016 — 0.050H 0.00� — 0.010α 0° — 8°
SymbolDimensions in mm
Min. Nom. Max.A — 6.00 B�C —B — 3.�0 B�C —C 0.31 — 0.51C’ — �.�0 B�C —D — — 1.75E — 1.�7 B�C —F 0.10 — 0.�5G 0.�0 — 1.�7H 0.10 — 0.�5α 0° — 8°
Rev. 1.10 1�0 �e�te��e� 1�� �01� Rev. 1.10 1�1 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
10-pin MSOP Outline Dimensions
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SymbolDimensions in inch
Min. Nom. Max.
A — — 0.0�3
A1 0.000 — 0.006
A� 0.030 0.033 0.037
B 0.007 — 0.013
C 0.003 — 0.00�
D — 0.118 B�C —
E — 0.1�3 B�C —
E1 — 0.118 B�C —
e — 0.0�0 B�C —
L 0.016 0.0�� 0.031
L1 — 0.037 B�C —
y — 0.00� —
θ 0° — 8°
SymbolDimensions in mm
Min. Nom. Max.
A — — 1.10
A1 0.00 — 0.15
A� 0.75 0.85 0.�5
B 0.17 — 0.33
C 0.08 — 0.�3
D — 3.0 B�C —
E — �.� B�C —
E1 — 3.0 B�C —
e — 0.5 B�C —
L 0.�0 0.60 0.80
L1 — 0.�5 B�C —
y — 0.1 —
θ 0° — 8°
Rev. 1.10 1�0 �e�te��e� 1�� �01� Rev. 1.10 1�1 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
16-pin NSOP (150mil) Outline Dimensions
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SymbolDimensions in inch
Min. Nom. Max.A — 0.�36 B�C —
B — 0.15� B�C —
C 0.01� — 0.0�0C’ — 0.3�0 B�C —D — — 0.06�E — 0.050 B�C —F 0.00� — 0.010G 0.016 — 0.050H 0.00� — 0.010α 0° — 8°
SymbolDimensions in mm
Min. Nom. Max.A — 6.0 B�C —B — 3.� B�C —C 0.31 — 0.51C’ — �.� B�C —D — — 1.75E — 1.�7 B�C —F 0.10 — 0.�5G 0.�0 — 1.�7H 0.10 — 0.�5α 0° — 8°
Rev. 1.10 1�� �e�te��e� 1�� �01� Rev. 1.10 1�3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
20-pin DIP (300mil) Outline Dimensions
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Fig 1. Full Lead Packages Fig 2. 1/2 Lead Packages
See Fig 1
SymbolDimensions in inch
Min. Nom. Max.
A 0.�80 1.030 1.060
B 0.��0 0.�50 0.�80
C 0.115 0.130 0.1�5
D 0.115 0.130 0.150
E 0.01� 0.018 0.0��
F 0.0�5 0.060 0.070
G — 0.1B�C —
H 0.300 0.310 0.3�5
I — — 0.�30
SymbolDimensions in mm
Min. Nom. Max.
A ��.8� �6.16 �6.��
B 6.10 6.35 7.11
C �.�� 3.30 �.�5
D �.�� 3.30 3.81
E 0.36 0.�6 0.56
F 1.1� 1.5� 1.78
G — �.5� B�C —
H 7.6� 7.87 8.�6
I — — 10.��
Rev. 1.10 1�� �e�te��e� 1�� �01� Rev. 1.10 1�3 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
See Fig2
SymbolDimensions in inch
Min. Nom. Max.
A 0.��5 0.�65 0.�85
B 0.�75 0.�85 0.��5
C 0.1�0 0.135 0.150
D 0.110 0.130 0.150
E 0.01� 0.018 0.0��
F 0.0�5 0.050 0.060
G — 0.1B�C —
H 0.300 0.310 0.3�5
I — — 0.�30
SymbolDimensions in mm
Min. Nom. Max.
A ��.00 ��.51 �5.0�
B 6.�� 7.�� 7.��
C 3.05 3.�3 3.81
D �.7� 3.30 3.81
E 0.36 0.�6 0.56
F 1.1� 1.�7 1.5�
G — �.5� B�C —
H 7.6� 7.87 8.�6
I — — 10.��
Rev. 1.10 1�� �e�te��e� 1�� �01� Rev. 1.10 1�5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
20-pin SOP (300mil) Outline Dimensions
� �
�
� �
� �
� �
�
�
� �
� ��
�
�
SymbolDimensions in inch
Min. Nom. Max.
A — 0.�06 B�C —
B — 0.�06 B�C —
C 0.01� — 0.0�0
C’ — 0.50� B�C —
D — — 0.10�
E — 0.050 B�C —
F 0.00� — 0.01�
G 0.016 — 0.050
H 0.008 — 0.013
α 0° — 8°
SymbolDimensions in mm
Min. Nom. Max.
A — 10.30 B�C —
B — 7.50 B�C —
C — 7.50 B�C —
C’ — 1�.80 B�C —
D — 1�.80 B�C —
E — 1.�7 B�C —
F 0.10 — 0.30
G 0.�0 — 1.�7
H 0.�0 — 1.�7
α 0° — 8°
Rev. 1.10 1�� �e�te��e� 1�� �01� Rev. 1.10 1�5 �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
20-pin SSOP (150mil) Outline Dimensions
� �
�
� �
� �
� �
�
�
� �
� � ��
�
SymbolDimensions in inch
Min. Nom. Max.A — 0.�36 B�C —
B — 0.155 B�C —
C 0.008 — 0.01�
C’ — 0.3�1 B�C —
D — — 0.06�
E — 0.0�5 B�C —
F 0.00� — 0.00�8
G 0.016 — 0.05
H 0.00� — 0.01
α 0° ― 8°
SymbolDimensions in mm
Min. Nom. Max.A — 6.00 B�C —
B — 3.�0 B�C —
C 0.�0 — 0.30
C‘ — 8.66 B�C —
D — — 1.75
E — 0.635 B�C —
F 0.10 — 0.�5
G 0.�1 — 1.�7
H 0.10 — 0.�5
α 0° ― 8°
Rev. 1.10 1�6 �e�te��e� 1�� �01� Rev. 1.10 PB �e�te��e� 1�� �01�
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
HT66F002/HT66F003/HT66F004Cost-Effective A/D Flash 8-Bit MCU with EEPROM
Co�y�ight© �01� �y HOLTEK �EMICONDUCTOR INC.
The info��ation a��ea�ing in this Data �heet is �elieved to �e accu�ate at the ti�e of �u�lication. Howeve�� Holtek assu�es no �es�onsi�ility a�ising f�o� the use of the specifications described. The applications mentioned herein are used solely fo� the �u��ose of illust�ation and Holtek �akes no wa��anty o� �e��esentation that such a��lications will �e suita�le without fu�the� �odification� no� �eco��ends the use of its ��oducts fo� a��lication that �ay ��esent a �isk to hu�an life due to �alfunction o� othe�wise. Holtek's ��oducts a�e not autho�ized fo� use as c�itical co��onents in life su��o�t devices o� syste�s. Holtek �ese�ves the �ight to alte� its products without prior notification. For the most up-to-date information, please visit ou� we� site at htt�://www.holtek.co�.tw.