course: vlsi circuits (video course) faculty coordinator(s) :

8/14/2019 Course: VLSI Circuits (Video Course) Faculty Coordinator(s) :

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Course: VLSI Circuits (Video Course)

Faculty Coordinator(s) :

Prof. S. Srinivasan

Department of Electrical Engineering

Indian Institute of Technology MadrasChennai 600036

Email :[email protected] ,[email protected] : (91-44) 2257 4401 (Office)

(91-44) 2257 6413 (Residence)

Detailed Syllabus :

1 Introduction to VLSI Design

Introduction

2 Combinational Circuit Design

Components of Combinational Design - Multiplexer and DecoderMultiplexer Based Design of Combinational CircuitsImplementation of Full Adder using MultiplexerDecoderImplementation of Full Adder using Decoder

3 Programmable Logic Devices

Types of Programmable Logic DevicesCombinational Logic ExamplesPROM - Fixed AND Array and Programmable OR ArrayImplementation of Functions using PROMPLA - Programmable Logic ArrayPLA Implementation Example

4 Programmable Array Logic

PAL - Programmable Array LogicComparison of PROM, PLA and PALImplementation of a Function using PALTypes of PAL Outputs

Device Examples

5 Review of Flip-Flops

Introduction to Sequential CircuitsR-S Latch and Clocked R-S LatchD Flip FlopJ-K Flip FlopMaster Slave OperationEdge Triggered Operation
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6 Sequential Circuits

Clocking of Flip-flopsSetup and Hold TimesMoore CircuitMealy Circuit

Clocking RulesSequential Circuits Design Rules

7 Sequential Circuit Design

Sequential Circuit Design BasicsDesign of a 4-bit Full Adder using D Flip-flopPattern IdentifierState GraphTransition Table

8 MSI Implementation of Sequential Circuits

Implementation of Pattern Identifier revisitedMUX Based RealizationROM Based RealizationPAL Implementation

9 Design of Sequential Circuits using One Hot Controller

Design of a Vending Machine as an exampleState GraphState TableImplementation using PAL

10 Verilog Modeling of Combinational Circuits

Introduction to VerilogLevels of AbstractionRealization of Combinational CircuitsVerilog Code for Multiplexers and DemultiplexersRealization of a Full AdderBehavioral, Data Flow and Structural RealizationRealization of a Magnitude ComparatorDesign Example

11 Modeling of Verilog Sequential Circuits - Core Statements

Design of a D Flip Flop

Realization of a RegisterRealization of a CounterRealization of a Nonretriggerable Monoshot

12 Modeling of Verilog Sequential Circuits - Core Statements(Continued)

Realization of a Right Shift RegisterRealization of a Parallel to Serial ConverterRealization of a Model State MachinePattern Sequence Detector as a Design Example


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13 RTL Coding Guidelines

RTL Coding Guidelines IntroductionDos and Donts for Asynchronous and Synchronous Logic Circuit DesignRTL Coding StyleSeparation of Combinational and Sequential Circuitsif - else if else statements for MUX and Priority Encoder RealizationsVerilog Directives Case Statements

Operators

14 Coding Organization - Complete Realization

Introduction to Coding OrganizationDesign Module a ModelComplete Code for Combinational and Sequential Circuits

15 Coding Organization - Complete Realization (Continued)

Complete Code for Sequential Circuits- Right Shift Register- Parallel to Serial Converter

- Model State Machine- Pattern Sequence Detector

Test Bench for Combinational Circuits

16 Writing a Test Bench

Test bench for simple design AND gateTest bench for Combinational CircuitsTest bench for Sequential Circuits

17 System Design using ASM Chart

Top-down Design Methodology

ASM ChartRules of Drawing ASM Chart

18 Example of System Design using ASM Chart

Design of Bus ArbiterASM ChartState TableImplementation of Bus Arbiter using MUX and D Flip-flopsSpecification of a Traffic Light ControllerState GraphASM Chart of Traffic Light Controller

19 Examples of System Design using Sequential Circuits

Algorithm of Traffic Light ControllerASM TableHardware Realization using MUX and D Flip-flopsTraffic Light Controller ROM Realization - ROM Table

20 Examples of System Design using Sequential Circuits (Continued)

Dice Game - IntroductionAlgorithm for Dice GameArchitecture


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ASM Chart for Dice Game

21 Microprogrammed Design

Introduction to Microprogrammed Design of Digital SystemsASM Chart for a Microprogrammed DesignMicroprogrammed ROM TableComparison of the Conventional ROM and the Microprogrammed ROMApproaches

Single Qualifier, Double address Design

22 Microprogrammed Design (Continued)

Single Qualifier, Single Address (SQSA) System DesignASM chart for SQSA Microprogrammed ImplementationMicroprogrammed TableImplementation of SQSA System using Microprogrammed ROM, MUX and aCounterDice Game using Microprogrammed SQSA SystemASM Chart and Microprogrammed Table for Dice game

23 Design Flow of VLSI Circuits

Top-down Design MethodologyBottom-up Design MethodologySimulation of Verilog Codes using ModelsimTest Bench and Simulation of a Simple Design

24 Simulation of Combinational Circuits

Simulation of Combinational CircuitsSimulation Waveforms

- Simple Gates- Simple Boolean Expressions- Shift Register

- MUX and DEMUX

25 Simulation of Combinational and Sequential Circuits

Simulation Waveforms- a Magnitude Comparator- a Design Example- a D Flip-flop- Registers- a Counter

26 Analysis of Waveforms using Modelsim

Analysis of Waveforms- a Counter- a Non-retriggerable Monoshot- a Right Shift Register- a Parallel to Serial Converter- a Model State Machine

27 Analysis of Waveforms using Modelsim (Continued)

Analysis of Waveforms of a Model State Machine (Continued)Analysis of Waveforms of a Pattern Sequence Detector


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28 ModelSim Simulation Tool

ModelSim Command Summary

29 Synthesis Tool

More Features of ModelsimSynplify Synthesis Tool

Features of Synplify Tool

30 Synthesis Tool (Continued)

Synthesis Tool Command SummaryAnalysis of Design Example using Synplify Tool

31 Synplify Tool - Schematic Circuit Diagram View

Analysis of the Report File generated by Synplify ToolCommands Continued Optimized Verilog File using Synplify ToolViewing Verilog Code as RTL Schematic Circuit Diagrams

32 Technology View using Synplify Tool

Technology View using Synplify ToolWarnings and Errors Log ReportComparison of FPGA Performance of different Vendors for a DesignCreation of Errors Deliberately and Correction using Modelsim and Synplify Tools

33 Synopsys Full and Parallel Cases

Compilation/Load Errors and Correction using Modelsim and Synplify Tools(Continued)Synopsys Full Case - RTL View

Synopsys Parallel Case - RTL ViewXilinx Place & Route Tool Design ManagerXilinx Place & Route Tool Command SummaryPlace & Route Tool Report

34 Xilinx Place & Route Tool

Xilinx Place & Route Tool ReportCreation of Bit FileSynthesis Revisited Waveform Analysis of Optimized FileVarious Report Files of Xilinx Place & Route ToolBack Annotation in DOS Mode using Xilinx Place & Route Commands

35 Xilinx Place & Route Tool (Continued)

Back Annotation in DOS Mode using Xilinx Place & Route Commands(Continued)Simulation of Back Annotated File using Modelsim ToolAnalysis of Back Annotated Waveforms to get the Gate Delays of a DesignUser Constraint FileXilinx Floor PlannerDesign of PCI Arbiter using ASM Chart - Introduction


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36 PCI Arbiter Design using ASM Chart

Design of PCI Arbiter (Continued)ASM ChartVerilog Code of PCI ArbiterTest Bench for the PCI Arbiter DesignSimulation Results after Back annotationSynplify Results

Xilinx Place and Route Results

37 Design of Memories - ROM

On-chip Dual Address ROM DesignTest Bench for Dual Address ROM DesignSimulation ResultsSynplify and Place & Route ResultsOn-chip Single Address ROM DesignTest Bench for Single Address ROM DesignSimulation ResultsSynplify and Place & Route Results

38 Design of Memories - RAM

Design of On-chip Dual RAMRTL Verilog CodeTest Bench for Dual RAM DesignSimulation ResultsSynplify and Xilinx Place & Route Results

39 Design of External RAM

Controller Design for External RAMVerilog Code for Controller of External RAMTest Bench for External RAM GO-No GO Test

Simulation WaveformSynplify and Xilinx Place & Route Results

40 Design of Arithmetic Circuits

Principle of PipeliningPartitioning of a DesignSerial Signed Adder DesignSynplify and Xilinx Place & Route ResultsTest Bench for Serial AdderComparison of a Serial Adder and a Parallel Adder ImplementationSimulation Waveform

41 Design of Arithmetic Circuits (Continued)

Design of Eight Inputs Signed Parallel AdderDesign PartitionVerilog Code for the Signed Parallel AdderTest Bench for Parallel AdderSimulation WaveformSynplify and Xilinx Place & Route ResultsParallel, Pipelined Multiplier Design A new Algorithm for Fast ImplementationVerilog Code for the Parallel, Pipelined Multiplier


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42 Design of Arithmetic Circuits (Continued)

Verilog Code for Parallel Multiplier (Continued)Test Bench for Parallel MultiplierSimulation Results of Back Annotated Parallel Multiplier DesignSynplify and Xilinx Place & Route Results

43 System Design Examples

Verilog Code for Traffic Light ControllerSimulation Results of Traffic Light Controller DesignSynplify and Xilinx Place & Route Results

44 System Design Examples (Continued)

Test Bench for Traffic Light ControllerIntroduction to Image/Video CompressionBlock Diagram of a Video EncoderA Novel, Parallel Algorithm for Fast Evaluation of Discrete Cosine Transform andQuantization (DCTQ)


Design of Discrete Cosine Transform and Quantization ProcessorDCTQ Processor Block DiagramSignal Description of DCTQ ProcessorArchitecture of DCTQ ProcessorSequence of Operations of a Host Processor and the DCTQ ProcessorVerilog Codes for DCTQ Design


Verilog Codes for DCTQ Design (Continued)

DCTQ Top Design CodePartial Products Register CodeDCTQ Controller Code


Verilog Code for DCTQ Design - DCTQ Controller Code (Continued)Test Bench for DCTQ DesignSynplify ResultsXilinx Place and Route ResultsAnalysis of Waveforms of DCTQ DesignVerification of Verilog DCTQ IQIDCT CoresMatlab Codes for Pre-processing and Post-processing of an ImageResults Original and Reconstructed Image Example

Implementation Results of DCTQ, IQIDCT, DCT and IDCT Cores on FPGA/ASICCapabilities of IP Cores

48 System Design Examples using FPGA Board

Design Applications using FPGA Board- Traffic Light Controller and Real Time Clock

XSV FPGA Board FeaturesTesting of FPGA BoardSetting the XSV Board Clock Oscillator FrequencyDownloading Configuration Bit Streams


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49 System Design Examples using FPGA Board (Continued)

Features of Digital Input/Output CardTypical Push Button Debouncing Circuit and Switch Interface CircuitsTypical Driving Circuit for Seven Segment and Discrete LEDsProblem on FPGA Boards and its SolutionHardware Setup for Traffic Light Controller

Demo of Traffic Light ControllerRevised Verilog Code Incorporating Blink Control and Pedestrian Crossing

50 Advanced Features of Xilinx Project Navigator

User Constraint File for Traffic Light ControllerPlace and Route and Back Annotation Using Xilinx Project Navigator

- Command Summary of NavigatorFloor PlanSimulation of Back Annotated File


Real Time Clock DesignFeatures and SpecificationBlock Diagram and Signal Descriptions of Real Time ClockSimplified Architecture of Real Time ClockVerilog RTL Code for Real Time Clock


Verilog RTL Code for Real Time Clock (Continued)- Real Time Clock Code- Stop Watch Code


Stop Watch Implementation (Continued)Alarms routineDisplay ROM Sub-moduleTest Bench for Real Time Clock


Test Bench for Real Time Clock DesignUser Constraint File for Real Time Clock DesignSynplify ResultsXilinx Place and Route ResultsWaveform Analysis of the Real Time Clock DesignDemo of the Real Time Clock

55 Project Design Suggested for FPGA/ASIC Implementations

Projects Suggested for FPGA/ASIC ImplementationsIssues Involved in Digital VLSI System DesignDetailed Specification for Electrostatic Precipitator ControllerDetailed Specification for JPEG/H.261/MPEG CodecReferencesConclusions

course: vlsi circuits (video course) faculty coordinator(s) :

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