course web page: ece 545 introduction to vhdl ece web page courses course web pages ece 545
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Course web page:
ECE 545
Introduction to VHDL
ECE web page Courses Course web pages ECE 545
http://ece.gmu.edu/courses/ECE545/index.htm
Kris Gaj
Office hours: Monday, Wednesday 7:30-8:30 PM and by appointment
Research and teaching interests:• reconfigurable computing• computer arithmetic• cryptography• network security
Contact:Science & Technology II, room 223
[email protected], [email protected]
(703) 993-1575
ECE 545
Part of:
MS in Electrical Engineering
MS in Computer Engineering
Digital Systems DesignMicroprocessor and Embedded Systems
Required course in two concentration areas:
Elective
Elective course in the remaining concentration areas
MS in CpE13MS in EE
12
MS in IS1
PhD in ECE1
PhD in IT1
Fall 2005 Enrollment as of August 31, 2005
algorithmic
Design level
register-transfer
gate
transistor
layout
devices
CoursesComputerArithmetic
Introduction to VHDL
DigitalIntegratedCircuitsMixed
Signals VLSI
VLSI Test Concepts
VLSI Design Automation
ECE545
ECE645
ECE 586
ECE 699
ECE681
ECE682
ECE684 MOS Device Electronics
ECE 584 SemiconductorDevice Fundamentals
There are TWO core courses common for all concentration areas:
CS 571 Operating Systems– H. Aydin, S. Setia, C. Snow, project, C/C++ or Java
Pros:• Prerequisite for many other courses and projects• HLL (High Level Language) refresher• Offered regularly in Fall and Spring
ECE 548 Sequential Machine Theory– K. Hintz, R. Schneider
Pros:• Common theoretical and mathematical foundation used in all concentrations• Offered regularly in Spring• Not a strong prerequisite for any other course; can be taken any time during the curriculum.
Core courses
DIGITAL SYSTEMS DESIGN
Concentration advisor: Ken Hintz
1. ECE 545 Introduction to VHDL – K. Gaj, K. Hintz, projects, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys
2. ECE 645 Computer Arithmetic: HW and SW Implementation – K. Gaj, projects, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys
3. ECE 586 Digital Integrated Circuits – D. Ioannou
4. ECE 681 VLSI Design Automation – K. Kazi, projectz, VHDL, ModelSim/Synopsys
MICROPROCESSOR AND EMBEDDED SYSTEMS
Concentration advisor: Peter Pachowicz
1. ECE 511 Microprocessors– R. Barnes, P. Pachowicz,
2. ECE 545 Introduction to VHDL– K. Gaj, K. Hintz, project, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys
3. ECE 611 Advanced Microprocessors– R. Barnes, D. Tabak
4. ECE 612 Real-Time Embedded Systems– K. Hintz
MICROPROCESSOR AND EMBEDDED SYSTEMS
Concentration advisor: Peter Pachowicz
1. ECE 511 Microprocessors– P. Pachowicz
2. ECE 545 Introduction to VHDL– K. Hintz, K. Gaj, project, VHDL, Aldec/ModelSim, Synplicity/Synopsys
3. ECE 611 Advanced Microprocessors– D. Tabak
4. ECE 612 Real-Time Embedded Systems– K. Hintz
DIGITAL SYSTEMS DESIGN: Ken Hintz
Concentration Area Advisors
COMPUTER NETWORKS: Brian Mark
NETWORK AND SYSTEM SECURITY: Kris Gaj
MICROPROCESSOR AND EMBEDDED SYSTEMS:
Peter Pachowicz
ECE 545
Lecture Projects
Project 1 25 %Project 2 10 %Project 3 15 %
Homework 10 %
Midterm exams Midterm 1 20 % in class Midterm 2 20 % take home
Lecture (1)
Lecture 1 - Introduction to VHDL for SynthesisLecture 2 - Data Flow & Structural Modeling of Combinational Logic. Packages and Components.Lecture 3 – Behavioral Modeling of Sequential Logic. Registers, Counters, Shift Registers. Simple Testbenches.Lecture 4 - Introduction to FPGA Devices & ToolsLecture 5 - Finite State Machines
Lecture 6 - Algorithmic State MachinesLecture 7 – Advanced Testbenches, File I/O, MemoryLecture 8 - Mixed Style RTL ModelingLecture 9 - Advanced Examples: Sorting, Average, MAX, MIN
Midterm 1
Lecture 10 - Variables, Functions and ProceduresLecture 11 – ASIC Logic Synthesis with Synopsys Design Compiler
Lecture 12 – Advanced Data Types. Operators and Attributes.Lecture 13 - Timing. Event-Driven SimulationLecture 14 - Behavioral Modeling - The DLX Computer System
Midterm Exam 2
Lecture (2)
TextbooksRequired Textbooks:
Volnei A. Pedroni, Circuit Design with VHDL, The MIT Press, 2004
Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998
Supplementary Textbooks:
Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd Edition, McGraw-Hill, 2005
Peter J. Ashenden, The Designer's Guide to VHDL, 2nd Edition, San Francisco:Morgan Kaufman, 1996, 2002
Midterm exam 1
2 hours 30 minutes
in class
design-oriented
open-books, open-notes
practice exams will be available on the web
Wednesday, October 26th
Tentative date:
Midterm Exam 2
take-home
full design, including logic synthesis and timing analysis
with Synopsys Design Compiler
48 hours
Saturday, Sunday, December 10-11
Tentative date:
Project technologies
FPGA: Field Programmable Gate Arraysand
ASIC: semi-custom Application Specific Integrated Circuits
World of Integrated Circuits
Integrated Circuits
Full-CustomASICs
Semi-CustomASICs
UserProgrammable
PLD FPGA
PAL PLA PML LUT(Look-Up Table)
MUX Gates
• designs must be sent for expensive and time consuming fabrication in semiconductor foundry
• bought off the shelf and reconfigured by designers themselves
Two competing implementation approaches
ASICApplication Specific
Integrated Circuit
FPGAField Programmable
Gate Array
• designed all the way from behavioral description to physical layout
• no physical layout design; design ends with a bitstream used to configure a device
Which Way to Go?
Off-the-shelf
Low development cost
Short time to market
Reconfigurability
High performance
ASICs FPGAs
Low power
Low cost inhigh volumes
Source: [Brown99]
What is an FPGA Chip ?• Field Programmable Gate
Array
• A chip that can be configured by user to implement different digital hardware
• Configurable Logic Blocks and Programmable Switch Matrices
• Bitstream to configure: function of each block & the interconnection between logic blocks
I/O Block
I/O B
lock
I/O Block
I/O B
lock
CLB Structure
COUT
D Q
CK
S
REC
D Q
CK
REC
O
G4G3G2G1
Look-UpTable
Carry&
ControlLogic
O
YB
Y
F4F3F2F1
XB
X
Look-UpTable
F5IN
BYSR
S
Carry&
ControlLogic
CINCLKCE SLICE
CLB Slice
LUT (Look-Up Table) Functionality
• Look-Up tables are primary elements for logic implementation
• Each LUT can implement any function of 4 inputs
x1 x2 x3 x4
y
x1 x2
y
LUT
x1x2x3x4
y
0x1
0x2 x3 x4
0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
y0100010101001100
0x1
0x2 x3 x4
0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
y1111111111110000
x1 x2 x3 x4
y
x1 x2 x3 x4
y
x1 x2
y
x1 x2
y
LUT
x1x2x3x4
y
0x1
0x2 x3 x4
0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
y0100010101001100
0x1
0x2 x3 x4
0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
y0100010101001100
0x1
0x2 x3 x4
0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
y1111111111110000
0x1
0x2 x3 x4
0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
y1111111111110000
Major FPGA Vendors
SRAM-based FPGAs
• Xilinx, Inc.
• Altera Corp.
• Atmel
• Lattice Semiconductor
Flash & antifuse FPGAs
• Actel Corp.
• Quick Logic Corp.
Share over 60% of the market
Xilinx FPGA Families• Old families
– XC3000, XC4000, XC5200
old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs.
• Low-cost families– Spartan/XL – derived from XC4000– Spartan-II – derived from Virtex– Spartan-IIE – derived from Virtex-E– Spartan-3
• High-performance families– Virtex (0.22µm)– Virtex-E, Virtex-EM (0.18µm)– Virtex-II, Virtex-II PRO (0.13µm)– Virtex-4 (0.09µm)
Design process (1)
Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..
Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; );end AES_core;
Specification
VHDL description (Your VHDL Source Files)
Functional simulation
Post-synthesis simulationSynthesis
Design process (2)
Implementation(Mapping, Placing & Routing)
Configuration
Timing simulation
On chip testing
Design Process control from Active-HDL
Simulation Tools
Many others…
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
beginA1<=A when (NEG_A='0') else
not A;B1<=B when (NEG_B='0') else
not B;Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;
with (L1 & L0) selectY1<=MUX_0 when "00",
MUX_1 when "01",MUX_2 when "10",MUX_3 when others;
end MLU_DATAFLOW;
VHDL description Circuit netlist
Logic Synthesis
Synthesis Tools
… and others
Features of synthesis tools
• Interpret RTL code
• Produce synthesized circuit netlist in a standard EDIF format
• Give preliminary performance estimates
• Some can display circuit schematics corresponding to EDIF netlist
Implementation
• After synthesis the entire implementation process is performed by FPGA vendor tools
Mapping
LUT2
LUT3
LUT4
LUT5
LUT1FF1
FF2
LUT0
Placing
CLB SLICES
FPGA
Routing
Programmable Connections
FPGA
Design Process control from Active-HDL
Top Level ASIC Digital Design Flow
RTL Design
Place + Route
Physical Verification
Synthesis
Design Inception
Design Complete
Macro Development
RTL DesignDesign Function Digital Tool
RTL Design
Testbench Developement
Mixed Mode Simulation
FPGA Verification(users discression)
Lint Checking(users discression)
Code Coverage(users discression)
Formal Verification
Cadence NC VerilogMentor Graphis ModelSim
Cadence NC VerilogMentor Graphics ModelSim
Cadence AMS Designer
Xilinx ISE
Cadence Hal
Cadence ICT
Agilent ADSMatlab
Design Inception Design Inception
Synthesis
Synthesis + Macro Development
System Interface Simulation
Cadence Conformal
Synthesis + Macro Development
Synthesis + Macro DevelopmentDesign Function Digital Tool
Synthesis
Static Timing Analysis
Logical Equivalency
DFT
Place + Route
Gate-Level Simulation
RTL
Synopsys DC Cadence RC
Synopsys PrimeTime
Cadence Conformal
Synopsys DFT CompilerCadence RC
Place + Route
Cadence NC VerilogMentor Graphics Modelsim
RTL
Macro Generation
Macro Verification
Macro Rules Generation / Library Generation
Mentor Graphics Calibre
Artisan/Cadence DFII
Artisan
Verification Verification
Place + Route
Floorplan
Macro Placement / Std Cell Placement
Placement-Based Optimization
Clock Tree Synthesis
Route
RC Extraction
Signal Integrity
Design Function Digital Tool
Static Timing
Analysis
Cadence NanoRoute
Cadence Fire&Ice QX
Cadence CeltIC / Voltage Storm
SynopsysPrime-Time
VerificationVerification
Cadence Encounter
Synthesis Synthesis
ATPG Mentor Graphics FastScan
Cadence EncounterMetal Fill
Spare Cells / Decoupling Cap Filler Cells Cadence Encounter
Physical VerificationDesign Function Digital Tool
GDSII Preparation / Schematic Preparation
DRC
LVS
ERC
Simulation Preparation
Back Annotated SimulationLayout Chip Finishing
Cadence DFII Cadence DFII
Cadence NC VerilogCadence Virtuoso
Placed + Routed Design
Placed + Routed Design
Design Complete Design Complete
Mentor Graphics Calibre
Top-Level SimulationSynopsys Nanosim
Cadence AMS Designer
CAD software available at GMU (1)
• Aldec Active-HDL (under Windows)
• ModelSim (under Unix)
• available from all PCs in the ECE educational labs using an X-terminal emulator• available remotely from home using a fast Internet connection
• available in the FPGA Lab, S&T II, room 203
VHDL simulators
• student edition can be purchased on an individual basis ($59.95 + S&H)
CAD software available at GMU (2)
• Synplicity Synplify Pro (under Windows)
• Synopsys Design Compiler (under Unix)• available from all PCs in the ECE educational labs using an X-terminal emulator• available remotely from home using a fast Internet connection
• available in the FPGA Lab, S&T II, room 203
Tools used for logic synthesis
• Xilinx XST (under Windows)
FPGA synthesis
ASIC synthesis
CAD software available at GMU (3)
• Xilinx ISE (under Windows)
• available in the FPGA Lab, S&T II, room 203
Tools used for implementation (mapping, placing & routing) in the FPGA technology
Projects – OverviewProject 1 (25 points) mid-September – October (~6 weeks)
Project 2 (10 points) November (~3 weeks)
Project 3 (15 points) December (~3 weeks)
Application: cryptography OR digital signal processingTechnology: FPGATarget: synthesizable code, timing, resource usage
Application: the same as in Project 1Technology: ASICTarget: revised synthesizable code, synthesis scripts, timing, resource usage, comparison
Application: simple microprocessor/microcontrollerTarget: behavioral code
Projects 1, 2
• choice between two project topics cryptography (e.g., encryption, authentication, hash) digital signal processing (e.g., digital filter, FFT, image processing, etc.)
• both topics specified by the instructor
• initial specification in the form of a - pseudocode and/or flowchart - detailed interface
• design and source code is required to be scalable, i.e., work for different parameters and operand sizes, specified at the time of synthesis
Encryption
A || B = M
A = A + S[0]B = B + S[1]
for i= 1 to r do { A= (AB) <<< B + S[2i] B= (BA) <<< A + S[2i+1] }
C= A || B
Example: Last year’s project - RC5 cipher
DecryptionA || B = C
for i= r downto 1 do { B= ((BS[2i+1]) >>> A) A A= ((A S[2i])>>>B) B }
B = B S[1]A = A S[0]
M= A || B
Encryption/decryptionunit
clockreset
encrypt/decrypt
data input
data available
data read
m
key input
key available
key read
k
Key scheduling unit
Key memory
data output
writefull
n
round key(s)
round number round key(s)
cycle number
Projects 1, 2Optimization Criteria
Maximum ratio
Throughput / Circuit Area
or
Minimum product Latency Circuit Area
Primary timing parameters
Latency Throughput
Circuit
Time to process
a single block of data
Xi
Yi
Number of bits processed
in a unit of time
Circuit
Xi
Xi+1
Xi+2
Yi
Yi+1
Yi+2
Throughput =Block_size · Number_of_blocks_processed_simultaneously
Latency
Project 3from FALL 2004
to be modified in FALL 2005
Using high-level behavioral VHDL describe an 8-bit microcontroller MC68HC11E9, workingin a single-chip mode, with the following simplifications:
1. Inputs and outputs of the microcontroller are reduced toclk, reset, PORTB, and PORTC.
2. Internal registers are reduced to the registersA, B, SP, CC (Condition Codes NZVC), and PC.
3. Internal I/O registers are limited toPORTB at the memory address $1004PORTC at the memory address $1003DDRC at the memory address $1007
System to be implemented
4. Instruction set of the microcontroller is reduced to the following instructions
a. Data transfer instructionsLDAA, LDAB, LDS, STAA, STAB, STS
b. Arithmetic instructionsADDA, ADDB, SUBA, SUBB
c. Logic instructionsANDA, ANDB, ORAA, ORAB, EORA, EORB
d. Data test instructionsCMPA, CMPB
e. Control instructionsBEQ, BNE, BSR, RTS
f. Stack instructionsPSHA, PSHB, PULA, PULB
5. Addressing modes of the microcontroller are reduced to the following modes
a. immediateb. extendedc. inherentd. relative
6. Program is stored in the internal ROM starting at the address $D0007. After reset, PC is set to the address $D000.8. The only parts of 68HC11E9 implemented in your model are:
a. CPUb. RAM (512 B in the range $0000-$01FF)c. ROM (12 kB in the range $D000-$FFFF)d. parallel I/O (PORTB and PORTC)
Features of the model
1. Your model should allow cycle accurate modeling of the circuit behavior.
2. Your model should contain debugging featuresequivalent to the debugging features of the DLX model,discussed in class and described in Ashenden, Chapter 15.
3. Generic parameters passed to the modelshould include a. name of the file with the contents of the internal ROMb. clk-to-output delayc. debugging mode
4. Your model should report all undefined opcodes,treat them as NOP, and proceed to the next ROM address.
Testing and debugging
The behavior of your model should be carefully verifiedusing a testbench instantiating your model with
a. the internal ROM containing a valid program composed of a substantial subset of instructions implemented in the modelb. debugging mode set to the most detailed mode (trace_each_step)
Deliverables
1. All source code files.2. Contents of the internal ROM used for
the model verification, in the hexadecimal notation, and expressed using the corresponding 68HC11 assembly language mnemonics.
3. The detailed log/report generated by your modelfor a given contents of ROM, and with the debuggingmode set to trace_each_step.
All Projects - Organization
• Projects divided into phases• Intermediate code submitted through WebCT at selected checkpoints
and evaluated by the instructor and/or TA• Penalty points for falling behind the schedule (below 50% of the
work that supposed to be done by a certain deadline)• Feedback provided to students on a fair and best effort basis• Final report and codes submitted by WebCT and graded using a full
scale • Contest for the best results (bonus points awarded to the winners)• Penalty and bonus points added to the final grade
Honor Code Rules
• All students are expected to write and debug their codes individually
• Students are encouraged to help and support each other in all problems related to the- operation of the CAD tools,- basic understanding of the problem.