courtesy rk brayton (ucb) and a kuehlmann (cadence) 1 logic synthesis introduction

1Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence)

Logic SynthesisLogic Synthesis

Introduction Introduction

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OrganizationOrganization

Instructor:Instructor: Adnan Aziz ACE 6.120 Email: adnan AT ece utexas edu Web: www.ece.utexas.edu/~adnan GPS: Longitude 30.287253, Latitude -97.736832

Office Hours: MW, 10:00am – 11:00am

http://www.ece.utexas.edu/~adnan

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GradingGrading

• Homework (~ 8 homeworks):Homework (~ 8 homeworks):– purpose is to solidify material and make you think deeper about purpose is to solidify material and make you think deeper about

conceptsconcepts

– team work allowed, but each problem solution should be stated in team work allowed, but each problem solution should be stated in your own wordsyour own words

• Midterms Midterms – 1 after first half1 after first half

– 1 after 75%1 after 75%

• Course project: Course project: – will start about halfway through coursewill start about halfway through course

– final report (like conference paper)final report (like conference paper)

• GraderGrader– TBDTBD

• WebsiteWebsite::– http://www.ece.utexas/edu/~adnan/syn-07

http://www.ece.utexas/edu/~adnan/syn-07

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HomeworkHomework

• About two-thirds writtenAbout two-thirds written– theoretical problems theoretical problems

– hand calculationshand calculations

• One third programming assignments:One third programming assignments:– to be written in C in SIS environmentto be written in C in SIS environment

– assignment is typically:assignment is typically:

• write some application (e.g., build a particular circuit write some application (e.g., build a particular circuit representation)representation)

• run some benchmarks on itrun some benchmarks on it

• code and results (e.g. table of statistics) is to be turned in code and results (e.g. table of statistics) is to be turned in as .tar file in to graderas .tar file in to grader

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Design of Integrated SystemsDesign of Integrated Systems

System LevelSystem Level

Register Transfer LevelRegister Transfer Level

Gate LevelGate Level

Transistor LevelTransistor Level

Layout LevelLayout Level

Mask LevelMask Level

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System LevelSystem Level

• Abstract algorithmic description of high-level behaviorAbstract algorithmic description of high-level behavior– e.g. C-Programming languagee.g. C-Programming language

– abstract because it does not contain any implementation details for abstract because it does not contain any implementation details for timing or datatiming or data

– efficient to get a compact execution model as first design draftefficient to get a compact execution model as first design draft– difficult to maintain throughout project because no link to difficult to maintain throughout project because no link to

implementationimplementation

Port*compute_optimal_route_for_packet(Packet_t *packet,

Channel_t *channel){ static Queue_t *packet_queue;

packet_queue = add_packet(packet_queue, packet); ...}

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RTL LevelRTL Level

• Cycle accurate model “close” to the hardware implementationCycle accurate model “close” to the hardware implementation– bit-vector data types and operations as abstraction from bit-level bit-vector data types and operations as abstraction from bit-level

implementationimplementation

– sequential constructs (e.g. if - then - else, while loops) to support sequential constructs (e.g. if - then - else, while loops) to support modeling of complex control flowmodeling of complex control flow

module mark1;reg [31:0] m[0:8192];reg [12:0] pc;reg [31:0] acc;reg[15:0] ir;

always begin ir = m[pc]; if(ir[15:13] == 3b’000) pc = m[ir[12:0]]; else if (ir[15:13] == 3’b010) acc = -m[ir[12:0]]; ... endendmodule

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Gate LevelGate Level

• Model on finite-state machine levelModel on finite-state machine level– models function in Boolean logic using registers and gatesmodels function in Boolean logic using registers and gates

– various delay models for gates and wiresvarious delay models for gates and wires

– in this lecture we will mostly deal with gate levelin this lecture we will mostly deal with gate level

1ns1ns

4ns4ns3ns3ns

5ns5ns

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Transistor LevelTransistor Level

• Model on CMOS transistor levelModel on CMOS transistor level– depending on application function modeled as resistive switchesdepending on application function modeled as resistive switches

• used in functional equivalence checkingused in functional equivalence checking

– or full differential equations for circuit simulationor full differential equations for circuit simulation

• used in detailed timing analysisused in detailed timing analysis

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Layout LevelLayout Level

• Transistors and wires are laid out as polygons in different Transistors and wires are laid out as polygons in different technology layers such as diffusion, poly-silicon, metal, etc.technology layers such as diffusion, poly-silicon, metal, etc.

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Design of Integrated SystemsDesign of Integrated SystemsR

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Project TimeProject Time

SystemSystem

RTLRTL

LogicLogic

- Design phases overlap to large degrees- Design phases overlap to large degrees- Parallel changes on multiple levels, multiple teams- Parallel changes on multiple levels, multiple teams- Tight scheduling constraints for product- Tight scheduling constraints for product

TransistorTransistor

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Design ChallengesDesign Challenges• Systems are becoming huge, design schedules are getting Systems are becoming huge, design schedules are getting

tightertighter– > 100 Mio gates becoming common for ASICs> 100 Mio gates becoming common for ASICs– > 0.4 Mio lines of C-code to describe system behavior> 0.4 Mio lines of C-code to describe system behavior– > 5 Mio lines of RLT code> 5 Mio lines of RLT code

• Design teams are getting very large for big projectsDesign teams are getting very large for big projects– several hundred peopleseveral hundred people– differences in skillsdifferences in skills– concurrent work on multiple levelsconcurrent work on multiple levels– management of design complexity and communication very difficultmanagement of design complexity and communication very difficult

• Design tools are becoming more complex but still inadequateDesign tools are becoming more complex but still inadequate– typical designer has to run ~50 tools on each componenttypical designer has to run ~50 tools on each component– tools have lots of bugs, interfaces do not line up etc.tools have lots of bugs, interfaces do not line up etc.

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Design ChallengesDesign Challenges

• Decision about design point very difficultDecision about design point very difficult– compromise between performance / costs / time-to-marketcompromise between performance / costs / time-to-market

– decision has to be made 2-3 years before design finisheddecision has to be made 2-3 years before design finished

– design points are difficult to predict without actually doing the design points are difficult to predict without actually doing the designdesign

– scheduling of product cyclesscheduling of product cycles

• Functional verification Functional verification – simulation still main vehicle for functional verification but inadequate simulation still main vehicle for functional verification but inadequate

because of size of design spacebecause of size of design space

– results in bugs in released hardware that is very expensive to results in bugs in released hardware that is very expensive to recover from (different in software ;-)recover from (different in software ;-)

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Design ChallengesDesign Challenges

• Fundamental tradeoffs between different modeling levels:Fundamental tradeoffs between different modeling levels:– modeling detail and team size to maintain modelmodeling detail and team size to maintain model

• high-level models can be maintained by one or two peoplehigh-level models can be maintained by one or two people

• detailed models need to be partitioned which results in a detailed models need to be partitioned which results in a significant communication overheadsignificant communication overhead

– modeling accuracy versus modeling compactnessmodeling accuracy versus modeling compactness

• compact models omit details and give only crude estimations compact models omit details and give only crude estimations for implementationfor implementation

• detailed models are lengthy and difficult to adopt for major detailed models are lengthy and difficult to adopt for major changes in design pointschanges in design points

– simulation speed versus hardware performancesimulation speed versus hardware performance

• high-level models can be simulated fast but cannot be high-level models can be simulated fast but cannot be implemented efficiently with automatic meansimplemented efficiently with automatic means

• low-level models can be made to have a fast implementation low-level models can be made to have a fast implementation but cannot be simulated very fastbut cannot be simulated very fast

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General Design ApproachGeneral Design Approach

• How do engineers build a bridge?How do engineers build a bridge?

• Divide and conquer !!!!Divide and conquer !!!!– partition design problem into many sub-problems which are partition design problem into many sub-problems which are

manageablemanageable

– define mathematical model for sub-problem and find an algorithmic define mathematical model for sub-problem and find an algorithmic solutionsolution

• beware of model limitations and check them !!!!!!!beware of model limitations and check them !!!!!!!

– implement algorithm in individual design tools, define and implement algorithm in individual design tools, define and implement general interfaces between the toolsimplement general interfaces between the tools

– implement checking tools for boundary conditionsimplement checking tools for boundary conditions

– concatenate design tools to general design flows which can be concatenate design tools to general design flows which can be managedmanaged

– see what doesn’t work and start oversee what doesn’t work and start over

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Design AutomationDesign Automation

• Design Automation is one of the most advanced areas in practical Design Automation is one of the most advanced areas in practical computer sciencecomputer science– many problems require sophisticated mathematical modelingmany problems require sophisticated mathematical modeling– many algorithms are computationally hard and require advanced and many algorithms are computationally hard and require advanced and

fine-tuned heuristics to work on realistic problem sizesfine-tuned heuristics to work on realistic problem sizes– boundary conditions need to be well declared and synchronized between boundary conditions need to be well declared and synchronized between

different tools (patchwork to cover all wholes)different tools (patchwork to cover all wholes)

• Two common pitfalls in CAD researchTwo common pitfalls in CAD research– problem is looking for a solution:problem is looking for a solution:

• problem scope is too big, makes modeling difficult or algorithms problem scope is too big, makes modeling difficult or algorithms don’t scaledon’t scale

• problem scope is too small, solutions are not good enoughproblem scope is too small, solutions are not good enough– solution is looking for a problem:solution is looking for a problem:

• model was oversimplified because real problem was too complex model was oversimplified because real problem was too complex with too many boundary conditionswith too many boundary conditions

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Key to SuccessKey to Success

• Fine-tuned combination of Design Methodology and ToolsFine-tuned combination of Design Methodology and Tools– addresses algorithmic complexity by requiringaddresses algorithmic complexity by requiring

• manual partitioning of the problemmanual partitioning of the problem

• manual input of hints/suggestionsmanual input of hints/suggestions

• manual manual iterationsiterations to drive tool application to best solution to drive tool application to best solution

– makes CAD systems and design flows very complex and difficult to makes CAD systems and design flows very complex and difficult to managemanage

Problem spaceProblem space Tools applicableTools applicable

Practical combination through design methodologyPractical combination through design methodology

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Examples of Divide and ConquerExamples of Divide and Conquer

• RLT cycle simulation does only evaluate the next state logic of RLT cycle simulation does only evaluate the next state logic of the circuits, timing is assumed to be correctthe circuits, timing is assumed to be correct– combination of static timing analysis, formal equivalence checking, combination of static timing analysis, formal equivalence checking,

and cycle simulation allows separation of issuesand cycle simulation allows separation of issues

– cycle simulation avoids expensive event scheduling and processing cycle simulation avoids expensive event scheduling and processing and performs significantly fasterand performs significantly faster

• However:However:– timing analysis is conservative with respect to the achievable clock timing analysis is conservative with respect to the achievable clock

cycle timecycle time

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• Static timing analysis assumed simple gate delay modelsStatic timing analysis assumed simple gate delay models– complexity of static timing analysis becomes linear (simple longest complexity of static timing analysis becomes linear (simple longest

and shortest paths analysis in circuit implementation)and shortest paths analysis in circuit implementation)

– very efficient implementation of incremental static timing analysis very efficient implementation of incremental static timing analysis which is needed in the inner loop of the technology dependent part which is needed in the inner loop of the technology dependent part of logic synthesisof logic synthesis

• However:However:– actual gate delay varies a lot in realityactual gate delay varies a lot in reality

• models often assume average fan-out rather than actual gate models often assume average fan-out rather than actual gate loadload

– delay model assumes ideal signalsdelay model assumes ideal signals

• slew dependency ignoredslew dependency ignored

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• Logic synthesis assumes ideal gates which are independent of Logic synthesis assumes ideal gates which are independent of physical environmentphysical environment– standard cell place and route technology has made logic synthesis standard cell place and route technology has made logic synthesis

possiblepossible

• gates are heavily over-designed to be functional in a wide gates are heavily over-designed to be functional in a wide variety of combinations (e.g. range of fan-out gates possible, variety of combinations (e.g. range of fan-out gates possible, different wire loadsdifferent wire loads

• layout placement and route done in standard rows that layout placement and route done in standard rows that minimize latch-up effects and optimize power and clock wiringminimize latch-up effects and optimize power and clock wiring

• However:However:• layout implementation remains sub-optimal because cells are layout implementation remains sub-optimal because cells are

designed for worst case application and with large safety designed for worst case application and with large safety margins with respect to environmentmargins with respect to environment

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• Logic synthesis uses crude model to estimate circuit areaLogic synthesis uses crude model to estimate circuit area• literal count or simple table-lookup for gates sizes allows fast literal count or simple table-lookup for gates sizes allows fast

comparison of different implementation choicescomparison of different implementation choices

• However:However:• actual gate size can vary to a very large degree depending on actual gate size can vary to a very large degree depending on

load and timing requirementload and timing requirement

• area for wiring completely ignoredarea for wiring completely ignored

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• Formal equivalence checking assumes identical state encoding Formal equivalence checking assumes identical state encoding of the two designs to be comparedof the two designs to be compared– reduces the general equivalence checking problem to reduces the general equivalence checking problem to

combinational equivalence checking which is computationally less combinational equivalence checking which is computationally less complexcomplex

– exploitation of structural similarities between designs to be exploitation of structural similarities between designs to be compared makes tools applicable for huge (multi-million gate) compared makes tools applicable for huge (multi-million gate) designsdesigns

– automatic algorithms for identifying register correspondence automatic algorithms for identifying register correspondence compensate to some extent for limited modelcompensate to some extent for limited model

• However:However:– combinational verification model cannot handle sequential combinational verification model cannot handle sequential

verification problemsverification problems

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Full Custom Design FlowFull Custom Design Flow

• Application: ultra-high performance designs Application: ultra-high performance designs – general-purpose processors, DSPs, graphic chips, internet routers, general-purpose processors, DSPs, graphic chips, internet routers,

games processors etc.games processors etc.

• Target: very large markets with high profit marginsTarget: very large markets with high profit margins– e.g. PC businesse.g. PC business

• Complexity: very complex and labor intenseComplexity: very complex and labor intense– involving large teamsinvolving large teams– high up-front investments and relatively high riskshigh up-front investments and relatively high risks

• Role of Logic Synthesis:Role of Logic Synthesis:– limited to components that are not performance critical or that might limited to components that are not performance critical or that might

change late in design cycle (due to designs bugs found late)change late in design cycle (due to designs bugs found late)• control logiccontrol logic• non-critical data paths logicnon-critical data paths logic

– bulk of data-path components and fast control logic are manually bulk of data-path components and fast control logic are manually crafted for optimal performancecrafted for optimal performance

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Full Custom Design FlowFull Custom Design Flow

ISA SpecificationISA Specification

RTL SpecRTL Spec

Gate Level NetlistGate Level Netlist

Transistor Level CircuitTransistor Level Circuit

LayoutLayout

Circuit SimulationCircuit Simulation

SimulationSimulation

Design Rule CheckerDesign Rule Checker

FormalFormalEquivalenceEquivalence

CheckingChecking



Manual or Manual or semi-automaticsemi-automatic

DesignDesign

Extract&CompareExtract&Compare

• Incomplete picture:Incomplete picture:

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ASIC Design FlowASIC Design Flow

• Application: general IC marketApplication: general IC market– peripheral chips in PCs, toys, handheld devices etc.peripheral chips in PCs, toys, handheld devices etc.

• Target: small to medium markets, tight design schedulesTarget: small to medium markets, tight design schedules– e.g. consumer electronicse.g. consumer electronics

• Complexity of design: standard design style, quite predictableComplexity of design: standard design style, quite predictable– standard flows, standard off-the-shelf toolsstandard flows, standard off-the-shelf tools

• Role of Logic Synthesis:Role of Logic Synthesis:– used on large fraction of design except for special blocks such as used on large fraction of design except for special blocks such as

RAM’s, ROM’s, analog componentsRAM’s, ROM’s, analog components

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ASIC Design FlowASIC Design Flow

Informal SpecificationInformal Specification

RTL SpecRTL Spec

Gate Level NetlistGate Level Netlist

Modifies Gate Level NetlistModifies Gate Level Netlist Static Timing AnalysisStatic Timing Analysis

FormalFormalEquivalenceEquivalence

CheckingChecking



Manual ChangesManual Changesto fix timing to fix timing

• Incomplete picture:Incomplete picture:

ASIC FoundryASIC FoundryTest Logic InsertionTest Logic Insertion

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What is Logic Synthesis?What is Logic Synthesis?

DD

XX YY

Given:Given: Finite-State Machine F(X,Y,Z, , ) where:Finite-State Machine F(X,Y,Z, , ) where: X: Input alphabetX: Input alphabetY: Output alphabetY: Output alphabetZ: Set of internal statesZ: Set of internal states : X x Z Z (next state function): X x Z Z (next state function) : X x Z Y (output function): X x Z Y (output function)

Target:Target: Circuit C(G, W) where:Circuit C(G, W) where:

G: set of circuit components g {Boolean gates,G: set of circuit components g {Boolean gates, flip-flops, etc}flip-flops, etc}W: set of wires connecting GW: set of wires connecting G

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Objective Function for SynthesisObjective Function for Synthesis

• Minimize areaMinimize area– in terms of literal count, cell count, register count, etc.in terms of literal count, cell count, register count, etc.

• Minimize powerMinimize power– in terms of switching activity in individual gates, deactivated circuit in terms of switching activity in individual gates, deactivated circuit

blocks, etc.blocks, etc.

• Maximize performanceMaximize performance– in terms of maximal clock frequency of synchronous systems, in terms of maximal clock frequency of synchronous systems,

throughput for asynchronous systemsthroughput for asynchronous systems

• Any combination of the aboveAny combination of the above– combined with different weightscombined with different weights

– formulated as a constraint problem formulated as a constraint problem

• ““minimize area for a clock speed > 300MHz”minimize area for a clock speed > 300MHz”

• More global objectivesMore global objectives– feedback from layoutfeedback from layout

• actual physical sizes, delays, placement and routingactual physical sizes, delays, placement and routing

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Constraints on SynthesisConstraints on Synthesis

• Given implementation style:Given implementation style:– two-level implementation (PLA, CAMs)two-level implementation (PLA, CAMs)

– multi-level logicmulti-level logic

– FPGAsFPGAs

• Given performance requirementsGiven performance requirements– minimal clock speed requirementminimal clock speed requirement

– minimal latency, throughputminimal latency, throughput

• Given cell libraryGiven cell library– set of cells in standard cell libraryset of cells in standard cell library

– fan-out constraints (maximum number of gates connected to fan-out constraints (maximum number of gates connected to another gate)another gate)

– cell generatorscell generators

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Instability of Logic SynthesisInstability of Logic Synthesis

Change in area and performance (15 testcases and 20 libraries)

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-4

-2

0

2

4

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-40 -30 -20 -10 0 10 20 30

area (%)

per

form

ance

(%

)

Experiment to write out netlist in middle of synthesis run and read back in w/o changeExperiment to write out netlist in middle of synthesis run and read back in w/o change

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Brief History of Logic SynthesisBrief History of Logic Synthesis

• 1960s: first work on automatic test pattern generation used for 1960s: first work on automatic test pattern generation used for Boolean reasoningBoolean reasoning– D-AlgorithmD-Algorithm

• 1978: Formal Equivalence checking introduced at IBM in 1978: Formal Equivalence checking introduced at IBM in production for designing mainframe computersproduction for designing mainframe computers– SAS tool based on the DBA algorithmSAS tool based on the DBA algorithm

• 1979: IBM introduced logic synthesis for gate array based main 1979: IBM introduced logic synthesis for gate array based main frame designedframe designed– LSS, next generation is BooleDozerLSS, next generation is BooleDozer

• End 1986: Synopsys foundedEnd 1986: Synopsys founded– first product “remapper” between standard cell librariesfirst product “remapper” between standard cell libraries

– later extended to full blown RTL synthesislater extended to full blown RTL synthesis

• 1990s other synthesis companies enter the marker1990s other synthesis companies enter the marker– Ambit, Compass, Synplicity. Magma, Monterey, ...Ambit, Compass, Synplicity. Magma, Monterey, ...

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Why learning about Logic Synthesis?Why learning about Logic Synthesis?

• Logic synthesis is the core of today's CAD flows for IC and Logic synthesis is the core of today's CAD flows for IC and system designsystem design– course covers many algorithms that are used in a broad range of course covers many algorithms that are used in a broad range of

CAD toolsCAD tools

– basis for other optimization techniques, e.g. embedded softwarebasis for other optimization techniques, e.g. embedded software

– basis for functional verification techniquesbasis for functional verification techniques

• Most algorithms are computationally hardMost algorithms are computationally hard– covered algorithms and flows are good example for approaching covered algorithms and flows are good example for approaching

hard algorithmic problemshard algorithmic problems

– course covers theory as well as implementation detailscourse covers theory as well as implementation details

– demonstrates an engineering approaches based on theoretical demonstrates an engineering approaches based on theoretical solid but also practical solutionssolid but also practical solutions

• very few research areas can offer this combinationvery few research areas can offer this combination

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Course OutlineCourse Outline

• Representation of Boolean functions and basic algorithmsRepresentation of Boolean functions and basic algorithms– Boolean functions, formulas, circuits, cube representations, BDDsBoolean functions, formulas, circuits, cube representations, BDDs

– efficient data structures and algorithms for manipulation and efficient data structures and algorithms for manipulation and Boolean reasoning Boolean reasoning

– SATSAT

• Functional optimization of combinational circuitsFunctional optimization of combinational circuits– two-level circuitstwo-level circuits

• Quine McCluskeyQuine McCluskey

• EspressoEspresso

– multi-level circuitsmulti-level circuits

• algebraic methodsalgebraic methods

• structural transformation-based methodsstructural transformation-based methods

• technology mappingtechnology mapping

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• TimingTiming– timing models and timing analysistiming models and timing analysis

– timing optimizationtiming optimization

• Functional Optimization of Sequential CircuitsFunctional Optimization of Sequential Circuits– retimingretiming

– synchronous versus asynchronous circuitssynchronous versus asynchronous circuits

– state assignment and state minimizationstate assignment and state minimization

– reachability analysisreachability analysis

– clock skew optimizationclock skew optimization

• Low-power SynthesisLow-power Synthesis– power analysispower analysis

– low-power synthesislow-power synthesis

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• TestingTesting– testing problem and test modelstesting problem and test models

– automatic test pattern generation (ATPG)automatic test pattern generation (ATPG)

• VerificationVerification– formal equivalence checkingformal equivalence checking

– verification planningverification planning

courtesy rk brayton (ucb) and a kuehlmann (cadence) 1 logic synthesis introduction

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