CPE 626 CPU Resources:Adders & Multipliers

Aleksandar MilenkovicE-mail: milenka@ece.uah.edu

Web: http://www.ece.uah.edu/~milenka

2

Outline

Full Adder Ripple Carry Adder Carry-Look-Ahead Adder Manchester Adders Carry Select Adder Carry Skip Adder Conditional Sum Adder Hybrid Designs

3

Full Adder

Inputs data inputs A, B carry in Cin

Outputs sum S carry out Cout

inout

ininin

inin

inininin

C)BA(BAC

CBACBACBA

C)BABA(C)BABA(

CBACBACBACBAS

4

Full Adder

)BA(CBA

)BA(CBAC

CBAS

in

inout

in

A

BS

Cin

Cout

5

Full Adder

outinin C)CBA(CBAS

GND

Cin

A

A

Vdd

B

A

Cin

B

B

A

B

GND

Cout

A B Cin

A B Cin

A

B

Cin

A

B

CinGND

S

Vdd

6

Transmission-Gate Adder (1)

A = 1 => -A = 0 => TG is open => out = -B

A = 0 => -A = 1 => TG is closed => out = B

A = 1 => -A = 0 => TG is closed => out = B

A = 0 => -A = 1 => TG is open => out = -B

V DD

AA

A

A

B

BA TG XOR V DD

AA

A

A

B

)B,A(XNORTG XNOR

7

Transmission-Gate Adder (2)

inin

inin

in

CC1S1BA

CC0S0BA

CBAS

AB

AB

BA

BA

Cin 0

1C

B 0

1

SUM

BA

BA

Cout

inC

)BA(CBA

)BA(CBAC

in

inout

8

Ripple Carry Adder - RCA (1)

Method 1 G[i] = A[i]*B[i] P[i] = A[i]B[i] C[i] = G[i] + P[i]*C[i-

1] S[i] = P[i] C[i-1]

Method 2 G[i] = A[i]*B[i] P[i] = A[i] + B[i] C[i] = G[i] + P[i]*C[i-

1] S[i] = A[i]B[i]C[i-1]

A[i]

B[i]S[i]

C[i]

C[i+1]

P[i]

G[i]

9

Ripple Carry Adder - RCA (2)

Replace AND-OR pair with fast 2-inputs NAND gates

RCA delay is proportional to n and is limited by

the propagation of the carry signal through all of the stages

A[i+1]

B[i+1]S[i+1]

C[i+2]

P[i]

G[i]

A[i]

B[i]S[i]

C[i]

C[i+1]

P[i]

G[i]

10

Ripple Carry Adder - RCA (3)

iii

iiii

iiiii1i

BAP

CPBA

C)BA(BAC

iii

iiii1i

iiiii

iiiiii

iiiiiii

iiiii1i

BAP

)CP()BA(C

C)BA(BA

CBCABA

)CBABA()BA(

)CBA()BA(C

ii1iii1i

ii1i

1i1i1i

CP2CorCP2C

BA1C

2C1CC

iii1i

ii1i

1i1i1i

2C1CP3C

BA4C

4C3CC

Used in odd stages!Used in even stages!

11

Ripple Carry Adder - RCA (4) Carry equations

C[i+1] = A[i]*B[i] + P[i]*C[i]orC[i+1] = (A[i] + B[i])*(P[i]’ + C[i])P[i]’ = NOT(P[i])

Even stages C1[i+1]’ = P[i]*C3[i]*C4[i] C2[i+1] = A[i] + B[i] C[i+1] = C1[i]*C2[i]

Odd stages C3[i+1]’ = P[i]*C1[i]*C2[i] C4[i+1]’ = A[i]*B[i] C[i+1] = C3[i]’ + C4[i]’

Inputs to stage zero:C3[0] = C4[0] = ‘0’

A[i]

B[i]S[i]

C2[i]

Oddstages

C1[i]

A[i+1]

B[i+1]S[i+1]

C2[i+2]

Evenstages

C1[i+2]

C[i]

C[i+1]

C4[i+1] C3[i+1]

12

Carry-Look-Ahead Adder – CLA (1) Idea: speed up carry computation – Ci+1 = Gi + Pi*Ci

Propagate: Pi = Ai + Bi

if Pi = 1, then carry from (i-1)th stage is propagated Generate: Gi = Ai*Bi

if Gi = 1 there is carry out

2i2i1ii2i1ii1iii

2i2i2i1ii1iii

1i1ii1iii

1i1i1iii

iii1i

iii

iii

CPPPGPPGPG

)CPG(PPGPG

CPPGPG

)CPG(PG

CPGC

BAG

BAP

iiii CBAS

13

Carry-Look-Ahead Adder – CLA (2)

00123

01231232334

00120121223

0010112

0001

CPPPP

GPPPGPPGPGC

CPPPGPPGPGC

CPPGPGC

CPGC

PG GeneratorCarry Generate

BlockSum Generator

G0

P0

C0

C1

C2

C3S3

S2

S1

S0

B3

A3

P3

G3

G2

G1

P1

P2

B2

A2

B1

A1

B0

A0

P2

P1

P0

C0

P2P1G0

P2

G1

G2

C3

P0

C0

G0

C1

14

Carry-Look-Ahead Adder – CLA (3)

0012301231232334

00120121223

0010112

0001

CPPPPGPPPGPPGPGC

CPPPGPPGPGC

CPPGPGC

CPGC

clk

P0

V DD

C1

clk

C0

G0

clk

P0

V DD

C2

clk

C0

G0

P1

G1

Domino implementation (Dynamic Carry Gates)

15

Carry-Look-Ahead Adder – CLA (4)

0012301231232334

00120121223

0010112

0001

CPPPPGPPPGPPGPGC

CPPPGPPGPGC

CPPGPGC

CPGC

0012301231232334 CPPPPGPPPGPPGPGC

030304 CPGC

003478111215

0347811121547811121581112151215

0034781103478114781181112151215

121215121516

00347811034781147811811

00347034747811811

881181112

00347034747

003034747447478

CPPPP

GPPPGPPGPG

)CPPPGPPGPG(PG

CPGC

CPPPGPPGPG

)CPPGPG(PG

CPGC

CPPGPG

)CPG(PGCPGC

16

Carry-Look-Ahead Adder – CLA (5)

A 3:0

A4

B 3:0

S 3:0

A 7-4

A4

B 7-4

S 7-4

A 11-8

A4

B 11-8

S 11-8

A 15-12

A4

B 15-12

S 15-12

CGC 0

C 0C 4C 8C 12 P 3-0G 3-0P 7-4G 7-4P 11-8G 11-8P 15-12G 15-12

G 15-0 P 15-0

17

Brent-Kung CLA a) lookahead

terms b) CLG cell c) cells can be

rearranged into tree

d) simplified representations for part a)

e) simplified representation for part c)

f) lookahead logic for 8-bit adder

g) Brent-Kung adderReduces delay, increases the regularity, reduces the number of

unnecessary switching events (power)

18

Manchester Adder Circuits (1)

iii1i

iii

iii

CPGC

BAG

BAP

clk

G i

V DD

clk

P i

iC 1iC

clk

G 0

V DD

clk

P 0

0C 1C C 1C 0

19

Manchester Adder Circuits (2)

Dynamic Stage Static Stage MUX stage

iii BAP

iC

P i

iP

G i

V DD

1iC

G i

iP

iC

iG

P i

iP

iP

1iC

clk

G i

V DD

clk

P i

iC 1iC

iii1i CPGC

i1ii

i1ii

CC1P

GC0P

20

4-bit Manchester Adder

clk

V DD

clk

0C

0CP

P G

P 0 G 0

0P

1C

P

P G

P 1 G 1

1P

2C

P

P G

P 2 G 2

2P

2C

P

P G

P 3 G 3

3P

3C 3C

B i P i

iCS i

A i

B i

A i

G i

P i

iP

21

Carry Bypass

0012301231232334 CPPPPGPPPGPPGPGC

0C

P

P G

P 0 G 0

0P

1C

P

P G

P 1

1P

2C

P

P G

P 2 G 2

2P

2C

P

P G

P 3 G 3

3P

3C 3C0C

G 1

P 0

P 1

P 2

P 3

22

Carry Select Adder (1)

41

81

121

160

81

121

160

121

160

16

41

81

120

81

120

121

160

16

121

160

1616

41

81

120

81

120

12

41

80

81

120

12

81

120

1212

41

80

8447478

4747447471

8

47447470

8

CCCCCCCCCC

)CCCCCC(CC

CCCC

CCCCCC

)CCC(CC

CCCC

CCCCPGC

PGCPGC

GCPGC

Compute 2 versions of the addition with different carry-ins, one assuming that the carry-in is 0 and another assuming that it is 1

23

Carry Select Adder (2)

C 0

A 3:0

A4

B 3:0

S 3:0

A 7:4

A4

B 7:4

C 4

0

A4

B 7:4

0

1

MP

0

1

A 7:4

S 7:40

S 7:41

S 7:4

C 4

C 80

C 81

A 11:8

A4

B 11:8

C 8

0

A4

B 11:8

0

1

MP

0

1

A 11:8

S 11:80

S 7:41

S 11:8

C 120

C 121

C 80

C 4

C 81

C 8

C 8

C 121

C 12

C 120

A 15:12

A4

B 15:12

C 12

A4

B 15:12

0

1

MP

0

1

A 15:12

S 15:12

C 160

C 161

S 15:121

S 15:120

0

C 8

C 161

C 16

C 160

24

Carry Skip Adder: Motivation

012303

012312323303

003034

0012301231232334

PPPPP

GPPPGPPGPGG

CPGC

CPPPPGPPPGPPGPGC

Computing P3-0 is much simpler than computing G0-3

Let’s compute only P3-0!

25

Carry Skip Adder

012303

012312323303

003034

PPPPP

GPPPGPPGPGG

CPGC

C 0

A 3:0

A4

B 3:0

S 3:0

A 7:4 B 7:4 A 11:8 B 11:8

C 4 A4C 8

S 7:4

P 7:4

A4C 12

S 11:8

P 11:8

A 15:12 B 15:12

A4

S 15:12

C 16

Carries begin rippling simultaneously through each block; If any block generates a carry, then the carry out will be true, even the carry-in may not be not true yet. If at the start of each add operation the carry-in to each block is 0, then correct carry-outs will be generated – carry-out can be thought of as if it is the G signal

Practical only if the carry-in signals can be easily cleared at the start of each operation – e.g. precharging CMOS

26

Carry Skip Adder: Analysis Assume

it takes 1 time unit for signal to propagate through two logic level

n bits wide adder blocks of size k

It will take k units for a carry to ripple through a block of size k

Critical path k units for the first block n/k – 2 units to skip the blocks k units to ripple through the last block

Increase the efficiency by varying the blocks size 20 bits (4, 4, 4, 4, 4,): Delay = 4 + 3 + 4 = 11 20 bits (2, 5, 6, 5, 2): Delay = 9

27

Conditional Sum Adder (1)

iiii CBAS

iiiii1i C)BA(BAC

)B,A(XNORBA1BAS

BA0BAS

iiiiii1i

iiii0i

iiiiii1

1i

iiiiii0

1i

BA1)BA(BAC

BA0)BA(BAC

28

Conditional Sum Adder (2)

29

Conditional Sum Adder (3)A 0 0 1 0 1 1 0 1

B 1 0 1 1 0 1 1 0

0 Si0 1 0 0 1 1 0 1 1 0

Ci0 0 0 1 0 0 1 0 0

Si1 0 1 1 0 0 1 0 0 1

Ci1 1 0 1 1 1 1 1 1

1 Si0 1 0 0 1 0 0 1 1 0

Ci0 0 1 1 0

Si1 1 1 1 0 0 1 0 0 1

Ci1 0 1 1 1

2 Si0 1 1 0 1 0 0 1 1 0

Ci0 0 1

Si1 1 1 1 0 0 1 0 0 1

Ci1 0 1 1

3 S0 1 1 1 0 0 0 1 1 0

0

S1 1 1 1 0 0 1 0 0 1

0

30

Hybrid Designs: An Example

Combine CLA (Carry Look-Ahead) with RCA