cpre 588 embedded computer systems - computer...
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CprE 588Embedded Computer Systems
Prof. Joseph ZambrenoDepartment of Electrical and Computer EngineeringIowa State University
Lecture #5 – System-Level Design with SpecC
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.2
System-On-Chip Design
Specification+ constraints
Memory
Memory
µProcessor
Interface
Comp.IP
BusInterface
Interface
Interface
Custom HW
System architecture+ estimates
ProcessorsIPs
MemoriesBusses
RTL/IS Implementation+ results
RegistersALUs/FUsMemories
Gates
Mem RFState
Control
ALU
Datapath
PC
Control Pipeline
State
IF FSM
State
IF FSMIP Netlist
RAM
IR
Memory
R. Domer, The SpecC System-Level Design Language and Methodology, Center for Embedded Systems, University of California-Irvine, 2001.
• Specification to architecture to implementation• Behavior to structure
1. System level: system specification to system architecture2. RT/IS level: component behavior to component microarchitecture
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.3
Abstraction LevelsStructure /
Implementation detailOrder /
Timing detail
Functional Untimed(causality)Specification
Structural Timed (estimated)
Architecture
Gate netlist
Gatedelays
Manufacturing
Bus-functional
Timing-accurate
Communication
RTL/IS Cycle-accurate
Implementation
Application domain MOCs (Matlab, SDF, etc.)Requirements Constraints
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.4
SpecC MethodologySystem design Validation flow
Specification model
Algor.IP
Proto.IP
Architecture model
Communication synthesis
Communication model
Comp.IP
Estimation
ValidationAnalysis
Compilation Simulation model
Estimation
ValidationAnalysis
Compilation Simulation model
Estimation
ValidationAnalysis
Compilation Simulation model
Implementation model
Softwarecompilation
Interfacesynthesis
Hardwaresynthesis
Backend Estimation
ValidationAnalysis
Compilation Simulation model
RTOSIP
RTLIP
Architecture exploration
Capture
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.5
Specification Model
Specification model
Architecture exploration
Architecture model
Communication model
Implementation model
Communication synthesis
Backend
• High-level, abstract model• Pure system functionality• Algorithmic behavior• No implementation details
• No implicit structure / architecture• Behavioral hierarchy
• Untimed• Executes in zero (logical) time• Causal ordering• Events only for synchronization
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.6
Specification Model Example
B1
v1
v2
e2
B1
B2 B3
• Simple, typical specification model• Hierarchical parallel-serial composition• Communication through ports and variables, events
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.7
Specification Model Example (cont.)
behavior B2B3( in int v1 ) {
int v2; // variablesevent e2;
B2 b2( v1, v2, e2 ); // childrenB3 b3( v1, v2, e2 );
void main(void) {par {b2.main(); b3.main();
}};
behavior Design() {
int v1; // variables
B1 b1 ( v1 ); // childrenB2B3 b2b3( v1 );
void main(void) {b1.main();b2b3.main();
}};
SpecC design hierarchy:
B1
v1
v2
e2
B1
B2 B3
1
5
10
15
20
25
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.8
Specification Model Example (cont.)
B1
v1
v2
e2
B1
B2 B3
• Leaf behaviors• C algorithms• Port accesses
behavior B3( in int v1,in int v2,in event e2 )
{void main(void) { // read v1
…wait( e2 ); // wait for syncf3( v1, v2, … ); // consume v2…
}};
1
5
10
behavior B2( in int v1, out int v2, out event e2 )
{void main(void) { // read v1
…v2 = f2( v1, … ); // produce v2notify( e2 ); // synchronize…
}};
1
5
10
behavior B1( out int v1 ) {
void main(void) { …v1 = … // write v1…
};
1
5
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.9
Communication
B2 B3c2
v2
e2
B2 B3
• Message-passing• Abstract
communication and synchronization
• Encapsulate in channel
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.10
Message-Passing Channel
ISen
d
IRec
v
ChMP
• Blocking, unbuffered message-passing
interface ISend {void send( void *d, int size );
};
interface IRecv {void recv( void *d, int size );
};
Channel interfaces:1
5
channel ChMP() implements ISend, IRecv{
void *buf = 0;event eReady, eAck;
void send( void *d, int size ) {buf = malloc( size );memcpy( buf, d, size );notify( eReady );wait( eAck );free( buf );buf = 0;
}
void recv( void *d, int size ) {if( !buf ) wait( eReady );memcpy( d, buf, size );notify( eAck );
}};
Simulation model:1
5
10
15
20
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.11
Message-Passing Specification
B2 B3c2
B1
v1
B1
behavior B2( in int v1, ISend c2 ) {
void main(void) { …v2 = f2( v1, … );
c2.send( &v2, sizeof(v2) );…
}};
c2.send( &v2, sizeof(v2) );c2.send( &v2, sizeof(v2) );
ISend c2ISend c21
5
10
behavior B3( in int v1, IRecv c2 ) {
void main(void) {…c2.recv( &v2, sizeof(v2) );
f3( v1, v2, …); …
}};
IRecv c2IRecv c2
c2.recv( &v2, sizeof(v2) );c2.recv( &v2, sizeof(v2) );
1
5
10
behavior B2B3( in int v1 ) {
ChMP c2();
B2 b2( v1, c2 );
B3 b3( v1, c2 );
void main(void) {par {
b2.main(); b3.main();
}}
};
ChMP c2;ChMP c2;
c2c2
c2c2
1
5
10
15
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.12
Architecture Exploration
Specification model
Architecture exploration
Architecture model
Communication model
Implementation model
Communication synthesis
Backend
• Component allocation / selection• Behavior partitioning• Variable partitioning• Scheduling
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.13
Allocation, Behavior Partitioning
• Allocate PEs• Partition behaviors• Globalize
communicationB2 B3c2
B1
v1
B1
Additional level of hierarchy to model PE structure
PE1
PE2
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.14
Model after Behavior Partitioning
B3
B13rcv
B34snd
B2
B1B1
B13snd
B34rcv
PE1
c2
v1
cb13
cb34
PE2
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.15
Synchronization
B13rcv
B34snd
B13snd
B34rcv
cb13
cb34
behavior BSnd( ISend ch ) {
void main(void) {ch.send( 0, 0 );
}};
behavior BRcv( IRecv ch ) {
void main(void) {ch.recv( 0, 0 );
}};
Preserve execution semantics
1
5
1
5
• For each component-crossing transition• Synchronization behavior pair• Synchronize over blocking message-passing
channel
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.16
After Behavior Partitioningbehavior PE1( int v1,
ISend cb13,ISend c2,IRecv cb34 )
{B1 b1 ( v1 );B2B3 b2b3( v1, cb13, c2, cb34 );
void main(void) {b1.main();b2b3.main();
}};
B2
B1B1
B13snd
B34rcv
PE1 1
5
10
behavior B2B3( in int v1, ISend cb13,ISend c2,IRecv cb34 )
{B2 b2 ( v1, c2 );B3Stub b3stub( cb13, cb34 );
void main(void) {par {
b2.main(); b3stub.main();
}}
};
1
5
10
15
behavior B3Stub( ISend cb13, IRecv cb34 ) {
BSnd b13snd( cb13 );BRcv b34rcv( cb34 );
void main(void) {b13snd.main();b34rcv.main();
}};
1
5
10
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.17
After Behavior Partitioning (cont.)
behavior PE2( in int v1,IRecv cb13,IRecv c2,ISend cb34)
{BRcv b13rcv( cb13 );B3 b3 ( v1, c2 );BSnd b34snd( cb34 );
void main(void) {
b13rcv.main();b3.main();b34snd.main();
}};
B3
B13rcv
B34snd
PE21
5
10
15
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.18
After Behavior Partitioning (cont.)
B3
B13rcv
B34snd
B2
B1B1
B13snd
B34rcv
PE1
c2
v1
cb13
cb34
PE2
behavior Design() {int v1;ChMP cb13, c2, cb34;
PE1 pe1( v1, cb13, c2, cb34 );PE2 pe2( v1, cb13, c2, cb34 );
void main(void) { par { pe1.main(); pe2.main(); }
}};
1
5
10
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.19
Variable Partitioning
B3
B13rcv
B34snd
B2
B1B1
B13snd
B34rcv
PE1
c2
v1
cb13
cb34
PE2
v1 v1
• Shared memory vs. message passing implementation• Map global variables to local memories• Communicate data over message-passing channels
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.20
Message-Passing Model
B3
B13rcv
B34snd
B2
B1B1
B13snd
B34rcv
PE1
c2
v1
cb13
cb34
PE2
v1
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.21
Message-Passing Communication
B13rcvB13snd
v1
cb13
v1
behavior B13Snd( in int v1 , ISend ch ) {
void main(void) {ch.send( &v1, sizeof(v1) );
}};
ch.send( &v1, sizeof(v1) );ch.send( &v1, sizeof(v1) );
in int v1in int v1 behavior B13Rcv( IRecv ch, out int v1 ) {
void main(void) {ch.recv( &v1, sizeof(v1) );
}};
ch.recv( &v1, sizeof(v1) );ch.recv( &v1, sizeof(v1) );
out int v1out int v1
Preserve shared semantics of variables
1
5
1
5
• Keep local variable copies in sync• Communicate updated values at synchronization points• Transfer control & data over message-passing channel
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.22
Message-Passing Modelbehavior PE1( ISend cb13,
ISend c2,IRecv cb34)
{int v1;
B1 b1 ( v1 );B2B3 b2b3( v1, cb13, c2, cb34 );
void main(void) {b1.main();b2b3.main();
}};
int v1;int v1;
B2
B1B1
B13snd
B34rcv
PE1
v1
1
5
10
behavior B3stub( in int v1 , ISend cb13,IRecv cb34 ) {
B13Snd b13snd( v1, cb13 );
BRcv b34rcv( cb34 );
void main(void) {b13snd.main();b34rcv.main();
}};
B13Snd b13snd( v1, cb13 );B13Snd b13snd( v1, cb13 );
in int v1in int v11
5
10
behavior B2B3( in int v1, ISend cb13,ISend c2,IRecv cb34)
{B2 b2 ( v1, c2 );B3stub b3stub( v1 , cb13, cb34
);
void main(void) {par {
b2.main(); b3stub.main();
}}
};
v1v1
1
5
10
15
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.23
Message-Passing Model (cont.)
B3
B13rcv
B34snd
PE2
v1
behavior PE2( IRecv cb13,IRecv c2,ISend cb34 )
{int v1;
B13Rcv b13rcv( cb13, v1 );
B3 b3 ( v1, c2 );BSnd b34snd( cb34 );
void main(void) {b13rcv.main();b3.main();b34snd.main();
}};
int v1;int v1;
B13Snd b13snd(v1, cb13 );B13Snd b13snd(v1, cb13 );
1
5
10
15
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.24
Message-Passing Model (cont.)
behavior Design() {ChMP cb13, c2, cb34;
PE1 pe1( cb13, c2, cb34 );PE2 pe2( cb13, c2, cb34 );
void main(void) {par { pe1.main(); pe2.main(); }
}};
B3
B13rcv
B34snd
B2
B1B1
B13snd
B34rcv
PE1
c2
v1
cb13
cb34
PE2
v1
1
5
10
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.25
Timed Computation
• Execution time of behaviors• Estimated target delay / timing budget
• Granularity• Behavior level / basic block level
Annotate behaviors• Simulation feedback• Synthesis constraints
behavior B2( in int v1, ISend c2 ) {
void main(void) { …waitfor( delay1 );
c2.send( … );…
}};
waitfor( B2_DELAY1 );waitfor( B2_DELAY1 );
waitfor( B2_DELAY2 );waitfor( B2_DELAY2 );
1
5
10
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.26
Scheduling
• Static scheduling• Fixed behavior
execution order• Flattened behavior
hierarchy
Serialize behavior execution on components
B2
B1B1
B13snd
B34rcv
PE1
• Dynamic scheduling• Pool of tasks• Scheduler, abstracted
OS
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.27
Model after Scheduling
B2
B1B1
B13snd
B34rcv
PE1
v1
• Statically scheduled PE1
behavior PE1( ISend cb13,ISend c2,IRecv cb34 )
{int v1;
B1 b1 ( v1 );B13Snd b13snd( v1, cb13 );B2 b2 ( v1, c2 );BRcv b34rcv( cb34 );
void main(void) {
b1.main();b13snd.main();b2.main();b34rcv.main();
}};
b1.main();b13snd.main();b2.main();b34rcv.main();
b1.main();b13snd.main();b2.main();b34rcv.main();
1
5
10
15
20
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.28
Model after Scheduling (cont.)
B3
B13rcv
B34snd
PE2
v1
behavior PE2( IRecv cb13,IRecv c2,ISend cb34 )
{int v1;
B13Rcv b13rcv( cb13, v1 );B3 b3 ( v1, c2 );BSnd b34snd( cb34 );
void main(void) {b13rcv.main();b3.main();b34snd.main();
}};
• No scheduling necessary for PE2
1
5
10
15
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.29
Model after Scheduling (cont.)
B3
B13rcv
B34snd
B2
B1B1
B13snd
B34rcv
PE1
c2
v1
cb13
cb34
PE2
v1
behavior Design(){
ChMP cb13, c2, cb34;
PE1 pe1( cb13, c2, cb34 );PE2 pe2( cb13, c2, cb34 );
void main(void) {par {
pe1.main(); pe2.main();
}}
};
1
5
10
CprE 588 – Embedded Computer SystemsFeb 10-12, 2009 Lect-05.30
Architecture Model
Specification model
Architecture model
Communication model
Implementation model
Backend
Architecture exploration
Communication synthesis
• Component structure/architecture• Top level of behavior hierarchy
• Behavioral/functional component view• Behaviors grouped under top-
level component behaviors• Sequential behavior execution
• Timed• Estimated execution delays