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Hardware Components 1 Lesson 3 0x003 011 Modified and presented by : Mohamed Zaki

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Page 1: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Hardware Components

1

Lesson 3 0x003

011

Modified and presented by : Mohamed Zaki

Page 2: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Topics

• Simple Computer Architecture• CPU Architecture• CPU Registers• Executing instruction• Instruction set types• Memory Devices• Bus Systems• Input / Output Architecture

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Page 3: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

COMPUTER ARCHITECTURE Von Neumann Architecture

CPU/Processor

Main Memory

Address Bus

Data Bus

Control Bus

Input & Output Devices

Page 4: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Examples of CPUs• Based on the manufacturer:

– Intel:• Celeron• Pentium I.• Pentium MMX. ( Multimedia Extension)• Pentium II.• Pentium III.• Pentium 4.• Centrino. ( Mobile Technology)• Core 2 DUO• Dual core• Quad core • Core i series (Laptop, Desktop, and Mobile Device Processors)• Xeon (Server and Workstation Processors)

– AMD.– ARM

• Dual Core A4,A5, A6• ARM Cortex-A9 MPCore (for iPad & iPhone and others) 4

Page 5: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

CPU Architecture• CPU:

– Is the part of a computer in which arithmetic and logical operations are performed and instructions are decoded then executed.

• CPU Components:• ALU ( Arithmetic and Logic Unit) • CU (Control Unit)• Registers:

– Are high speed & small in size temporary memory storage areas used during data manipulation ( calculation , comparison , etc..)

• The clock:• It is a circuit for generating pulses that enable

computer components to work in an ordered manner . 5

CPU : Central Processing Unit. Also called Processor

Page 6: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

CPU Architecture

101010100001001010010100010100100001

؟؟؟؟؟

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Control Unit

MAR

MBR

Program Counter Register

ALU

GENERAL PURPOS REGISTER

Main Memory / RAM / Primary Memory

CIR

Bus : set of wires

Page 7: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

CPU Registers• General purpose registers:

– are used to hold data before and after it is manipulated. Also used for many operation such addition, subtraction multiplication and logic operations

• Special Purpose Registers:– Program counter PC:

it is loaded with the address in memory of the first instruction location of a program. After fetching, it is increased to point to the next location.

– Memory Buffer register MBR: all data and instructions pass in and out from the main storage through MBR.

– Current instruction register CIR:an instruction to be performed will be taken from the main storage via the

MBR and placed in register IR.

– Memory address register MAR : prior to each transfer between the MBR and main storage , the exact source or

destination of data in the main storage must be specified by MAR. 7

Page 8: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Executing a Software Program

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Copy PC contents into MAR & Initiate a memory read

Increment the PC

Copy the instruction

Which is in the MBR into CIR

Decode the CIR

Execute the instruction

The chart shows the steps that the CPU uses to execute a software

Page 9: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Instruction set types

Arithmetic and Logic inst. Set:Such as addition, subtraction, multiplication, Increment, decrement, and logical

operations, Such as add, sub,mul.

I/O instructions:To transfer data between peripherals and memory, or between peripherals and

accumulator, Such as mov

Processor reference instructions:To stop the microprocessor activities. Such as halt.

Fetch (Load) and store instruction:To transfer the data between accumulator and memory, Such as load

Memory reference instructions:To access the memory during their execution, it is both Load + store instructions.

Transfer of control, or branch instruction: (Executing a Program)To change the program sequence. Such as jmp

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Each CPU has a set of instructions

Page 10: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Memory Devices• Any memory is constructed from a collection of memory

cells, each having unique address.• Each cell contains a combination of binary data(0 or 1).• Types of Memory:

– RAM.– ROM.– Cache Memory.

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Page 11: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Random Access Memory (RAM)

o It also called Main or Primary Memory.o Programs & Data are stored there before processing .o The larger amount of RAM, the quicker programs will

run.o More than one type of RAMs are used in modern PCs,

like DRAM(Dynamic RAM) and SDRAM(Synchronous DRAM)

o The data will be lost if the power is cut(Volatile Memory).

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Page 12: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Read Only Memory (ROM)

• It holds the firmware program (BIOS).

• It starts the POST “ power on self test” program

• It contains auto-startup program that will load the necessary OS programs in RAM.

• The information remains in the ROM when the computer turned off. ( Nonvolatile Memory)

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Page 13: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

The Differences between ROM and RAM:

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ROM (Read Only Memory) RAM (Random Access Memory)

1. Used to store part of O.S. by the factory.

2. ROM can be used for read only, we can't write or modify any thing on the ROM.

3. Not volatile memory (i.e. the information remains in the ROM when the computer turned off)

1. Used to store programs such as accounting program, games, word processor by the user.

2. We can use the RAM for read and write data.

3. Volatile memory (i.e. the information in the RAM is removed when the power turned off)

Page 14: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Cache Memory

• Is a small memory, located close to the processor?• Some processors are built with internal cache

memory.• It has much shorter access time than the RAM.

Therefore, it is used to hold instructions and data that has recently been accessed.

• There are two types of cache memory: L1 and L2.– L1 ( Level 1) internal cache, built in with in the CPU.– L2 ( Level 2) external cache, built in with in the

Motherboard, L2 is lager than L1. ( A+ Book p 131)

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Page 15: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

CPU, RAM, and Cache Diagram

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CPU

Cache

RAM

• Write through cache.• Write back cache.

Page 16: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Hard Disk

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Page 17: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Hard Disk is a data storage device used for storing and retrieving digital information using rapidly rotating discs (platters) coated with magnetic material.A magnetic heads arranged on a moving arm to read and write data to the surfaces.

Page 18: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Sector

Track

Magnetic polarity determines the bit value (1,0)

Bit Value is 1

Bit Value is 0

Disk Organization

0 0 1 0 1 1 1 0

The Format Command is used to create Tracks and Sectors

Page 19: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Other Storage Devices

Flash Memory DVD Disks Magnetic Tapes

Page 20: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Storage Device Hierarchy

Registers

Cache

Main Memory

Flash Memory

Hard Disks

Magnetic Tapes

Size

Bytes

M Bytes

G Bytes

G Bytes

G – T Bytes

T Bytes

Speed1 nsec

10 nsec

100 nsec

msec

msec

sec -min

Hard Disk and Tapes have mechanical movementsOthers do not have and called Solid Sate Devices (SSD)

Page 21: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Bus Systems (Connecting them together )

• Is a collection of parallel electrical lines which connect the computer components.

• The buses used to transfer:– Data signals.– Address signals.– Control signals.– Power.

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Page 22: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Bus Systems

– The address bus is the set of wires carrying the addressing information used to describe the memory location, which the data is being sent or retrieved.

– The size of the address bus indicates the maximum amount of RAM that a chip can address.

Size of memory that can be addressed= 2L

Were L = No. of Lines in address bus ( Size of address bus)

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Address Bus

Page 23: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Bus Systems

Size of address bus

Size of memory Size of address bus

Size of memory

1 21 16 216 ~= 64 KB2 22 =4 20 220 ~= 1 MB3 23=8 30 220=1 GB4 24 =16 32 232=4 GB : :

: :

10 210 =1024=1KB

11 211=210x21=2 KB12 212=210x22=4 KB

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Address Bus

Page 24: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Bus Systems

Examples:1) how many addresses can be built by 3 digits (3 lines): 2n = 23 = 8 address bus locations from

( 000 to 111 ) 2): how many addresses can be built by 3 digits (3 lines):

2n = 23 = 8 address bus locations from ( 000 to 111 )

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Address Bus

Page 25: CPU, Memory, and Bus systems · PPT file · Web view · 2013-10-08Topics. Simple Computer Architecture. CPU Architecture. CPU Registers. Executing instruction. Instruction set types

Input / Output Architecture• The computer has the ability to send and receive data to

and from other devices.• We can transfer data in parallel and serial lines.• When the CPU wishes to send data to a particular I/O

devices it places a unique identity code ( address ) onto the address line.

• Only the device that recognizes that code will respond to the command that is placed on the control line.

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