cs 150 - spring 2008 – lec #24: seq logic optimization - 1 sequential logic optimization zstate...

CS 150 - Spring 2008 – Lec #24: Seq Logic Optimization - 1

Sequential Logic Optimization

State Minimization Algorithms for State Minimization

State, Input, and Output Encodings Minimize the Next State and Output logic


Optimization in Context

Understand the word specification Draw a picture Derive a state diagram and Symbolic State Table Determine an implementation approach (e.g., gate logic,

ROM, FPGA, etc.) Perform STATE MINIMIZATION Perform STATE ASSIGNMENT Map Symbolic State Table to Encoded State Tables for

implementation (INPUT and OUTPUT encodings)


Finite State Machine Optimization

State Minimization Fewer states require fewer state bits Fewer bits require fewer logic equations

In general, one equation per output bit BUT What counts are literals, not numbers of equations

Encodings: State, Inputs, Outputs State encoding with fewer bits has fewer equations to implement

However, each may be more complex State encoding with more bits (e.g., one-hot) has simpler

equations Complexity directly related to complexity of state diagram

Input/output encoding may or may not be under designer control


Input Next State OutputSequence Present StateX=0 X=1 X=0 X=1

Reset S0 S1 S2 0 00 S1 S3 S4 0 01 S2 S5 S6 0 000 S3 S0 S0 0 001 S4 S0 S0 1 010 S5 S0 S0 0 011 S6 S0 S0 1 0

State Minimization Example

Sequence Detector for 010 or 110

S0

S3

S2S1

S5 S6S4

1/00/0

1/0

1/00/1

0/01/00/0

1/00/0

1/00/1

1/00/0

These two states must be identical – why?These two states must be identical – why?






S0

S3

S2S1

S5 S6S4

1/00/0

1/0

1/00/1

0/01/00/0

1/00/0

1/00/1

1/00/0

States S3, S5 are identical because can’t detect from here, next step is always S0

States S4, S6 are identical because they detect on 0, next step is always S0



Reset S0 S1 S2 0 00 S1 S3/5 S4/6 0 01 S2 S3/5 S4/6 0 000/11 S3/5 S0 S0 0 001/10 S4/6 S0 S0 1 0



S0

S3/5

S2S1

S4/6

1/00/0

1/00/0

1/00/0

1/00/11/00/0

These states are identical – why?



Reset S0 S1/2 S1/2 0 00/1 S1/2 S3/5 S4/6 0 000/11 S3/5 S0 S0 0 001/10 S4/6 S0 S0 1 0



S0

S3/5

S1/2

S4/6

0,1/0

1/00/0

1/00/11/00/0


Algorithmic Approach to State Minimization

Goal – identify and combine states that have equivalent behavior

Equivalent States: Same output For all input combinations, states transition to same or

equivalent states

Algorithm Sketch 1. Place all states in one set 2. Initially partition set based on output behavior 3. Successively partition resulting subsets based on next state

transitions 4. Repeat (3) until no further partitioning is required

states left in the same set are equivalent Polynomial time procedure (in size of state set)






S0

S3

S2S1

S5 S6S4

1/00/0

1/0

1/00/1

0/01/00/0

1/00/0

1/00/1

1/00/0


( S0 S1 S2 S3 S4 S5 S6 )

( S0 S1 S2 S3 S5 ) ( S4 S6 )

( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 )

( S0 ) ( S1 S2 ) ( S3 S5 ) ( S4 S6 )



S1 is equivalent to S2



Method of Successive Partitions


Input Next State OutputSequence Present State X=0 X=1 X=0 X=1

Reset S0 S1' S1' 0 00 + 1 S1' S3' S4' 0 0X0 S3' S0 S0 0 0X1 S4' S0 S0 1 0

Minimized FSM

State minimized sequence detector for 010 or 110

S0

S1’

S3’ S4’

X/0

1/0

1/00/1

0/0

X/0

7 States reduced to 4 States3 bit encoding replaced by 2 bit encoding


Another Example

4-Bit Sequence Detector: output 1 after each 4-bit input sequence consisting of the binary strings 0110 or 1010


State Transition Table Group states with same next state and same outputs

S’10


Iterate the Row Matching Algorithm

S’7


Iterate One Last Time

S’3 S’4


Final Reduced State Machine

15 states (min 4 FFs) reduced to 7 states (min 3 FFs)


symbolic state transition table

present next state output state 00 01 10 11 S0 S0 S1 S2 S3 1 S1 S0 S3 S1 S4 0 S2 S1 S3 S2 S4 1 S3 S1 S0 S4 S5 0 S4 S0 S1 S2 S5 1 S5 S1 S4 S0 S5 0

inputs here

More Complex State Minimization

Multiple input example

1001

11

00

00

01

1110

10

01

1100

1000

11

00

1110

01

10

1101

00

S0[1]

S2[1]

S4[1]

S1[0]

S3[0]

S5[0]

01


S0-S1 S1-S3 S2-S2 S3-S4

S0-S0 S1-S1 S2-S2 S3-S5

S0-S1 S3-S0 S1-S4 S4-S5

S0-S1 S3-S4 S1-S0 S4-S5

S1-S0 S3-S1 S2-S2S4-S5

S4-S0S5-S5

S1-S1 S0-S4

minimized state table(S0==S4) (S3==S5)

present next state output state 00 01 10 11 S0' S0' S1 S2 S3' 1 S1 S0' S3' S1 S3' 0 S2 S1 S3' S2 S0' 1 S3' S1 S0' S0' S3' 0

Minimized FSM Implication Chart Method

Cross out incompatible states based on outputs Then cross out more cells if indexed chart entries are

already crossed out

S1

S2

S3

S4

S5

S0 S1 S2 S3 S4

present next state output state 00 01 10 11 S0 S0 S1 S2 S3 1 S1 S0 S3 S1 S4 0 S2 S1 S3 S2 S4 1 S3 S1 S0 S4 S5 0 S4 S0 S1 S2 S5 1 S5 S1 S4 S0 S5 0


“Polynomial” Algorithm

n (n+1)/2 squares for n states At each iteration, must cross off at least one square,

or done ≤ n(n+1)/2 iterations at most

Filling out a square takes O(num input combinations) Total Running time is O(n2 * num input

combinations) “Polynomial”?...well

Representation of finite state machine is often log number of states x log number of input combinations

Consider a counter

Algorithm is exponential in this representation


Minimizing Incompletely Specified FSMs

Equivalence of states is transitive when machine is fully specified

But its not transitive when don't cares are presente.g., state output

S0 – 0 S1 is compatible with both S0 and S2S1 1 – but S0 and S2 are incompatibleS2 – 1 disagree in output 2

No polynomial time algorithm exists for determining best grouping of states into equivalent sets that will yield the smallest number of final states


X Q1 Q0 Q1+ Q0

+

0 0 0 0 00 0 1 0 00 1 1 0 01 0 0 0 11 0 1 1 11 1 1 1 1– 1 0 0 0

Q1+ = X (Q1 xor Q0)

Q0+ = X Q1’ Q0’

Minimizing States May Not Yield Best Circuit

Example: edge detector - outputs 1 when last two input changes from 0 to 1

00[0]

11[0]

01[1]X’

X’

X’

X

X

X


X Q1 Q0 Q1+ Q0

+

0 0 0 0 00 0 1 0 00 1 1 0 01 0 0 0 11 0 1 1 11 1 1 1 1– 1 0 0 0

Q1+ = X (Q1 xor Q0)

Q0+ = X Q1’ Q0’

Edge Detector Implementation

00[0]

11[0]

01[1]X’

X’

X’

X

X

X

X

Q1

Q0


Another Implementation of Edge Detector

"Ad hoc" solution - not minimal but cheap and fast

00[0]

10[0]

01[1]

X’ X

X’

X

X

X11[0]

X’

X’


State Assignment

Choose bit vectors to assign to each “symbolic” state With n state bits for m states there are 2n! / (2n – m)!

[log n <= m <= 2n] 2n codes possible for 1st state, 2n–1 for 2nd, 2n–2 for 3rd,

… Huge number even for small values of n and m

Intractable for state machines of any size Heuristics are necessary for practical solutions

Optimize some metric for the combinational logic Size (amount of logic and number of FFs) Speed (depth of logic and fanout) Dependencies (decomposition)


Key Idea Behind State Assignment

Goal is to minimize the logic realizing a state machine But we can’t generate logic and optimize (takes too long) Need to get a good proxy for logic complexity

Key insight: If state bits don’t change, don’t need logic How many bit changes in one-hot?

One-hot encoding One AND gate per incoming edge to state One OR gate per state Logic is cheap, but far too many bits (one per state!)

Therefore: minimize bit changes subject to number-of-state-bits constraint


Note minimize-changes heuristic doesn’t always work!

Consider a counter

Can get n bit changes (consider counting from -1 to 0) Logic is very small

But is generally a good proxy Key: minimizing number of bit changes (usually)

minimizes Karnaugh maps


State Assignment Strategies

Possible Strategies Sequential – just number states as they appear in the state

table Random – pick random codes One-hot – use as many state bits as there are states (bit=1 –

> state) Output – use outputs to help encode states Heuristic – rules of thumb that seem to work in most cases

No guarantee of optimality – another intractable problem


One-hot State Assignment Simple

Easy to encode, debug

Small Logic Functions Each state function requires only predecessor state bits as input

Good for Programmable Devices Lots of flip-flops readily available Simple functions with small support (signals its dependent upon)

Impractical for Large Machines Too many states require too many flip-flops Decompose FSMs into smaller pieces that can be one-hot encoded

Many Slight Variations to One-hot One-hot + all-0


State Maps and Counting Bit Changes

Bit Change Heuristic

S0

S1 S2

S3

S4

0 1

S0 -> S1: 2 1S0 -> S2: 3 1S1 -> S3: 3 1S2 -> S3: 2 1S3 -> S4: 1 1S4 -> S1: 2 2Total: 13 7


Equations for Each AssignmentS0

S1 S2

S3

S4

0 1State Equations:• S1

+ = S0 X’ + S4

• S2+ = S0 X,

•S3 +

=S1 + S2,

•S4+ = S3

Q2 = S1 + S2

•Q1 = S4 + S2 + S3

•Q0 = S4 + S2 + S1

Assignment One:S0 000

S1 101

S2 111

S3 010

S4 011

Q2 = S0 X’ + S4 + S0 X

•Q1 = S3 + S2 + S1 + S0 X

•Q0 = S3 + S0 X’ + S4 + S0 X

Q2 = Q2’Q1’Q0’ + Q2’Q1Q0

•Q1 = Q2’Q1Q0’ + Q2Q1Q0 + Q2Q1’Q0 + Q2’Q1’Q0’ X

•Q0 = Q2’Q1Q0’ + Q2’Q1’Q0’ + Q2’Q1Q0


Karnaugh Maps

1

1 1

1 1

1 1

00 01 11 10

00

01

11

10

Q1Q0

XQ2

Q1 1 1 1

00 01 11 10

0

1

Q1Q0

Q2

Q01 1

00 01 11 10

0

1

Q1Q0

Q2

Q2

Q2 = Q2’Q1’Q0’ + Q2’Q1Q0

•Q1 = Q2’Q1Q0’ + Q2Q1Q0 + Q2Q1’Q0 + Q2’Q1’Q0’ X

•Q0 = Q2’Q1Q0’ + Q2’Q1’Q0’ + Q2’Q1Q0


Equations for Each AssignmentS0

S1 S2

S3

S4

0 1State Equations:• S1

+ = S0 X’ + S4

• S2+ = S0 X,

•S3 +

=S1 + S2,

•S4+ = S3

Q2 = S4

•Q1 = S4 + S2 + S3

•Q0 = S4 + S3 + S1

Assignment Two:S0 000

S1 001

S2 010

S3 011

S4 111

Q2 = S3

Q1 = S3 + S2 + S1 + S0 X

•Q0 = S3 + S2 + S1 + S4 + S0 X

Q2 = Q2’Q1Q0

•Q1 = Q2’Q1Q0 + Q2‘Q1Q0’ + Q2’Q1’Q0 + Q2’Q1’Q0’ X

•Q0 = Q2’Q1Q0 + Q2’Q1Q0’ + Q2’Q1’Q0 + Q2Q1Q0+ Q2’Q1’Q0’ X


Karnaugh Maps

1 1 1

1 1 1 1

00 01 11 10

00

01

11

10

Q1Q0

XQ2

Q1

1

00 01 11 10

0

1

Q1Q0

Q2

Q2

Q2 = Q2’Q1Q0

•Q1 = Q2’Q1Q0 + Q2‘Q1Q0’ + Q2’Q1’Q0 + Q2’Q1’Q0’ X

•Q0 = Q2’Q1Q0 + Q2’Q1Q0’ + Q2’Q1’Q0 + Q2Q1Q0+ Q2’Q1’Q0’ X

1 1 1

1

1

1 1 1 1

00 01 11 10

00

01

11

10

Q1Q0

XQ2

Q0


I Q Q+ Oi a c ji b c k

I Q Q+ Oi a b jk a c l

I Q Q+ Oi a b ji c d j

c = i * a + i * b

b = i * ac = k * a

j = i * a + i * cb = i * ad = i * c

i / j i / k

a b

c

a

b c

i / j k / l

b d

i / ja c

i / j

Adjacency Heuristics for State Assignment

Adjacent codes to states that share a common next state Group 1's in next state map

Adjacent codes to states that share a common ancestor state Group 1's in next state map

Adjacent codes to states that have a common output behavior Group 1's in output map


Heuristics for State Assignment

Successor/Predecessor Heuristics

High Priority: S’3 and S’4 share common successor state (S0)

Medium Priority: S’3 and S’4 share common predecessor state (S’1)

Low Priority: 0/0: S0, S’1, S’3

1/0: S0, S’1, S’3, S’4


Heuristics for State Assignment


Another Example

High Priority: S’3, S’4

S’7, S’10

Medium Priority: S1, S2

2 x S’3, S’4

S’7, S’10

Low Priority: 0/0: S0, S1, S2, S’3, S’4, S’7

1/0: S0, S1, S2, S’3, S’4, S’7, S10


Example Continued

Choose assignment for S0 = 000

Place the high priority adjacency state pairs into the State Map

Repeat for the medium adjacency pairs

Repeat for any left over states, using the low priority scheme

Two alternativeassignments at the left


Why Do These Heuristics Work?

Attempt to maximize adjacent groupings of 1’s in the next state and output functions


General Approach to Heuristic State Assignment All current methods are variants of this

1) Determine which states “attract” each other (weighted pairs) 2) Generate constraints on codes (which should be in same cube) 3) Place codes on Boolean cube so as to maximize constraints

satisfied (weighted sum)

Different weights make sense depending on whether we are optimizing for two-level or multi-level forms

Can't consider all possible embeddings of state clusters in Boolean cube Heuristics for ordering embedding To prune search for best embedding Expand cube (more state bits) to satisfy more constraints


Output-Based Encoding Reuse outputs as state bits - use outputs to help

distinguish states Why create new functions for state bits when output can

serve as well Fits in nicely with synchronous Mealy implementations

HG = ST’ H1’ H0’ F1 F0’ + ST H1 H0’ F1’ F0HY = ST H1’ H0’ F1 F0’ + ST’ H1’ H0 F1 F0’ FG = ST H1’ H0 F1 F0’ + ST’ H1 H0’ F1’ F0’ HY = ST H1 H0’ F1’ F0’ + ST’ H1 H0’ F1’ F0

Output patterns are unique to states, we do notneed ANY state bits – implement 5 functions(one for each output) instead of 7 (outputs plus2 state bits)

Inputs Present State Next State OutputsC TL TS ST H F0 – – HG HG 0 00 10 – 0 – HG HG 0 00 10 1 1 – HG HY 1 00 10 – – 0 HY HY 0 01 10 – – 1 HY FG 1 01 101 0 – FG FG 0 10 000 – – FG FY 1 10 00– 1 – FG FY 1 10 00– – 0 FY FY 0 10 01– – 1 FY HG 1 10 01


Current State Assignment Approaches

For tight encodings using close to the minimum number of state bits Best of 10 random seems to be adequate (averages as well as

heuristics) Heuristic approaches are not even close to optimality Used in custom chip design

One-hot encoding Easy for small state machines Generates small equations with easy to estimate complexity Common in FPGAs and other programmable logic

Output-based encoding Ad hoc - no tools Most common approach taken by human designers Yields very small circuits for most FSMs


Sequential Logic Implementation Summary Implementation of sequential logic

State minimization State assignment

Implications for programmable logic devices When logic is expensive and FFs are scarce, optimization

is highly desirable (e.g., gate logic, PLAs, etc.) In Xilinx devices, logic is bountiful (4 and 5 variable TTs)

and FFs are many (2 per CLB), so optimization is not so crucial an issue as in other forms of programmable logic

This makes sparse encodings like One-Hot worth considering

cs 150 - spring 2008 – lec #24: seq logic optimization - 1 sequential logic optimization zstate...

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