cs 152 computer architecture and engineering lecture 9 multiprogramming and exceptions february 25,...

CS 152 Computer Architecture and Engineering

Lecture 9

Multiprogrammingand

Exceptions

February 25, 2004

John Kubiatowicz (www.cs.berkeley.edu/~kubitron)

lecture slides: http://inst.eecs.berkeley.edu/~cs152/

2/25/04 ©UCB Spring 2004 CS152 / Kubiatowicz

Lec9.2

The Big Picture: Where are We Now?

° The Five Classic Components of a Computer

° Today’s Topics: • Microprogramed control

• Administrivia; Courses

• Microprogram it yourself

• Exceptions

• Intro to Pipelining (if time permits)

Control

Datapath

Memory

Processor

Input

Output


Lec9.3

Review: Multicycle Datapath

° Critical Path ?

PC

Nex

t P

C

Ope

rand

Fet

ch

Inst

ruct

ion

Fet

ch

nPC

_sel

IRRegFile E

xtA

LU Reg

. F

ile

Mem

Acc

ess

Dat

aM

em

Res

ult

Sto

reR

egD

stR

egW

r

Mem

Wr

Mem

Rd

S

M

Mem

ToR

eg

Equ

al

ALU

ctr

ALU

Src

Ext

Op

A

B

E


Lec9.4

Review: Control Specification as State Machine

IR <= MEM[PC]

R-type

A <= R[rs]B <= R[rt]

S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4

BEQPC <= Next(PC,Equal)

SW

“instruction fetch”

“decode / operand fetch”

Exe

cute

Mem

ory

Writ

e-ba

ck


Lec9.5

Review: Performance Evaluation

° What is the average CPI?• state diagram gives CPI for each instruction type

• workload gives frequency of each type

Type CPIi for type Frequency CPIi x freqIi

Arith/Logic 4 40% 1.6

Load 5 30% 1.5

Store 4 10% 0.4

branch 3 20% 0.6

Average CPI:4.1


Lec9.6

Review: Micro-Controller Design

° The state digrams that arise define the controller for an instruction set processor are highly structured

° Use this structure to construct a simple “microsequencer”

° Control reduces to programming this very simple device

microprogrammingsequencercontrol

datapath control

micro-PCsequencer

microinstruction


Lec9.7

Example: Jump-Counter

op-codeMap ROM

Counterzeroincload

0000i

i+1

i

None of above: Do nothing (for wait states)

“Zero” “Increment” “Load”


Lec9.8

Using a Jump Counter

IR <= MEM[PC]

R-type

A <= R[rs]B <= R[rt]

S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4

BEQ

PC <= Next(PC)

SW


“decode”

0000

0001

0100

0101

0110

0111

1000

1001

1010

00111011

1100

inc

load

zero zerozero

zero

zeroinc inc inc inc

inc

Exe

cute

Mem

ory

Writ

e-ba

ck


Lec9.9

Our Microsequencer

op-code

Map ROM

Micro-PC

Z I Ldatapath control

Equal


Lec9.10

Microprogram Control Specification: Logic? ROM?

0000 x inc 10001 x load 1 10011 0 zero 1 00011 1 zero 1 10100 x inc 0 1 fun 10101 x zero 1 0 0 1 10110 x inc 0 0 or 10111 x zero 1 0 0 1 01000 x inc 1 0 add 11001 x inc 1 0 11010 x zero 1 0 1 1 01011 x inc 1 0 add 11100 x zero 1 0 0 1 0

µPC Equal Next IR PC Ops Exec Mem Write-Backen sel A B Ex Sr ALU S R W M M-R Wr Dst

R:

ORi:

LW:

SW:

BEQ:

Inputs Outputs


Lec9.11

Alternative multicycle datapath (book)

° Miminizes Hardware: 1 memory, 1 adder

IdealMemoryWrAdrDin

RAdr

32

32

32Dout

MemWr

32

AL

U

3232

ALUOp

ALUControl

32

IRWr

Instru

ction R

eg

32

Reg File

Ra

Rw

busW

Rb5

5

32busA

32busB

RegWr

Rs

Rt

Mu

x

0

1

Rt

Rd

PCWr

ALUSelA

Mux 01

RegDst

Mu

x

0

1

32

PC

MemtoReg

Extend

ExtOp

Mu

x

0

132

0

1

23

4

16Imm 32

<< 2

ALUSelB

Mu

x1

0

32

Equal

ZeroPCWrCond PCSrc

32

IorD

Mem

Data R

eg

AL

U O

ut

B

A


Lec9.12

New Finite State Machine (FSM) Spec

IR <= MEM[PC]PC <= PC + 4

R-type

ALUout <= A fun B

R[rd] <= ALUout

ALUout <= A or ZX

R[rt] <= ALUout

ORi

ALUout <= A + SX

R[rt] <= M

M <= MEM[ALUout]

LW

ALUout <= A + SX

MEM[ALUout] <= B

SW


“decode”

Exe

cute

Mem

ory

Writ

e-ba

ck

0000

0001

0100

0101

0110

0111

1000

1001

1010

1011

1100

BEQ

0010

0011

If A = B then PC <= ALUout

ALUout <= PC +SX

Q: How improveto do something instate 0001?


Lec9.13

Finite State Machine (FSM) Spec


R-type

ALUout <= A fun B

R[rd] <= ALUout

ALUout <= A or ZX

R[rt] <= ALUout

ORi

ALUout <= A + SX

R[rt] <= M

M <= MEM[ALUout]

LW

ALUout <= A + SX

MEM[ALUout] <= B

SW


“decode”

0000

0001

0100

0101

0110

0111

1000

1001

1010

1011

1100

BEQ

0010


ALUout <= PC +SX

Exe

cute

Mem

ory

Writ

e-ba

ck


Lec9.14

sequencercontrol

micro-PC-sequencer:fetch,dispatch,sequential

DispatchROM

Opcode

Inputs

Microprogramming

° Microprogramming is a fundamental concept• implement an instruction set by building a very simple processor

and interpreting the instructions

• essential for very complex instructions and when few register transfers are possible

• overkill when ISA matches datapath 1-1

-Code ROM

To DataPath

DecodeDecode

datapath control

microinstruction ()


Lec9.15

Microprogramming° Microprogramming is a convenient method for implementing structured control state diagrams:

• Random logic replaced by microPC sequencer and ROM

• Each line of ROM called a instruction: contains sequencer control + values for control points

• limited state transitions: branch to zero, next sequential,branch to instruction address from displatch ROM

° Horizontal Code: one control bit in Instruction for every control line in datapath

° Vertical Code: groups of control-lines coded together in Instruction (e.g. possible ALU dest)

° Control design reduces to Microprogramming• Part of the design process is to develop a “language” that

describes control and is easy for humans to understand


Lec9.16

“Macroinstruction” Interpretation

MainMemory

executionunit

controlmemory

CPU

ADDSUBAND

DATA

.

.

.

User program plus Data

this can change!

AND microsequence

e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s)

one of these ismapped into oneof these


Lec9.17

Administrivia° Lab 3 design document to go over in section• EMail preliminary design document to TA by 9pm tonight• Email final version to TA by midnight Thursday• Sections back in normal rooms• This is a complicated lab – may need to give updates as we get

the boards installed° Change to Lab specification

• Your ChipScope should be set up to trigger on a PC entered from board switches (8-switches 10-bit PC)

° Homework quiz still next Wednesday• Homework is shorter this time • Make sure to check on assigned problems

° Midterm I, Wednesday March 10th (Two Weeks)• 5:30 - 8:30 in 306 Soda Hall • Bring a Calculator!• One 8 1/2 by 11 page (both sides) of notes• Make up exam?


Lec9.18

Review: Testing: Make sure that things work° Testing methodologies

• Understand what correct behavior iswhen you design things

- Collect vectors for later use

• Build monitor modules to check assertions of correct values

• Produce a regression test

- Set of tests to run each time something changes

° Types of test (Doug Clark):• Directed Vectors – test explicit behavior

• Random Vectors – apply random values or orderings to device

• Daemons – continuous error insertion

° Monitor modules:• Check to see if invariants are maintained

during long running simulations

Alewife Numbers


Lec9.19

module monitorsum32(carry,sum,A,B );input [31:0] A,B;output [31:0] sum;output carry;reg [31:0] predsum;reg precarry;

// The “real” addersum32 mysum (carry,sum,A,B);

`ifndef synthesis // This checker code only for simulationalways @(A or B)

begin #100 //wait for output to settle (don’t make too long!){predcarry,predsum} = A + B;

if ((carry != predcarry) || (sum != predsum))$display(“>>> Mismatch: 0x%x+0x%x->0x%x carry %x”,

A,B,sum,carry);end

`endifendmodule

Review: Monitor Modules: Passthrough testing


Lec9.20

Lab3 version: monitors and benches° Important design idea:

• Set up your processor so that you can take the same design and both simulate and push it to board

° Testing Ideas:• wrap testing infrastructure around devices under test (DUT)• Include test vectors that are supposed to detect errors in

implementation. Even strange ones…• Can (and probably should in later labs) include assert statements to

check for “things that should never happen”

Test Bench

Device UnderTest

Inline vectorsAssert StatementsFile IO (either for patternsor output diagnostics)

Inline Monitor

Output in readableformat (disassembly)Assert Statements

Complete Top-Level Design


Lec9.21

Designing a Microinstruction Set

1) Start with list of control signals

2) Group signals together that make sense (vs. random): called “fields”

3) Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last)

4) To minimize the width, encode operations that will never be used at the same time

5) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals

• Use computers to design computers


Lec9.22

Recap: Multicycle datapath (book)

IdealMemoryWrAdrDin

RAdr

32

32

32Dout

MemWr

32

AL

U

3232

ALUOp

ALUControl

32

IRWr

Instru

ction R

eg

32

Reg File

Ra

Rw

busW

Rb5

5

32busA

32busB

RegWr

Rs

Rt

Mu

x

0

1

Rt

Rd

PCWr

ALUSelA

Mux 01

RegDst

Mu

x

0

1

32

PC

MemtoReg

Extend

ExtOp

Mu

x

0

132

0

1

23

4

16Imm 32

<< 2

ALUSelB

Mu

x1

0

32

Equal

ZeroPCWrCond PCSrc

32

IorD

Mem

Data R

eg

AL

U O

ut

B

A

MemRd


Lec9.23

Step 1 Start with List of control signals

Signal name Effect when deasserted Effect when assertedALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs]RegWrite None Reg. is written MemtoReg Reg. write data input = ALU Reg. write data input = memory RegDst Reg. dest. no. = rt Reg. dest. no. = rdMemRead None Memory at address is read,

MDR <= Mem[addr]MemWrite None Memory at address is written IorD Memory address = PC Memory address = SIRWrite None IR <= MemoryPCWrite None PC <= PCSourcePCWriteCond None IF ALUzero then PC <= PCSourcePCSource PCSource = ALU PCSource = ALUoutExtOp Zero Extended Sign Extended

Sin

gle

Bit

Con

trol

Signal name Value Effect ALUOp 00 ALU adds 01 ALU subtracts 10 ALU does function code

11 ALU does logical OR ALUSelB 00 2nd ALU input = 4 01 2nd ALU input = Reg[rt] 10 2nd ALU input = extended,shift left 2 11 2nd ALU input = extended

Mu

ltip

le B

it C

ontr

ol


Lec9.24

Step 2Group together related signals

IdealMemoryWrAdrDin

RAdr

32

32

32Dout

MemWr

32

AL

U

3232

ALUOp

ALUControl

32

IRWr

Instru

ction R

eg

32

Reg File

Ra

Rw

busW

Rb5

5

32busA

32busB

RegWr

Rs

Rt

Mu

x

0

1

Rt

Rd

PCWr

ALUSelA

Mux 01

RegDst

Mu

x

0

1

32

PC

MemtoReg

Extend

ExtOp

Mu

x

0

132

0

1

23

4

16Imm 32

<< 2

ALUSelB

Mu

x1

0

32

Equal

ZeroPCWrCond PCSrc

32

IorD

Mem

Data R

eg

AL

U O

ut

B

A

MemRd

ALU

SRC1

SRC2

DestinationMemory

PCWrite


Lec9.25

3&4) Microinstruction Format: unencoded vs. encoded fields

Field Name Width Control Signals Set

wide narrow

ALU Control 4 2 ALUOp

SRC1 2 1 ALUSelA

SRC2 5 3 ALUSelB, ExtOp

ALU Destination 3 2 RegWrite, MemtoReg, RegDst

Memory 3 2 MemRead, MemWrite, IorD

Memory Register 1 1 IRWrite

PCWrite Control 3 2 PCWrite, PCWriteCond, PCSource

Sequencing 3 2 AddrCtl

Total width 24 15 bits


Lec9.26

Step 5Group into Fields, Order and Assign Names

Field Name Values for Field Function of Field with Specific ValueALU Add ALU adds

Subt. ALU subtractsFunc ALU does function codeOr ALU does logical OR

SRC1 PC 1st ALU input <= PCrs 1st ALU input <= Reg[rs]

SRC2 4 2nd ALU input <= 4Extend 2nd ALU input <= sign ext. IR[15-0]Extend0 2nd ALU input <= zero ext. IR[15-0] Extshft 2nd ALU input <= sign ex., sl IR[15-0]rt 2nd ALU input <= Reg[rt]

dest(ination) rd ALU Reg[rd] <= ALUout rt ALU Reg[rt] <= ALUout

rt Mem Reg[rt] <= Mem Mem(ory) Read PC Read memory using PC

Read ALU Read memory using ALUout for addrWrite ALU Write memory using ALUout for addr

Memreg IR IR <= MemPCwrite PCwr PC <= PCSource

PCSrc IF Zero then PCSource <= ALUout else ALUPCWrCond IF Zero then PC <= PCSource

Seq(uencing) Seq Go to next sequential µinstructionFetch Go to the first microinstructionDispatch Dispatch using ROM.

ALU SRC1

SRC2

Dest Mem Memreg PCwrite Seq


Lec9.27

Quick check: what do these fieldnames mean?

Code Name RegWrite MemToRegRegDest

00 --- 0 X X01 rd ALU 1 0 110 rt ALU 1 0 011 rt MEM 1 1 0

Code Name ALUSelB ExtOp000 --- X X001 4 00 X010 rt 01 X011 ExtShft 10 1100 Extend 11 1111 Extend0 11 0

Destination:

SRC2:


Lec9.28

Specific Sequencer for our Microcoding

Sequencer-based control unit from last lecture• Called “microPC” or “µPC” vs. state register

Code Name Effect 00 fetch Next µaddress = 0 01 dispatch Next µaddress = dispatch ROM 10 seq Next µaddress = µaddress + 1

ROM:

Opcode

microPC

1

µAddressSelectLogic

Adder

ROM

Mux

0012

Opcode: Dispatch state000000: Rtype (0100) 000100: BEQ (0010) 001101: ORI (0110) 100011: LW (1000) 101011: SW (1011)


Lec9.29

Recap: Finite State Machine (FSM) Spec


R-type

ALUout <= A fun B

R[rd] <= ALUout

ALUout <= A or ZX

R[rt] <= ALUout

ORi

ALUout <= A + SX

R[rt] <= M

M <= MEM[ALUout]

LW

ALUout <= A + SX

MEM[ALUout] <= B

SW


“decode”

0000

0001

0100

0101

0110

0111

1000

1001

1010

1011

1100

BEQ

0010


ALUout <= PC +SX

Exe

cute

Mem

ory

Writ

e-ba

ck


Lec9.30

Microprogram it yourself!Addr ALU SRC1 SRC2 Dest. Memory Mem. Reg. PC Write Sequencing

Fetch:0000: Add PC 4 Read PC IR ALU Seq

Decode:0001: Add PC Extshft Dispatch

BEQ:0010: Subt. rs rt ALUoutCond. Fetch

Rtype:0100: Func rs rt Seq0101: rd ALU Fetch

ORI:0110: Or rs Extend0 Seq0111: rt ALU Fetch

LW:1000: Add rs Extend Seq1001: Read ALU Seq1010: rt MEM Fetch

SW:1011: Add rs Extend Seq1100: Write ALU Fetch


Lec9.31

Overview of Control

° Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique.

Initial Representation Finite State Diagram Microprogram

Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs

Logic Representation Logic Equations Truth Tables

Implementation PLA ROM Technique

“hardwired control” “microprogrammed control”


Lec9.32

Exceptions

° Exception = unprogrammed control transfer• system takes action to handle the exception

- must record the address of the offending instruction- record any other information necessary to return afterwards

• returns control to user• must save & restore user state

° Allows constuction of a “user virtual machine”

normal control flow: sequential, jumps, branches, calls, returns

user program SystemExceptionHandlerException:

return fromexception


Lec9.33

Two Types of Exceptions: Interrupts and Traps° Interrupts

• caused by external events:

- Network, Keyboard, Disk I/O, Timer

• asynchronous to program execution

- Most interrupts can be disabled for brief periods of time

- Some (like “Power Failing”) are non-maskable (NMI)

• may be handled between instructions

• simply suspend and resume user program

° Traps• caused by internal events

- exceptional conditions (overflow)

- errors (parity)

- faults (non-resident page)

• synchronous to program execution

• condition must be remedied by the handler

• instruction may be retried or simulated and program continued or program may be aborted


Lec9.34

Precise Exceptions° Precise state of the machine is preserved as if

program executed up to the offending instruction• All previous instructions completed

• Offending instruction and all following instructions act as if they have not even started

• Same system code will work on different implementations

• Position clearly established by IBM

• Difficult in the presence of pipelining, out-ot-order execution, ...

• MIPS takes this position

° Imprecise system software has to figure out what is where and put it all back together

° Performance goals often lead designers to forsake precise interrupts

• system software developers, user, markets etc. usually wish they had not done this

° Modern techniques for out-of-order execution and branch prediction help implement precise interrupts


Lec9.35

Summary° Microprogramming is a fundamental concept

• implement an instruction set by building a very simple processor and interpreting the instructions

• essential for very complex instructions and when few register transfers are possible

• Control design reduces to Microprogramming

° Design of a Microprogramming language1. Start with list of control signals2. Group signals together that make sense (vs. random): called “fields”3. Place fields in some logical order (e.g., ALU operation & ALU operands

first and microinstruction sequencing last)4. To minimize the width, encode operations that will never be used at the

same time5. Create a symbolic legend for the microinstruction format, showing

name of field values and how they set the control signals

° Sophisticated microcontrollers lead to complete micro-machine language! • Branches, jumps, etc• Old MIT course: many levels: Machine language, Microcode, nanocode

cs 152 computer architecture and engineering lecture 9 multiprogramming and exceptions february 25,...

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