CS61C:GreatIdeasinComputerArchitectureSequentialElements,Synchronous

DigitalSystems

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Instructors:VladimirStojanovic&NicholasWeaver

http://inst.eecs.Berkeley.edu/~cs61c/sp16

LevelsofRepresentation/Interpretation

lw $t0,0($2)lw $t1,4($2)sw $t1,0($2)sw $t0,4($2)

HighLevelLanguageProgram(e.g.,C)

AssemblyLanguageProgram(e.g.,MIPS)

MachineLanguageProgram(MIPS)

HardwareArchitectureDescription(e.g.,blockdiagrams)

Compiler

Assembler

MachineInterpretation

temp=v[k];v[k]=v[k+1];v[k+1]=temp;

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

LogicCircuitDescription(CircuitSchematicDiagrams)

ArchitectureImplementation

Anythingcanberepresentedasanumber,

i.e.,dataorinstructions

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BooleanAlgebra:Circuit&AlgebraicSimplification

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LawsofBooleanAlgebra

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XX=0X0=0X1=XXX=XXY=YX

(XY)Z=Z(YZ)X(Y+Z)=XY+XZ

XY+X=XXY+X=X+YXY=X+Y

X+X=1X+1=1X+0=XX+X=X

X+Y=Y+X(X+Y)+Z=Z+(Y+Z)X+YZ=(X+Y)(X+Z)

(X+Y)X=X(X+Y)X=XYX+Y=XY

ComplementarityLawsof0’sand1’s

IdentitiesIdempotentLawsCommutativityAssociativityDistribution

UnitingTheoremUnitingTheoremv.2DeMorgan’s Law

BooleanAlgebraicSimplificationExample

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BooleanAlgebraicSimplificationExample

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ab c y00000011010001111001101111011111

SignalsandWaveforms:Grouping

SignalsandWaveforms:CircuitDelay

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3 4 5

10 0 1

5 13 4 6

SampleDebuggingWaveform

Clickers/PeerInstruction

• SimplifyZ=A+BC+A(BC)

• A: Z=0• B: Z=A(1+BC)• C:Z=(A+BC)• D:Z=BC• E:Z=1

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TypeofCircuits• SynchronousDigitalSystemsconsistoftwobasictypesofcircuits:• CombinationalLogic(CL)circuits

–Outputisafunctionoftheinputsonly,notthehistoryofitsexecution– E.g.,circuitstoaddA,B(ALUs)

• SequentialLogic(SL)• Circuitsthat“remember”orstoreinformation• aka“StateElements”• E.g.,memoriesandregisters(Registers)

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UsesforStateElements

• Placetostorevaluesforlaterre-use:– Registerfiles(like$1-$31inMIPS)– Memory(cachesandmainmemory)

• Helpcontrolflowofinformationbetweencombinational logicblocks– Stateelementsholdupthemovementofinformationatinputtocombinationallogicblockstoallowfororderlypassage

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AccumulatorExample

Want: S=0; for (i=0;i<n;i++)

S = S + Xi

Whydoweneedtocontroltheflowofinformation?

Assume:• EachXvalueisappliedinsuccession,onepercycle• AfterncyclesthesumispresentonS

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SUMXi S

FirstTry:Doesthiswork?

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No!Reason#1:Howtocontrolthenextiterationofthe‘for’loop?Reason#2:Howdowesay:‘S=0’?

Feedback

RegisterInternals

• n instancesofa“Flip-Flop”

• Flip-flopnamebecausetheoutputflipsandflopsbetween0and1

• Dis“datainput”,Qis“dataoutput”

• Alsocalled“D-typeFlip-Flop”15

Flip-FlopOperation• Edge-triggeredd-typeflip-flop– Thisoneis“positiveedge-triggered”

• “Ontherisingedgeoftheclock,theinputdissampledandtransferredtotheoutput.Atallothertimes,theinputdisignored.”

• Examplewaveforms:

Flip-FlopTiming• Edge-triggeredd-typeflip-flop– Thisoneis“positiveedge-triggered”

• “Ontherisingedgeoftheclock,theinputdissampledandtransferredtotheoutput.Atallothertimes,theinputdisignored.”

• Examplewaveforms(moredetail):

CameraAnalogyTimingTerms

• Wanttotakeaportrait– timingrightbeforeandaftertakingpicture

• Setuptime– don’tmovesinceabouttotakepicture(opencamerashutter)

• Holdtime– needtoholdstillaftershutteropensuntilcamerashuttercloses

• Timeclicktodata– timefromopenshutteruntilcanseeimageonoutput(viewscreen)

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HardwareTimingTerms

• SetupTime:whentheinputmustbestablebeforethe edgeoftheCLK

• HoldTime:whentheinputmustbestableafterthe edgeoftheCLK

• “CLK-to-Q”Delay:howlongittakestheoutputtochange,measuredfromthe edgeoftheCLK

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AccumulatorTiming1/2• Resetinputtoregisteris

usedtoforceittoallzeros(takespriorityoverDinput).

• Si-1 holdstheresultoftheith-1iteration.

• Analyzecircuittimingstartingattheoutputoftheregister.

AccumulatorTiming2/2• resetsignalshown.

• Also,inpracticeXmightnotarrivetotheadderatthesametimeasSi-1

• Si temporarilyiswrong,butregisteralwayscapturescorrectvalue.

• Ingoodcircuits,instabilityneverhappensaroundrisingedgeofclk.

ModelforSynchronousSystems

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• Collectionof CombinationalLogicblocksseparatedbyregisters• Feedbackisoptional• Clocksignal(s)connectsonlytoclockinputofregisters• Clock(CLK):steadysquarewavethatsynchronizesthesystem• Register:severalbitsofstatethatsamplesonrisingedgeofCLK(positiveedge-triggered)orfallingedge(negativeedge-triggered)

MaximumClockFrequency

• Whatisthemaximumfrequencyofthiscircuit?

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Period=MaxDelay=CLK-to-QDelay+CLDelay+SetupTime

Hint:Frequency=1/Period

CriticalPaths

Timing…

Note: delay of 1 clock cycle from input to output.Clock period limited by propagation delay of adder/shifter.

PipeliningtoimproveperformanceTiming…

• Insertion of register allows higher clock frequency• More outputs per second (higher bandwidth)• But each individual result takes longer (greater latency)

RecapofTimingTerms• Clock(CLK)- steadysquarewavethatsynchronizessystem• SetupTime - whentheinputmustbestablebefore the

risingedgeoftheCLK• HoldTime - whentheinputmustbestableafter therising

edgeoftheCLK• “CLK-to-Q” Delay- howlongittakestheoutputtochange,

measuredfromtherisingedgeoftheCLK

• Flip-flop - onebitofstatethatsampleseveryrisingedgeoftheCLK(positiveedge-triggered)

• Register - severalbitsofstatethatsamplesonrisingedgeofCLKoronLOAD(positiveedge-triggered)

Clickers/PeerInstruction

Whatismaximumclockfrequency?(assumeallunconnectedinputscomefromsomeregister)• A:5GHz• B:200MHz• C:500MHz• D:1/7GHz• E:1/6GHz

Clock->Q1nsSetup1nsHold1nsANDdelay1ns

Administrivia• NolectureonWed– studyformidterm• Midterm1isonThu2/25– Time6-8pm– Location

• 2050VLSB(aa-lz)• 1Pimentel(ma-zz)

– Coversuptoandincluding02/17lecture(CALL2)– 1handwritten,doublesided,8.5”x11”cheatsheet– We’llgiveyouMIPSgreensheet

• Emailssent-outtostudentsrequiringspecialaccommodationfortheexam– pleaserespond

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StudyAdvice

1. Reviewslides,book,worksheets,etc.andaddtoyourcheatsheet asyoudosoa. Thisstepisnottheend

2. Takeamockexamintheallottedtime,usingonlyyourcheatsheet

3. Gooversolutions,lookatwhytheanswersarewhattheyare(especiallyforquestionsyouansweredincorrectly)

4. Updatecheatsheet asnecessary5. if(!perfect)goto 2;

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