CS221: VHDL Examples

Dr.  A. Sahu

Dept of Comp. Sc. & Engg.Dept of Comp. Sc. & Engg.

Indian Institute of Technology Guwahati

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OutlineOutline• VHDL

Test benches Packages and Library–Test benches, Packages and Library–Generic and GeneratesVHDL Edit• VHDL Editor : emacs

• Examples

• Assignments: Please look at course website

• Online Demo in Class –Examples, GHDL, GTKWAVEp , ,

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Test BenchesTest Benches

• Purpose ‐ test correctness of Design UnderPurpose  test correctness of Design Under Test (DUT)– provide input stimulus– provide input stimulus

– observe outputs

compare against expected outputs– compare against expected outputs

• Test Bench is also a VHDL model

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Test bench for AdderTest bench

For (i=0;i<8;i++){it 10wait 10ns

Read (Truth Table)Send read A, B, Ci A

Adder

Receive S,Co from adderCompare with expectedif (error found)

B

Ci

S

Coif (error found)

Report Error }

Compare result

Expected S

Expected Co

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Test Bench Modelling

Test Bench Design Under 

Test 

• Test bench a separate VHDL entity

(DUT)

Signals

• Test bench a separate VHDL entity• Ports are connected to DUT’s ports

i/p port corresponding to DUT’s o/p port– i/p port corresponding to DUT s o/p port– o/p port corresponding to DUT’s i/p port

• Test bench instantiates the DUTTest bench instantiates the DUT • Stimulus generation and output monitoring in a separate VHDL processseparate VHDL process 

• Signals are connected to DUT’s ports5

Libraries and PackagesLibraries and Packages

• PACKAGE ‐ collection ofPACKAGE  collection of– Components

data types– data types

– functions/procedures

LIBRARY ll ti f PACKAGE• LIBRARY ‐ collection of PACKAGEs

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PackagesPACKAGE util ISPACKAGE util IS

COMPONENT c ISPORT (a: IN BIT, b: OUT BIT);

PackageEND COMPONENT

TYPEmy_int IS INTEGER RANGE ‐7 TO 7;

FUNCTION comp (a: BIT VECTOR)

Package Declaration

p ( _ )

RETURN BIT_VECTOR;END util;

PACKAGE BODY util ISFUNCTION comp (a: BIT_VECTOR) RETURN  Package BIT_VECTOR ISBEGIN

RETURN NOT a;

Body

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;

END comp;

END util;

Using a PackageUsing a PackageLibrary Name

Package Name

All Contents

PACKAGE util IS

COMPONENT c IS

Name Name

COMPONENT c ISPORT (a: IN BIT, b: OUT BIT);END COMPONENT

USE WORK.UTIL.ALL;

...

SIGNAL x: my int;TYPEmy_int IS INTEGER RANGE ‐7 TO 7;

FUNCTION comp (a: BIT_VECTOR)RETURN BIT_VECTOR;

y_ ;

a = comp (b);

_ ;

END util;

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LibrariesLibraries

• STDSTD – STANDARD : types/utilities (BIT, TIME, INTEGER,...)

• TEXTIO• TEXTIO

– interface to text files

• WORK

– default library for storing user designs

• STD_LOGIC_1164

– multi‐valued logicg

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TEXTIO PackageTEXTIO Package

• Data types and functions forData types and functions for – reading from text files

writing out text files– writing out text files

FILE f: TEXT IS “file_name”;

VARIABLE one line: line;VARIABLE one_line: line;VARIABLE str: STRING;...

READLINE (f, one_line);  ‐‐ read one line from fileREAD (str, one_line);  ‐‐ read a word from line

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WRITELINE (g, one_line); ‐‐ write one line to fileWRITE (str, one_line);  ‐‐ write a word into line

Design Parameterization:

GENERIC & GENERATEENTITY e ISGENERIC (delay: TIME := 2 NS; 

width: INTEGER := 4);PORT (a: IN BIT VECTOR (0 TO width);PORT (a: IN BIT_VECTOR (0 TO width);

b: OUT BIT_VECTOR (0 TO width)  );END e;

Default

Value

ARCHITECTURE a OF e ISBEGIN

b <= NOT a AFTER delay;

END a;

Generic

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Generic

Parameters

Passing GENERIC ParametersENTITY IS

;

ENTITY c ISGENERIC (delay: TIME := 4 ns); PORT (a: IN BIT; b: OUT BIT);END c;

ARCHITECTURE a OF e ISCOMPONENT cGENERIC (t: TIME:= 4 NS);

ARCHITECTURE def OF e ISCOMPONENT cGENERIC (t: TIME:= 4 NS);GENERIC (t: TIME:= 4 NS);

PORT (a: IN BIT, b: OUT BIT);END COMPONENT;

SIGNAL x, y: BIT;

GENERIC (t: TIME:  4 NS);PORT (a: IN BIT, b: OUT BIT);END COMPONENT;

SIGNAL x, y: BIT;, y ;

FOR ALL: c USE work.c (arc);

BEGIN

FOR ALL: c USE work.c (arc);

BEGIN

c1: c GENERIC MAP (3 ns)PORT MAP (x, y);END a;

c1: c PORT MAP (x, y);END def;

12Delay Parameter 3ns

Delay Default Value 4ns

GENERATE: Conditional and LoopedInstantiation

• Number of instances of DFF determined byNumber of instances of DFF determined by Generic Parameter n

Inp Outp

DD_F

0

DD_F

1

DD_F

2

DD_F

N‐1

Inp Outp

CLK

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GENERATE: Conditional and LoopedInstantiation

GENERIC (n: INTEGER)...Need intermediate

...

SIGNAL t: BIT_VECTOR (0 TO n‐1);

Need intermediate

signal t (0 to n‐1)

Inp Outp

t(0) t(1) t(2) t(n‐1)

DD_F

0

DD_F

1

DD_F

2

DD_F

N‐1

Inp Outp

CLK

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GENERATE StatementGENERATE Statement

SIGNAL t: BIT_VECTOR (0 TO n‐1);...

dff_0: DFF PORT MAP (Inp, Clk, t (0));dff_n: DFF PORT MAP (t (n‐1), Clk, Outp);FOR i IN 1 TO n‐1 GENERATE

dff_i: DFF PORT MAP ( t (i‐1), Clk, t (i) );END GENERATE;

Outp

DD_F

0

DD_F

1

DD_F

2

DD_F

N

Inp Outp

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CLK

N Bit Ripple Carry Adder: FAN Bit Ripple Carry Adder:  FAENTITY full_adder IS

PORT (a, b, c_in: IN std_logic; Sum, Carry: OUT std_logic ); 

END full_adder;

ARCHITECTURE full_adder_arch_1 OF full_adder IS

SIGNAL S1, S2, S3: std_logic;BEGINBEGIN

s3      <= ( a AND b )        after 5 ns;s2      <= ( c_in AND s1 ) after 5 ns;s1      <= ( a XOR b )        after 15 ns; Carry <= ( s2 OR s3 )      after 5 ns;Sum  <= ( s1 XOR c in ) after 15 ns;

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( _ ) ;

END full_adder_arch_1;

N Bit Ripple Carry AdderN Bit Ripple Carry AdderENTITY adder_bits_n IS 

GENERIC(n: INTEGER :=  2);

PORT (

Cin: IN std_logic;

a, b: IN std_logic_vector(n‐1 downto 0);S: OUT std_logic_vector(n‐1 downto 0);Cout: OUT std logicCout: OUT std_logic);  

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END;

N Bit Ripple Carry AdderN Bit Ripple Carry AdderARCHITECTURE ripple_n_arch OF adder_bits_n IS

COMPONENT full_adderPORT (x, y, z: IN std_logic; Sum, Carry: OUT std_logic);

END COMPONENT;END COMPONENT;

SIGNAL t: std_logic_vector(n downto 0);

BEGIN

t(0)   <= Cin; Cout <= t(n);( ) ; ( );

FA: FOR i in 0 to n‐1 GENERATEFA_i: full_adder PORT MAP (t(i), a(i), b(i), S(i), t(i+1));

end generate;

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end generate;END;

Test benches for 4 bit adder: Stimulus only ARCHITECTURE tb OF tb_adder_4 IS

COMPONENT adder bits n GENERIC(n: INTEGER := 2);COMPONENT adder_bits_n GENERIC(n: INTEGER := 2);PORT ( Cin: IN   std_logic;   a, b: IN  std_logic_vector(n‐1 downto 0);

S: OUT std_logic_vector(n‐1 downto 0);   Cout: OUT std_logic); END COMPONENT;END COMPONENT;

SIGNAL x, y, Sum:      std_logic_vector(n downto 0);

SIGNAL c Cout: std logic;SIGNAL c, Cout:          std_logic;BEGIN

x <= “0000”, “0001” after 200 ns, “0101”, after 400 ns;< “0010” “0011” ft 200 “1010” ft 400y <= “0010”, “0011” after 200 ns, “1010”, after 400 ns;

c <= ‘1’, ‘0’ after 200 ns;UUT_ADDER_4: adder_bits_n GENERIC MAP(4)  

PORT MAP ( S C )

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PORT MAP (c, x, y, Sum, Cout);END 

4 bit multiplexor 4x1

4x1

I0

I1

I2Y

4 Bit : 3 downto 04x1 Mux

I2

I3

S1 S0

entityMux is

port( I3:     in std_logic_vector(3 downto 0);I2:     in std logic vector(3 downto 0);_ g _ ( );

I1:     in std_logic_vector(3 downto 0);I0:     in std_logic_vector(3 downto 0);S: in std logic vector(1 downto 0);S:      in std_logic_vector(1 downto 0);O:      out std_logic_vector(3 downto 0)

);

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endMux;

Architecture of 4x1 MuxArchitecture of 4x1 Muxarchitecture behvioral of Mux is

Begin

process (I3,I2,I1,I0,S)begin    ‐‐ use case statementg

case S iswhen "00" =>        O <= I0;when "01" => O <= I1;when 01  =>        O <= I1;when "10" =>        O <= I2;when "11" =>        O <= I3;h h O "ZZZ"when others =>    O <= "ZZZ";

end case;

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end process;end behvioural;

Resister entity regis is

port(       rst, clk, load: in std_logic;input: in std logic vector( 3 downto 0 );input: in std_logic_vector( 3 downto 0 );output: out std_logic_vector( 3 downto 0 )

);

d iend regis;

architecture regis_arc of regis isbegin

process( rst, clk, load, input )begin

if( rst = '1' ) then output <= "0000";if( rst   1  ) then  output <   0000 ;

elsif( clk'event and clk = '1') thenif( load = '1' ) then output <= input; 

d if d if

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end if;     end if; end process;

end regis_arc;

How to Write FSM is VHDLHow to Write FSM is VHDL

S301010

S0 S1 S2InitC= 10

C

00000 00011 xxx00

01010

S4

C=

01 C=

11

entity fsm is

S511111

00101

entity fsm is

port(   rst, clk,proceed : in std_logic;comparison: in std_logic_vector( 1 downto 0 );

bl l l ld ld t td l i

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;

enable, xsel, ysel, xld, yld: out std_logic);

end fsm;

FSM ArchitectureFSM Architecturearchitecture fsm_arc of fsm is

i ( i i 0 2 3 )type states is ( init, s0, s1, s2, s3, s4, s5 );signal nState, cState: states;beging

Process1: process( rst, clk )begin

if( rst = '1' ) thenif( rst =  1  ) thencState <= init;

elsif( clk'event and clk = '1' ) thenS ScState <= nState;

end if;end process;

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FSM Architectureprocess( proceed, comparison, cState )begin

variable :  OP : std_loic_vector (4 downto 0);case cState iswhen init =>    if( proceed = '0' ) then       nState <= init;

else             nState <= s0;           end if;when s0 =>      OP <=  “ 00000 “ ; nState <= s1;h 1 > OP < “ 00001” St t < 2when s1 =>      OP <=  “ 00001”;  nState <= s2;

when s2 =>      OP<=  “ XXX01” ; if( comparison = "10" ) then        nState <= s3;

elsif( comparison = "01" ) then nState <= s4;elsif( comparison =  01  ) then          nState <= s4;elsif( comparison = "11" ) then         nState <= s5;              end if;

when s3 =>      OP <= “ 01010”  nState <= s2;when s4 =>      OP <=  “ 00101” ; nState <= s2;; ;

when s5 =>      OP <=  “11111” ;  nState <= s0;when others =>  nState <= s0;end case;

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enable <= OP(4);  xsel <= OP(3);ysel <= OP(2);xld <= OP(1);yld <= OP(0);end process;       

end fsm_arc;

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