cs3350b computer architecture winter 2015 lecture 5.7: single-cycle cpu: datapath control (part 2)...

CS3350B Computer Architecture

Winter 2015

Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2)

Marc Moreno Mazawww.csd.uwo.ca/Courses/CS3350b

[Adapted from lectures on Computer Organization and Design,

Patterson & Hennessy, 5th edition, 2013]

http://www.cse.psu.edu/~

Review: Processor Design 5 stepsStep 1: Analyze instruction set to determine datapath

requirements– Meaning of each instruction is given by register transfers– Datapath must include storage element for ISA registers– Datapath must support each register transferStep 2: Select set of datapath components & establish

clock methodologyStep 3: Assemble datapath components that meet the

requirementsStep 4: Analyze implementation of each instruction to

determine setting of control points that realizes the register transfer

Step 5: Assemble the control logic2

Processor Design: 5 stepsStep 1: Analyze instruction set to determine datapath

requirements– Meaning of each instruction is given by register transfers– Datapath must include storage element for ISA registers– Datapath must support each register transferStep 2: Select set of datapath components & establish

clock methodologyStep 3: Assemble datapath components that meet the

requirementsStep 4: Analyze implementation of each instruction to

determine setting of control points that realizes the register transfer

Step 5: Assemble the control logic3

Register-Register Timing: One Complete Cycle (Add/Sub)

Clk

PCRs, Rt, Rd,Op, Func

ALUctr

Instruction Memory Access Time

Old Value New Value

RegWr Old Value New Value

Delay through Control Logic

busA, BRegister File Access Time

Old Value New Value

busWALU Delay

Old Value New Value

Old Value New Value

New ValueOld Value

Register WriteOccurs Here32

ALUctr

clk

busW

RegWr

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs Rt

ALU

5Rd

4

Register-Register Timing: One Complete Cycle

Clk

PCRs, Rt, Rd,Op, Func

ALUctr

Instruction Memory Access Time

Old Value New Value

RegWr Old Value New Value

Delay through Control Logic

busA, BRegister File Access Time

Old Value New Value

busWALU Delay

Old Value New Value

Old Value New Value

New ValueOld Value

Register WriteOccurs Here32

ALUctr

clk

busW

RegWr

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs Rt

ALU

5Rd

5

3c: Logical Op (or) with Immediate

• R[rt] = R[rs] op ZeroExt[imm16]op rs rt immediate

016212631

6 bits 16 bits5 bits5 bits

immediate016 1531

16 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

What about Rt Read?

32

ALUctr

clk

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

Rd

ZeroExt 3216imm16

ALUSrc

01

0

1

ALU5

RegDst

Writing to Rt register (not Rd)!!

6

3d: Load Operations• R[rt] = Mem[R[rs] + SignExt[imm16]]

Example: lw rt,rs,imm16

op rs rt immediate016212631


32

ALUctr

clk

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

Rd

ZeroExt 3216imm16

ALUSrc

01

0

1

ALU

5

RegDst

7

3d: Load Operations

• R[rt] = Mem[R[rs] + SignExt[imm16]]Example: lw rt,rs,imm16



32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender 3216imm16

ALUSrcExtOp

MemtoReg

clk

01

0

1

ALU 0

1Adr

DataMemory

5

8

3e: Store Operations• Mem[ R[rs] + SignExt[imm16] ] = R[rt]

Ex.: sw rt, rs, imm16op rs rt immediate

016212631


32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Exten

der 3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In

32

MemWr01

0

1

AL

U 0

1

WrEn Adr

DataMemory

5

9

3e: Store Operations• Mem[ R[rs] + SignExt[imm16] ] = R[rt]

Ex.: sw rt, rs, imm16op rs rt immediate

016212631


32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Exten

der 3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In

32

MemWr01

0

1

AL

U 0

1

WrEn Adr

DataMemory

5

10

3f: The Branch Instruction

beq rs, rt, imm16– mem[PC] Fetch the instruction from memory– Equal = R[rs] == R[rt] Calculate branch condition– if (Equal) Calculate the next instruction’s address

• PC = PC + 4 + ( SignExt(imm16) x 4 )

else• PC = PC + 4



11

Datapath for Branch Operationsbeq rs, rt, imm16

Datapath generates condition (Equal)



Already have mux, adder, need special sign extender for PC, need equal compare (sub?)imm16

clk

PC

00

4nPC_sel

PC

Ext

Ad

derA

dder

Mu

x

Inst Address

32

ALUctr

clk

busW

RegWr

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs Rt

AL

U

5

=

Equal

12

Instruction Fetch Unit including Branch

• if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4


• How to encode nPC_sel?• Direct MUX select?• Branch inst. / not branch inst.

• Let’s pick 2nd option

Adr

InstMemory

nPC_selInstruction<31:0>

Equal

nPC_sel

Q: What logic gate?

imm16 clk

PC

00

4

PC Ext

AdderAdder

Mux

0

1

MUX ctrl

13

Putting it All Together: A Single Cycle Datapath

imm16

32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Exten

der

3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWrEqual

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

clk

PC

00

4

nPC_sel

PC

Ext

Adr

InstMemory

Ad

derA

dder

Mu

x

01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5

14

Datapath Control Signals• ExtOp: “zero”, “sign”• ALUsrc: 0 regB;

1 immed• ALUctr: “ADD”, “SUB”,

“OR”

• MemWr: 1 write memory• MemtoReg: 0 ALU; 1 Mem• RegDst: 0 “rt”; 1 “rd”• RegWr: 1 write register

32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Extender 3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWr01

0

1

ALU 0

1WrEn Adr

DataMemory

5

imm16

clk

PC

00

4nPC_sel & Equal

PC Ext

AdderAdder

Mux

Inst Address

0

1

15

Given Datapath: RTL Control

ALUctrRegDst ALUSrcExtOp MemtoRegMemWr

Instruction<31:0>

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel

Adr

InstMemory

DATA PATH

Control

Op

<0:5>

Fun

RegWr

<26:31>16

RTL: The Add Instruction

add rd, rs, rt– MEM[PC] Fetch the instruction from memory– R[rd] = R[rs] + R[rt]The actual operation– PC = PC + 4 Calculate the next instruction’s address

op rs rt rd shamt funct061116212631

6 bits 6 bits5 bits5 bits5 bits5 bits

17

Instruction Fetch Unit at the Beginning of Add• Fetch the instruction from Instruction memory:

Instruction = MEM[PC]– same for

all instructions

imm16

clk

PC

00

4 nPC_sel

PC Ext

AdderAdder

Mux

Inst Address

InstMemory Instruction<31:0>

18

Single Cycle Datapath during Add

R[rd] = R[rs] + R[rt]


32

ALUctr=ADD

clk

busW

RegWr=1

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=1

Extender

3216imm16

ALUSrc=0ExtOp=x

MemtoReg=0

clk

Data In32

MemWr=0

zero01

0

1

=

ALU 0

1WrEn Adr

DataMemory

5

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel=+4 instrfetchunitclk

19

Instruction Fetch Unit at End of Add

• PC = PC + 4– Same for all

instructions except: Branch and Jump

imm16

clk

PC

00

4 nPC_sel=+4

PC Ext

AdderAdder

Mux

Inst Address

InstMemory

20

P&H Figure 4.17

21

Summary of the Control Signals (1/2)inst Register Transfer

add R[rd] R[rs] + R[rt]; PC PC + 4

ALUsrc=RegB, ALUctr=“ADD”, RegDst=rd, RegWr, nPC_sel=“+4”

sub R[rd] R[rs] – R[rt]; PC PC + 4

ALUsrc=RegB, ALUctr=“SUB”, RegDst=rd, RegWr, nPC_sel=“+4”

ori R[rt] R[rs] + zero_ext(Imm16); PC PC + 4

ALUsrc=Im, Extop=“Z”, ALUctr=“OR”, RegDst=rt,RegWr, nPC_sel=“+4”

lw R[rt] MEM[ R[rs] + sign_ext(Imm16)]; PC PC + 4

ALUsrc=Im, Extop=“sn”, ALUctr=“ADD”, MemtoReg, RegDst=rt, RegWr, nPC_sel = “+4”

sw MEM[ R[rs] + sign_ext(Imm16)] R[rs]; PC PC + 4

ALUsrc=Im, Extop=“sn”, ALUctr = “ADD”, MemWr, nPC_sel = “+4”

beq if (R[rs] == R[rt]) then PC PC + sign_ext(Imm16)] || 00else PC PC + 4

nPC_sel = “br”, ALUctr = “SUB”

22

Summary of the Control Signals (2/2)

add sub ori lw sw beq jumpRegDstALUSrcMemtoRegRegWriteMemWritenPCselJumpExtOpALUctr<2:0>

1001000x

Add

1001000x

Subtract

01010000

Or

01110001

Add

x1x01001

Add

x0x0010x

Subtract

xxx00?1x

x

op target address


op rs rt immediate

R-type

I-type

J-type

add, sub

ori, lw, sw, beq

jump

funcop 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010Appendix A

10 0000See 10 0010 We Don’t Care :-)

23

Boolean Expressions for ControllerRegDst = add + subALUSrc = ori + lw + swMemtoReg = lwRegWrite = add + sub + ori + lw MemWrite = swnPCsel = beqJump = jump ExtOp = lw + swALUctr[0] = sub + beq (assume ALUctr is 00 ADD, 01 SUB, 10 OR)ALUctr[1] = or

Where:

rtype = ~op5 ~op4 ~op3 ~op2 ~op1 ~op0, ori = ~op5 ~op4 op3 op2 ~op1 op0 lw = op5 ~op4 ~op3 ~op2 op1 op0 sw = op5 ~op4 op3 ~op2 op1 op0

beq = ~op5 ~op4 ~op3 op2 ~op1 ~op0 jump = ~op5 ~op4 ~op3 ~op2 op1 ~op0

add = rtype func5 ~func4 ~func3 ~func2 ~func1 ~func0

sub = rtype func5 ~func4 ~func3 ~func2 func1 ~func0

How do we implement this in

gates?

24

Controller Implementation

addsuborilwswbeqjump

RegDstALUSrcMemtoRegRegWriteMemWritenPCselJumpExtOpALUctr[0]ALUctr[1]

“AND” logic “OR” logic

opcode func

25

Summary: Single-cycle Processor• Five steps to design a processor:

1. Analyze instruction set datapath requirements

2. Select set of datapath components & establish clock methodology

3. Assemble datapath meeting the requirements

4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.

5. Assemble the control logic• Formulate Logic Equations• Design Circuits

Control

Datapath

Memory

ProcessorInput

Output

26

cs3350b computer architecture winter 2015 lecture 5.7: single-cycle cpu: datapath control (part 2)...

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