cs4923/4/5/6/7/8/9 multi-channel digital audio decodersalsa-project.org/~james/datasheets/ ·...

Preliminary Product Information This document contains inCirrus Logic reserves the r

Copyright Cir(All RighP.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581http://www.cirrus.com

DATA7:0,

CS

Parallel or Serial Host Interf

CMPCLK,

Compressed

PLL

FILT1 VA

Framer

CMPDAT,

SCLKN2CMPREQ,LRCLKN2

SCLKN1,STCCLK2LRCLKN1

SDATAN1

Data InputInterface

DigitalAudioInput

Interface

FILT2 AGND

Clock Manager

CLKINCLKSEL

Shifter

InputBuffer

Controller

RAM InputBuffer

DGND[3:1] VD[3:1]

24-BitDSP Processing

RAMProgramMemory

RAMData

Memory

ROMProgramMemory

ROMData

Memory

STC

EMAD7:0,GPIO7:0

R/W,EMOE,

GPIO11

RD,DS,

EMWR,GPIO10

WR,SCDOUT,

PSEL,GPIO9

SCDIO,

A0,SCCLK S

RAM

BuffOutp

RESET

SDATAN2

CS4923/4/5/6/7/8/9

Multi-Channel Digital Audio Decoders
lCS4923/4/5/6/7/8 features
— Optional Virtual 3D Output— Simulated Surround and Programmable Effects— Real Time Autodetection of Dolby Digital®,

DTS®, MPEG Multi-Channel and PCM— Flexible 6-channel master or slave output

lCS4923/4/5/6/7/8/9 features— IEC60958/61937 transmitter for compressed-

data or linear-PCM output— Dedicated 8 kilobyte input buffer— DAC clock via analog phase-locked loop— Dedicated byte wide or serial host interface— Multiple compressed data input modes — PES layer decode for A/V synchronization— 96-kHz-capable PCM I/O, master or slave— Optional external memory and auto-boot — +3.3-V CMOS low-power, 44-pin package

lCS4923/4/5/6 features— Capable of Dolby Digital® Group A Performance— Dolby bass manager and crossover filters— Dolby Surround Pro Logic® Decoding

lCS4925/7: MPEG-2 Multi-Channel DecoderlCS4926/8: DTS Multi-Channel DecoderlCS4929: AAC 2-Channel (Low Complexity)

and MPEG-2 Stereo Decoder

DescriptionThe CS4923/4/5/6/7/8 is a family of multi-channel digitalaudio decoders, with the exception of the CS4929 as theonly stereo digital audio decoder. The CS4923/4/5/6 aredesigned for Dolby Digital and MPEG-2 Stereo decoding. Inaddition the CS4925 adds MPEG-2 multi-channel decodingcapability and the CS4926 provides DTS decoding. TheCS4927 is an MPEG-2 multi-channel decoder and theCS4928 is a DTS multi-channel decoder. The CS4929 is anAAC 2-channel and MPEG-2 stereo decoder. Each one ofthe CS4923/4/5/6/7/8/9 provides a complete and flexiblesolution for multi-channel (or stereo in the case of theCS4929) audio decoding in home A/V receiver/amplifiers,DVD movie players, out-board decoders, laser-disc players,HDTV sets, head-end decoders, set-top boxes, and similarproducts.

Cirrus Logic’s Crystal Audio Division provides a complete setof audio decoder and auxiliary audio DSP applicationprograms for various applications. For all complementaryanalog and digital audio I/O, Crystal Audio also provides acomplete set of high-quality audio peripherals including:multimedia CODECs, stereo A/D and D/A converters andIEC60958 interfaces. Of special note, the CS4226 is acomplementary CODEC providing a digital receiver, stereoA/D converters, and six 20-bit DACs in one package.

ORDERING INFORMATIONCS4923xx-CL 44-pin PLCC (xx = ROM revision) CRD4923 Reference design with CS4226CDB4923 Evaluation board

formation for a new product.ight to modify this product without notice.

1

rus Logic, Inc. 1999ts Reserved)

AUG ‘99DS262F2

ace DDDC

MCLK

SCLK

LRCLK

AUDATA[2.0]

XMT958

A1,CDIN

ABOOT,INTREQ

EXTMEM,GPIO8

OutputFormatter

erut

CS4923/4/5/6/7/8/9

TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4

ABSOLUTE MAXIMUM RATINGS ............................................................................................ 4RECOMMENDED OPERATING CONDITIONS ........................................................................ 4DIGITAL D.C. CHARACTERISTICS.......................................................................................... 4POWER SUPPLY CHARACTERISTICS ................................................................................... 4SWITCHING CHARACTERISTICS—RESET............................................................................ 5SWITCHING CHARACTERISTICS—CMPDAT, CMPCLK........................................................ 6SWITCHING CHARACTERISTICS—CLKIN ............................................................................. 7SWITCHING CHARACTERISTICS—INTEL® HOST MODE..................................................... 8SWITCHING CHARACTERISTICS—MOTOROLA® HOST MODE ........................................ 10SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT................................................ 16SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT............................................ 18

2. FAMILY OVERVIEW .............................................................................................................. 202.1 Multi-channel Decoder Family of Parts ............................................................................ 212.2 Document Strategy .......................................................................................................... 21

2.2.1 Hardware Documentation ............................................................................... 222.2.2 CS4923/4/5/6/7/8/9 Application Code User’s Guides ..................................... 22

2.3 Using the CS4923/4/5/6/7/8/9 .......................................................................................... 223. TYPICAL CONNECTION DIAGRAMS ................................................................................... 23

3.1 Multiplexed Pins ............................................................................................................... 233.2 Termination Requirements ............................................................................................... 243.3 Phase Locked Loop Filter ................................................................................................ 24

4. POWER .................................................................................................................................. 314.1 Decoupling ....................................................................................................................... 314.2 Analog Power Conditioning .............................................................................................. 314.3 Pads ................................................................................................................................. 31

5. CLOCKING ............................................................................................................................. 326. CONTROL .............................................................................................................................. 33

6.1 Boot and Control Mode Overview .................................................................................... 336.2 Parallel Host Interface ...................................................................................................... 34

6.2.1 Intel Parallel Host Mode .................................................................................. 346.2.2 Motorola Parallel Host Mode ........................................................................... 36

6.3 SPI Serial Host Interface .................................................................................................. 366.3.1 SPI Write ......................................................................................................... 376.3.2 SPI Read ......................................................................................................... 37

Contacting Cirrus Logic SupportFor a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:http://www.cirrus.com/corporate/contacts/

Dolby, Dolby Digital, and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corporation.Intel is a registered trademark of Intel Corporation.Motorola is a registered trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductor.All other names are trademarks, registered trademarks, or service marks of their respective companies.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the informationcontained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty ofany kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rightsof third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part ofthis publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, orotherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, nopart of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufactureor sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearingin this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-marks and service marks can be found at http://www.cirrus.com.

2 DS262F2

CS4923/4/5/6/7/8/9

6.4 I2C Serial Host Interface .................................................................................................. 396.4.1 I2C Write ......................................................................................................... 396.4.2 I2C Read ......................................................................................................... 39

6.5 External Memory .............................................................................................................. 416.5.1 External Memory and Autoboot ...................................................................... 43

7. DIGITAL INPUT & OUTPUT .................................................................................................. 447.1 Digital Audio Formats ....................................................................................................... 447.2 Digital Audio Input Port .................................................................................................... 467.3 Compressed Data Input Port ........................................................................................... 467.4 Parallel Digital Audio Data Input ...................................................................................... 467.5 Digital Audio Output Port ................................................................................................. 47

7.5.1 IEC60958 Output ............................................................................................ 488. PIN DESCRIPTIONS .............................................................................................................. 499. PACKAGE DIMENSIONS ...................................................................................................... 54

LIST OF FIGURESFigure 1. RESET Timing .................................................................................................................. 5Figure 2. Serial Compressed Data Timing ....................................................................................... 6Figure 3. CLKIN with CLKSEL = VSS = PLL Enable........................................................................ 7Figure 4. CLKIN with CLKSEL = VD = PLL Bypass ......................................................................... 7Figure 5. Intel Parallel Host Mode Read Cycle................................................................................. 9Figure 6. Intel Parallel Host Mode Write Cycle................................................................................. 9Figure 7. Motorola Parallel Host Mode Read Cycle ....................................................................... 11Figure 8. Motorola Parallel Host Mode Write Cycle........................................................................ 11Figure 9. SPI Control Port Timing................................................................................................... 13Figure 10. I2C Control Port Timing ................................................................................................. 15Figure 11. Digital Audio Input, Data and Clock Timing................................................................... 17Figure 12. Digital Audio Output, Data and Clock Timing ................................................................ 19Figure 13. I2C Control..................................................................................................................... 25Figure 14. I2C Control with External Memory ................................................................................. 26Figure 15. SPI Control .................................................................................................................... 27Figure 16. SPI Control with External Memory ................................................................................ 28Figure 17. Intel Parallel Control Mode ............................................................................................ 29Figure 18. Motorola Parallel Control Mode..................................................................................... 30Figure 19. SPI Timing..................................................................................................................... 38Figure 20. I2C Timing ..................................................................................................................... 40Figure 21. External Memory Interface ............................................................................................ 42Figure 22. Run-Time Memory Access ............................................................................................ 42Figure 23. Autoboot Timing Diagram.............................................................................................. 43Figure 24. I2S Format ..................................................................................................................... 45Figure 25. Left Justified Format...................................................................................................... 45Figure 26. Right Justified................................................................................................................ 45Figure 27. Multi-Channel Format (M == 20) ................................................................................... 45

LIST OF TABLESTable 1. Silicon Revisions .............................................................................................................. 20Table 2. Host Modes ...................................................................................................................... 33Table 3. Host Memory Map ............................................................................................................ 34Table 4. Intel Parallel Host Mode Pin Assignments........................................................................ 34Table 5. Parallel Input/Output Registers......................................................................................... 35Table 6. Motorola Parallel Host Mode Pin Assignments ................................................................ 36Table 7. SPI Serial Mode Pin Assignments.................................................................................... 36Table 8. I2C Serial Mode Pin Assignments .................................................................................... 39Table 9. Memory Interface Pins...................................................................................................... 41Table 10. Digital Audio Input Port................................................................................................... 46Table 11. Compressed Data Input Port .......................................................................................... 46Table 12. Digital Audio Output Port ................................................................................................ 47Table 13. MCLK/SCLK Master Mode Ratios .................................................................................. 47

DS262F2 3

CS4923/4/5/6/7/8/9

1. CHARACTERISTICS AND SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; all voltages with respect to 0 V)

WARNING: Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; all voltages with respect to 0 V)

DIGITAL D.C. CHARACTERISTICS (TA = 25 °C; VA, VD[3:1] = 3.3 V ±5%; measurements performed under static conditions.)

POWER SUPPLY CHARACTERISTICS (TA = 25 °C; VA, VD[3:1] = 3.3 V ±5%; measurements performed under operating conditions)

Parameter Symbol Min Max Unit

DC power supplies: Positive digitalPositive analog

||VA| – |VD||

VDVA

–0.3–0.3

-

3.633.630.4

VVV

Input current, any pin except supplies Iin - ±10 mA

Digital input voltage VIND –0.3 5.5 V

Ambient operating temperature (power applied) TAmax –55 125 °C

Storage temperature Tstg –65 150 °C

Parameter Symbol Min Typ Max Unit

DC power supplies: Positive digitalPositive analog

||VA| – |VD||

VDVA

3.133.13

-

3.33.3-

3.473.470.4

VVV

Ambient operating temperature TA 0 - 70 °C


High-level input voltage VIH 2.0 - - V

Low-level input voltage VIL - - 0.8 V

High-level output voltage at IO = –4.0 mA VOH VD × 0.9 - - V

Low-level output voltage at IO = 4.0 mA VOL - - VD × 0.1 V

Input leakage current Iin - - 1.0 µA


Power supply current: Digital operating: VD[3:1]Analog operating: VA

--

2254

4358

mAmA

4 DS262F2

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—RESET (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)z


RESET minimum pulse width low Trstl 100 - ns

All bidirectional pins high-Z after RESET low Trst2z - 50 ns

Configuration bits setup before RESET high Trstsu 50 - ns

Configuration bits hold after RESET high Trsthld 15 - ns

RESET

Trst2z

Trstl

Trstsu Trsthld

RD, WR,PSEL, ABOOT

All BidirectionalOutputs

Figure 1. RESET Timing

DS262F2 5

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—CMPDAT, CMPCLK (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)


Serial compressed data clock CMPCLK period Tcmpclk 37 - ns

CMPDAT setup before CMPCLK high Tcmpsu 5 - ns

CMPDAT hold after CMPCLK high Tcmphld 3 - ns

CMPCLK

Tcmpsu

Tcmpclk

CMPDAT

Tcmphld

Figure 2. Serial Compressed Data Timing

6 DS262F2

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—CLKIN (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)


CLKIN period for internal DSP clock mode Tclki 20 3800 ns

CLKIN high time for internal DSP clock mode Tclkih 8 ns

CLKIN low time for internal DSP clock mode Tclkil 8 ns

CLKIN period for external DSP clock mode Tclke 20 25 ns

CLKIN high time for external DSP clock mode Tclkeh 9 ns

CLKIN low time for external DSP clock mode Tclkel 9 ns

CLKIN

Tclkih Tclkil

Tclki

Figure 3. CLKIN with CLKSEL = VSS = PLL Enable

CLKIN

Tclkeh Tclkel

Tclke

Figure 4. CLKIN with CLKSEL = VD = PLL Bypass

DS262F2 7

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—INTEL ® HOST MODE (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can be defined as follows:

External CLKIN Mode: DCLK == CLKIN/3 before and during bootDCLK == CLKIN after boot

Internal Clock Mode:DCLK == 10MHz before and during boot, i.e. DCLK == 100nsDCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see CS4923/4/5/6/7/8/9 Hardware User’s Guide for more information)

2. This specification is characterized but not production tested.


Address setup before CS and RD low or CS and WR low Tias 5 - ns

Address hold time after CS and RD low or CS and WR low Tiah 5 - ns

Delay between RD then CS low or CS then RD low Ticdr 0 ∞ ns

Data valid after CS and RD low Tidd - 20 ns

CS and RD low for read (Note 1) Tirpw DCLK + 10 - ns

Data hold time after CS or RD high Tidhr 5 - ns

Data high-Z after CS or RD high (Note 2) Tidis - 15 ns

CS or RD high to CS and RD low for next read (Note 1) Tird 2*DCLK + 10 - ns

CS or RD high to CS and WR low for next write (Note 1) Tirdtw 2*DCLK + 10 - ns

Delay between WR then CS low or CS then WR low Ticdw 0 ∞ ns

Data setup before CS or WR high Tidsu 20 - ns

CS and WR low for write (Note 1) Tiwpw DCLK + 10 - ns

Data hold after CS or WR high Tidhw 5 - ns

CS or WR high to CS and RD low for next read (Note 1) Tiwtrd 2*DCLK + 10 - ns

CS or WR high to CS and WR low for next write (Note 1) Tiwd 2*DCLK + 10 - ns

8 DS262F2

CS4923/4/5/6/7/8/9

A1:0

DATA7:0

CS

WR

RD

Tias

Ticdr

Tiah

Tidd

Tirpw

Tidhr

Tidis

Tird Tirdtw

Figure 5. Intel Parallel Host Mode Read Cycle

A1:0

DATA7:0

CS

RD

WR

Tias

Ticdw

Tiah

Tiwpw

Tidhw

Tiwd Tiwtrd

Tidsu

Figure 6. Intel Parallel Host Mode Write Cycle

DS262F2 9

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—MOTOROLA ® HOST MODE (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes: 3. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can be defined as follows:

External CLKIN Mode: DCLK == CLKIN/3 before and during bootDCLK == CLKIN after boot

Internal Clock Mode:DCLK == 10MHz before and during boot, i.e. DCLK == 100nsDCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see CS4923/4/5/6/7/8/9 Hardware Users Guide for more information)

4. This specification is characterized but not production tested.


Address setup before CS and DS low Tmas 5 - ns

Address hold time after CS and DS low Tmah 5 - ns

Delay between DS then CS low or CS then DS low Tmcdr 0 ∞ ns

Data valid after CS and DS low with R/W high Tmdd - 20 ns

CS and DS low for read (Note 3) Tmrpw DCLK + 10 - ns

Data hold time after CS or DS high after read Tmdhr 5 - ns

Data high-Z after CS or DS high low after read (Note 4) Tmdis - 15 ns

CS or DS high to CS and DS low for next read (Note 3) Tmrd 2*DCLK + 10 - ns

CS or DS high to CS and DS low for next write (Note 3) Tmrdtw 2*DCLK + 10 - ns

Delay between DS then CS low or CS then DS low Tmcdw 0 ∞ ns

Data setup before CS or DS high Tmdsu 20 - ns

CS and DS low for write (Note 3) Tmwpw DCLK + 10 - ns

R/W setup before CS or DS low Tmrwsu 5 - ns

R/W hold time after CS or DS high Tmrwhld 5 - ns

Data hold after CS or DS high Tmdhw 5 - ns

CS or DS high to CS and DS low with R/W high for next read(Note 3)

Tmwtrd 2*DCLK + 10 - ns

CS or DS high to CS and DS low for next write (Note 3) Tmwd 2*DCLK + 10 - ns

10 DS262F2

CS4923/4/5/6/7/8/9

A1:0

DATA7:0

CS

R/W

DS

Tmas

Tmcdr

Tmah

Tmdd

Tmrpw

Tmdhr

Tmdis

Tmrd Tmrdtw

Tmrwsu

Tmrwhld

Figure 7. Motorola Parallel Host Mode Read Cycle

A1:0

DATA7:0

CS

R/W

DS

Tmas

Tmdsu

Tmah

Tmdhw

Tmwd Tmwtrd

TmwpwTmcdw

Tmrwsu

Tmrwhld

Figure 8. Motorola Parallel Host Mode Write Cycle

DS262F2 11

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—SPI CONTROL PORT (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes: 5. The specification fsck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the software. The relevant application code user’s manual should be consulted for the software speed limitations.

6. Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK.

7. SCDOUT should not be sampled during this time period.

8. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the second-to-last bit of the last byte of data during a read operation as shown.

9. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat this condition as a new read transaction. Raise chip select to end the current read transaction and then drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start a new read transaction.

10. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time.

11. This time is by design and not tested.

Parameter Symbol Min Max Units

SCCLK clock frequency (Note 5) fsck - 2000 kHz

CS falling to SCCLK rising tcss 20 - ns

Rise time of SCCLK line (Note 11) tr - 50 ns

Fall time of SCCLK lines (Note 11) tf - 50 ns

SCCLK low time tscl 150 - ns

SCCLK high time tsch 150 - ns

Setup time SCDIN to SCCLK rising tcdisu 50 - ns

Hold time SCCLK rising to SCDIN (Note 6) tcdih 50 - ns

Transition time from SCCLK to SCDOUT valid (Note 7) tscdov - 40 ns

Time from SCCLK rising to INTREQ rising (Note 8) tscrh - 200 ns

Rise time for INTREQ (Note 8) trr - (Note 10)

ns

Hold time for INTREQ from SCCLK rising (Note 9, 11) tscrl 0 - ns

Time from SCCLK falling to CS rising tsccsh 20 - ns

High time between active CS tcsht 200 - ns

Time from CS rising to SCDOUT high-Z (Note 11) tcscdo 10 ns

12 DS262F2

CS

4923/4/5/6/7/8/9

DS

262F2

13

tcsht

A6

cdo

tri-state

tcss tscl

trtsch

t cdisu

tscdov

t cdih

tscdov

tf

MSB

MSB

A0A6 A5

CS

SCCLK

SCDIN

SCDOUT

INTREQ

tsccsh

tscrltscrh

LSB

LSB

6 75

tcs

076210

R/W

Figure 9. SPI Control Port Timing

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS— I2C® CONTROL PORT (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes: 12. The specification fscl indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the software. The relevant application code user’s manual should be consulted for the software speed limitations.

13. Data must be held for sufficient time to bridge the 300-ns transition time of SCCLK. This hold time is by design and not tested.

14. This rise time is shorter than that recommended by the I2C specifications. For more information, see the section on SCP communications.

15. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the last data bit of the last byte of data during a read operation as shown.

16. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat this condition as a new read transaction. Send a new start condition followed by the 7-bit address and the R/W bit (set to 1 for a read). This time is by design and is not tested.

17. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time.

18. This time is by design and not tested.

Parameter Symbol Min Max Units

SCCLK clock frequency (Note 12) fscl 400 kHz

Bus free time between transmissions tbuf 4.7 µs

Start-condition hold time (prior to first clock pulse) thdst 4.0 µs

Clock low time tlow 1.2 µs

Clock high time thigh 1.0 µs

SCDIO setup time to SCCLK rising tsud 250 ns

SCDIO hold time from SCCLK falling (Note 13) thdd 0 µs

Rise time of SCCLK (Note 14), (Note 18) tr 50 ns

Fall time of SCCLK (Note 18) tf 300 ns

Time from SCCLK falling to CS4923/4/5/6/7/8/9 ACK tsca 40 ns

Time from SCCLK falling to SCDIO valid during read operation tscsdv 40 ns

Time from SCCLK rising to INTREQ rising (Note 15) tscrh 200 ns

Hold time for INTREQ from SCCLK rising (Note 16) tscrl 0 ns

Rise time for INTREQ trr (Note 17)

ns

Setup time for stop condition tsusp 4.7 µs

14 DS262F2

CS

4923/4/5/6/7/8/9

DS

262F2

15

tsusp

tscrl

ACK

8

stop

MSBA0A6 A5

SCCLK

SCDIO

INTREQ

R/W ACK

stop start

0 1 6 7 8 0 7

LSB

tscrh

tbuftsud

thdst tlow thdd thigh tr tf tsca

tscsdv

Figure 10. I2C Control Port Timing

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT (TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes: 19. Master mode timing specifications are characterized, not production tested.

20. Master mode is defined as the CS4923 driving LRCLKN1(2) and SCLKN1(2). Master or Slave mode can be programmed.

21. This timing parameter is defined from the non-active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid.

22. This timing parameter is defined from the active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid.

23. Slave mode is defined as SCLKN1(2) and LRCLKN1(2) being driven by an external source.


SCLKN1(2) period for both Master and Slave mode (Note 19) Tsclki 40 - ns

SCLKN1(2) duty cycle for Master and Slave mode (Note 19) 45 55 %

Master Mode (Note 19,20)

LRCLKN1(2) delay after SCLKN1(2) transition (Note 21) Tlrds - 10 ns

SDATAN1(2) setup to SCLKN1(2) transition (Note 22) Tsdsum 10 - ns

SDATAN1(2) hold time after SCLKN1(2) transition (Note 22) Tsdhm 5 - ns

Slave Mode (Note 23)

Time from active edge of SCLKN1(2) to LRCLKN1(2) transition Tstlr 10 - ns

Time from LRCLKN1(2) transition to SCLKN1(2) active edge Tlrts 10 - ns

SDATAN1(2) setup to SCLKN1(2) transition (Note 22) Tsdsus 5 - ns

SDATAN1(2) hold time after SCLKN1(2) transition (Note 22) Tsdhs 5 - ns

16 DS262F2

CS4923/4/5/6/7/8/9

SCLKN1SCLKN2

Tsclki

SDATAN1SDATAN2

LRCLKN1LRCLKN2

Tlrts Tstlr

Tsdsus Tsdhs

SLAVE MODE

SCLKN1SCLKN2

Tsclki

SDATAN1SDATAN2

LRCLKN1LRCLKN2

Tlrds

Tsdsum Tsdhm

MASTER MODE

Figure 11. Digital Audio Input, Data and Clock Timing

DS262F2 17

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT (TA = 25 °C; VA, VD = 3.3 V ±5%; measurements performed under static conditions.)

Notes: 24. MCLK can be an input or an output. These specifications apply for both cases.

25. Master mode timing specifications are characterized, not production tested.

26. Master mode is defined as the CS4923 driving both SCLK and LRCLK. When MCLK is an input, it is divided to produce SCLK and LRCLK.

27. This timing parameter is defined from the non-active edge of SCLK. The active edge of SCLK is the point at which the data is valid.

28. Slave mode is defined as SCLK and LRCLK being driven by an external source.

29. This specification is characterized, not production tested.


MCLK period (Note 24) Tmclk 40 - ns

MCLK duty cycle (Note 24) 40 60 %

SCLK period for Master or Slave mode (Note 25) Tsclk 40 - ns

SCLK duty cycle for Master or Slave mode (Note 25) 45 55 %

Master Mode (Note 25,26)

SCLK delay from MCLK rising edge, MCLK as an input Tsdmi 15 ns

SCLK delay from MCLK rising edge, MCLK as an output Tsdmo –5 10 ns

LRCLK delay from SCLK transition (Note 27) Tlrds 10 ns

AUDATA2–0 delay from SCLK transition (Note 27) Tadsm 10 ns

Slave Mode (Note 28)

Time from active edge of SCLKN1(2) to LRCLKN1(2) transition Tstlr 10 - ns

Time from LRCLKN1(2) transition to SCLKN1(2) active edge Tlrts 10 - ns

AUDATA2–0 delay from SCLK transition (Note 27,29) Tadss 15 ns

18 DS262F2

CS4923/4/5/6/7/8/9

SCLK (Output)

MCLK (Input)

Tsdmi

Tmclk

SCLK (Output)

MCLK (Output)

Tsdmo

Tmclk

SCLK

Tsclk

AUDATA2:0

LRCLKTlrds

Tadsm

MASTER MODE

SCLK

Tsclk

AUDATA2:0

LRCLKTstlr

Tlrts

Tadss

SLAVE MODE

Figure 12. Digital Audio Output, Data and Clock Timing

DS262F2 19

CS4923/4/5/6/7/8/9

isbe

enteredeontllmselyionatne

ed

ds.nes ard its

bets

or-pli-de

2. FAMILY OVERVIEW

The CS4923, CS4924, CS4925, CS4926, CS4927,CS4928 and the CS4929 are system on a chipsolutions for multi-channel (or stereo in the case ofthe CS4929) audio decompression and digitalsignal processing. Because the parts are primarilyRAM-based, a download of application software isrequired each time the CS4923/4/5/6/7/8/9 ispowered up. This document uses “download” and“code load” interchangeably. These terms shouldbe interpreted as meaning the transfer ofapplication code into the internalCS4923/4/5/6/7/8/9 memory from either anexternal microcontroller or through the autobootprocedure.

This document focuses on the electrical featuresand characteristics of these parts. The differentfeatures are described from a hardware designperspective. It should be understood that not all ofthe features portrayed in this document aresupported by all of the versions of application codeavailable. The application user’s guides (seesection 2.2.2) should be consulted to confirmwhich hardware features are supported by thesoftware. This document will be valuable to boththe hardware designer and the system programmer.

This data sheet covers the CS4923, CS4924,CS4925, CS4926, CS4927, CS4928 and CS4929.These parts are identical from an external electricalperspective. Internally each device has beentailored for supporting different decodingstandards. For this document CS4923/4/5/6/7/8/9has been replaced in certain places with CS492Xfor readability. Unless otherwise specifiedCS492X should be interpreted as applying to theCS4923, CS4924, CS4925, CS4926, CS4927,CS4928 and CS4929.

There are two revisions of silicon commerciallyavailable. The features available on Revision D area super-set of those features available on RevisionB. Differences between the revisions are pointed

out when features are discussed within thdocument. The silicon revision for any chip can determined by referencing Table 1 below.

These parts are generally targeted at two differmarket segments. The broadcast market whaudio/video (A/V) synchronization is required, anthe outboard decoder markets where audio/vidsynchronization is not required. The importadifferentiation is the format in which the data wibe received by the CS4923/4/5/6/7/8/9. In systewhere A/V synchronization is required from thCS4923/4/5/6/7/8/9, the incoming data is typicalPES encoded. In an outboard decoder applicatthe data typically comes in the IEC61937 form(as specified by the DVD consortium). Aimportant point to remember is that thCS4923/4/5/6/7/8/9 will support bothenvironments, but different downloads are requirdepending on the input data type.

Broadcast applications include (but are not limiteto) set top box applications, DVDs and digital TVOutboard decoder applications include standalodecoders and audio/video receivers. Often timesystem may be a hybrid between an outboadecoder and a broadcast system depending onfunctionality.

As discussed above, compressed audio canpacked in IEC61937, PES, or elementary formadepending on the decoder environment. Each fmat is supported by a separate download of apcation code. Consult the relevant Application Co

Revision B Revision DCS492301 CS492305CS492401 CS492405CS492501 CS492505CS492603 CS492604

CS492705CS492804CS492906

Table 1. Silicon Revisions

20 DS262F2

CS4923/4/5/6/7/8/9

ort
User’s Guide to determine which formats are sup-ported by a particular application. A brief descrip-tion of each format is presented below.
Elementary - an elementary bitstream consists onlyof compressed audio data (e.g., strictly the DolbyDigital bitstream); used primarily in broadcast en-vironments.

PES - a Packetized Elementary Stream (PES) bit-stream contains the elementary compressed audiostream and additional header information whichcan be used for A/V synchronization; used primari-ly in broadcast environments.

IEC61937 - a method of packing compressed audiosuch that it can be delivered using a bi-phase en-coded signal (e.g., S/PDIF output signal from DVDplayer); used primarily for outboard decoderswhere A/V synchronization is not required.

2.1 Multi-channel Decoder Family of Parts

CS4923 - Dolby DigitalTM Audio Decoder. TheCS4923 is the original member of the family and isintended to be used if only Dolby Digital decodingis required. For Dolby Digital, post processingincludes bass management, delays and Dolby ProLogic decoding. Separate downloads can also beused to support stereo to 5.1 channel effectsprocessing and stereo MPEG decoding.

CS4924 - Dolby DigitalTM Source ProductDecoder. The CS4924 is the stereo version of theCS4923 designed for source products such asDVD, HDTV, and set-top boxes. Separatedownloads are available for stereo decode of DolbyDigital and MPEG audio.

CS4925 - International Multi-Channel DVDAudio Decoder. The CS4925 supports both DolbyDigital and MPEG-2 multi-channel formats. Forboth Dolby Digital and MPEG-2 multi-channel,post processing includes bass management andDolby Pro Logic decoding. Separate downloads areavailable for decode of Dolby Digital and MPEG

audio. Another code load can be used to suppstereo to 5.1 channel effects processing.

CS4926 - DTS/Dolby® Multi-Channel AudioDecoder. The CS4926 supports both Dolby Digitaland DTS, or Digital Theater Surround. For DolbyDigital, post processing includes bass managementand Dolby Pro Logic. The Dolby Digital code andDTS code take separate code downloads. Separatedownloads can also be used to support stereo to 5.1channel effects processing and stereo MPEGdecoding.

CS4927 - MPEG-2 Multi-Channel Decoder. TheCS4927 supports MPEG-2 multi-channel decodingand should be used in applications where DolbyDigital decoding is not necessary. For MPEG-2multi-channel decoding, post processing includesbass management and Dolby Pro Logic decoding.Another code load can be used to support stereo to5.1 channel effects processing.

CS4928 - DTS Multi-Channel Decoder. TheCS4928 supports DTS multi-channel decoding andshould be used in applications where Dolby Digitaldecoding is not necessary. For DTS multi-channeldecoding, post processing includes bassmanagement. Separate downloads can also be usedto support stereo to 5.1 channel effects processingand stereo MPEG decoding.

CS4929 - AAC 2-Channel, (Low Complexity) andMPEG-2 Stereo Decoder. The CS4929 is capableof decoding both 2-channel AAC and MPEG-2audio. The CS4929 supports elementary and PESformats.

2.2 Document Strategy

Multiple documents are needed to fully define,understand and implement the functionality of theCS4923/4/5/6/7/8/9. They can be split up into twobasic groups: hardware and application codedocumentation. It should be noted that hardwareand application code are co-dependent and one cannot successfully use the device without an

DS262F2 21

CS4923/4/5/6/7/8/9

,

e

elye

understanding of both. The ‘ANXXX’ notationdenotes the application note number under whichthe respective user’s guide was released.

2.2.1 Hardware Documentation

CS4923/4/5/6/7/8/9 Family Data Sheet - Thisdocument describes the electrical characteristics ofthe device from timing to base functionality. This isthe hardware designers tool to learn the part’selectrical and systems requirements.

AN115 - CS4923/4/5/6/7/8/9 Hardware User’sGuide - describes the functional aspects of thedevice. An in depth description of communication,boot procedure, external memory and hardwareconfiguration are given in this document. Thisdocument will be valuable to both the hardwaredesigner and the system programmer.

2.2.2 CS4923/4/5/6/7/8/9 Application Code User’s Guides

The following application notes describe theapplication codes used with theCS4923/4/5/6/7/8/9. Whenever an application codeuser’s guide is referred to, it should be assumed thatone or more of the below documents are beingreferenced. The following list covers currentlyreleased application notes. This list will grow witheach new application released. For a current list ofreleased user’s guides please see www.crystal.comand search for the part number.

AN120 - Dolby Digital User’s Guide for theCS4923/4/5/6. This document covers the featuresavailable in the Dolby Digital code includingdelays, pink noise, bass management, Pro Logic,PCM pass through and Dolby Digital processingfeatures. Optional appendices are available thatdocument code for Dolby Virtual, Q-Surround andVMAx.

AN121 - MPEG User’s Guide for the CS4925.This document covers the features available in the

MPEG Multi-Channel code including delays, bassmanagement, Pro Logic, and MPEG processingfeatures.

AN122 - DTS User’s Guide for the CS4926CS4928. This document covers the featuresavailable in the DTS code including bassmanagement and DTS processing features.

AN123 - Surround User’s Guide for theCS4923/4/5/6/7/8. This code covers the differentStereo PCM to surround effects processing code.Optional appendices are available that documentCrystal Original Surround, Circle Surround andLogic 7.

AN140 - Broadcast Systems Guide for thCS4923/4/5/6/7/8/9. This guide describes allapplication code (e.g. Dolby Digital, MPEG, AAC)designed for broadcast systems such as HDTV andset-top box receivers. This document also providesa discussion of broadcast system considerationsand dependencies such as A/V synchronization andchannel change procedures.

2.3 Using the CS4923/4/5/6/7/8/9

No matter what application is being used on thechip, the following four steps are always followedto use the CS4923/4/5/6/7/8/9 in system.

1) Reset and/or Download Code - Detailedinformation in AN115

2) Hardware Configuration - Detailed informationin AN115

3) Application configuration - Detailedinformation in the appropriate ApplicationCode User’s guide

4) Kickstart - This is the “Go” command to thCS492X once the system is properconfigured. Information can be found in thappropriate Application Code User’s guide.

22 DS262F2

CS4923/4/5/6/7/8/9

inot

Tto

elfata

edr,

an

ir

istsns

.

tput

linsstal ann beioncialed

se., isse.

3. TYPICAL CONNECTION DIAGRAMS

Six typical connection diagrams have beenpresented to illustrate using the device with thedifferent communication modes available. Theyare as follows:

Figure 13: I2C ControlFigure 14: I2C Control with External MemoryFigure 15: SPI ControlFigure 16: SPI Control with External MemoryFigure 17: Intel Parallel Control ModeFigure 18: Motorola Parallel Control Mode

The following should be noted when viewing thetypical connection diagrams:

The pins are grouped functionally in each of thetypical connection diagrams. Please be aware thatthe CS4923/4/5/6/7/8/9 symbol may appeardifferently in each diagram.

The external memory interface is only supportedwhen a serial communication mode has beenchosen.

The typical connection diagrams demonstrate thePLL being used (CLKSEL is pulled low). Toenable external CLKIN, CLKSEL should be pulledhigh. The system designer must be aware thatcertain software features may not be available ifexternal CLKIN is used as the DSP must runslower when external CLKIN is used. The systemdesigner should also be aware of additional dutycycle requirements when using external CLKINmode. It is highly suggested that the systemdesigner take advantage of the PLL and pullCLKSEL low.

3.1 Multiplexed Pins

The CS4923/4/5/6/7/8/9 family of digital signalprocessors (DSPs) incorporate a large amount offlexibility into a 44 pin package. Because of thehigh degree of integration, many of these pins areinternally multiplexed to serve multiple purposes.

Some pins are designed to operate in one mode atpower up, and serve a different purpose when theDSP is running. Other pins have functionalitywhich can be controlled by the application runningon the DSP. In order to better explain the behaviorof the part, the pins which are multiplexed havebeen given multiple names. Each name is specificto the pin’s operation in a particular mode.

An example of this would be the use of pin 20 one of the serial control modes. During the boperiod of the CS492X, pin 20 is called ABOOT.ABOOT is sampled on the rising edge of RESE.If ABOOT is high the host must download code the DSP. If ABOOT is low when sampled, theCS492X goes into autoboot mode and loads itswith code by generating addresses and reading don EMAD[7:0]. When the device has been loadwith code and is running an application, howevepin 20 is called INTREQ. INTREQ is an open drainoutput used to inform the host that the DSP hasoutgoing message which should be read.

In this document, pins will be referred to by thefunctionality. The section “Pin Descriptions” onpage 49 describes each pin of the CS492X and lall of its names. Please refer to the Pin Descriptiosection when exact pin numbers are in question

The device has 12 general purpose input and ou(GPIO[11:0]) pins that all have multiplefunctionality. While in one of the parallecommunication modes (see section 6.2), these pare used to implement the parallel hocommunication interface. While in one of the serihost modes these pins are used to implementexternal memory interface. Alternatively while ione of the serial host modes these pins couldused for another general purpose if the applicatcode has been programmed to support the spepurpose. In this document the pins are referencby the name corresponding to their particular uSometimes GPIO[11:0], or some subset thereofused when referring to the pins in a general sen

DS262F2 23

CS4923/4/5/6/7/8/9

3.2 Termination Requirements

The CS4923/4/5/6/7/8/9 incorporates open drainpins which must be pulled high for properoperation. INTREQ (pin 20) is always an opendrain pin which requires a pull-up for properoperation. When in the I2C serial communicationmode, the SCDIO signal (pin 19) is open drain andthus requires a pull-up for proper operation.

Due to the internal, multiplexed design of the pins,certain signals may or may not require terminationdepending on the mode being used. If a parallelhost communication mode is not being used,GPIO[11:0] must be terminated or driven as thesepins will come up as high impedance inputs andwill be prone to oscillation if they are left floating.The specific termination requirements may varysince the state of some of the GPIO pins willdetermine the communication mode at the risingedge of reset (please see section 6 for more

information). For the explicit terminationrequirements of each communication mode pleasesee the typical connection diagrams.

Generally a 4.7k Ohm resistor is recommended foropen drain pins while a 10k Ohm resistor issufficient for the GPIO pins and unused inputs.

3.3 Phase Locked Loop Filter

The internal phase locked loop (PLL) of theCS4923/4/5/6/7/8/9 requires an external filter forsuccessful operation. The topology of this filter andcomponent values are shown in the typicalconnection diagrams. Care should be taken whenlaying out the filter circuitry to minimize tracelengths and to avoid any close routing of highfrequency signals. Any noise coupled on to thefilter circuit will be directly coupled into the PLL,which could affect performance.

24 DS262F2

CS4923/4/5/6/7/8/9

Figure 13. I2C Control

NOTE: A capaci tor pair (1 u F and 0.1 uF) must be supplied for each power pin.

MIC

RO

CO

NT

RO

LLE

R

I2C

IN

TE

RFA

CE

OSCILLATOR

DAC (S)

DIR orADC [S]

NOTE: +3.3VA is s imply +3.3VD after f i l ter ing through the ferr ite bead. Pin 32 must be referenced to +3.3VA

EMAD_GPIO [8:0]

+3.3V Supply (+3.3VD)

+3 .3VD+3.3VD

+3.3VA

+3.3VA

0.1 uF+ 1 uF 0.1 uF+ 1 uF 0.1 uF+ 1 uF

FERRITE BEAD

+ 1 uF 0.1 uF

4.70

K

4.70

K

4.70

K

4.70

K

10k

Res

isto

r P

ack

10k

3 3

10k

10k

OPT_TX

3 3

3 3

10k

10k

+ 2.2 uF

0.22 uF

CS4923/4/5/6/7/8/9

1

2

3

4

5

6

7

8

9

1 0

1 1

12

13

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

23

24

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

34

35

3 6

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4VD

1

DG

ND

1

X M T 9 5 8

W R _ _ G P I O 1 0

R D _ _ G P I O 1 1

S C D I N

S C C L K

G P I O 7

G P I O 6

G P I O 5

G P I O 4

VD

2

DG

ND

2

G P I O 3

G P I O 2

G P I O 1

G P I O 0

C S

S C D I O

I N T R E Q

G P I O 8

S DATA N

VD

3

DG

ND

3

S C L K N

S L R C L K N

C M P DAT

C M P C L K

C M P R E Q

CLKIN

C L K S E L

FLT2

FLT1

VA

AG

ND

R E S E T

D D

D C

AU DATA 2

AU DATA 1

AU DATA 0

L R C L K

S C L K

M C L K

+ 47 uF

NOTE: Only AUDATA0 connect ion appl ies for the CS4929

DS262F2 25

CS4923/4/5/6/7/8/9

NOTE: A capaci tor pair (1 uF and 0.1 uF) must be supplied for each power pin.

SYSTEM

MICRO

CONTROL LER

I2C

IN

TE

RFA

CE

D[7:0]

Q[7:0]

D[7:0]

Q[7:0]

OCTAL F/ FOCTAL F/ F

E X T E R N A LR O M

A[7:0 ]

A[15:8]

D[7:0 ]

/CE

/OE

DIR orADCs

DACs

OSCILLATOR

NOTE: +3.3VA is s imply +3.3VD after f i l t er ing through the ferr ite bead. Pin 32 must be referenced to +3.3VA

EMAD[7:0]


+3 .3VD+3.3VD

+3.3VA

+3.3VA

0.1 uF+ 1 uF 0.1 uF+ 1 uF 0.1 uF+ 1 uF + 1 uF 0.1 uF

4.70

K

4.70

K

4.70

K

10 k

10k

Res

isto

r P

ack

10k

10k

FERRITE BEAD10

k

4.70

K

10 k

3 3

OPT_TX

3 3

3 3

+ 2.2 uF

0.22 uF

+ 47 uF

10k

CS4923/4/5/6/7/8/9

1

2

3

4

5

6

7

8

9

1 0

1 1

12

13

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

23

24

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

34

35

3 6

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4VD

1

DG

ND

1

X M T 9 5 8

W R _ _ G P I O 1 0

R D _ _ E M O E

S C D I N

S C C L K

E M A D 7

E M A D 6

E M A D 5

E M A D 4

VD

2

DG

ND

2

E M A D 3

E M A D 2

E M A D 1

E M A D 0

C S

S C D I O

I N T R E Q _ _ A B O OT

E X T M E M

S DATA N

VD

3

DG

ND

3

S C L K N

S L R C L K N

C M P DAT

C M P C L K

C M P R E Q

CLKIN

C L K S E L

FLT2

FLT1

VA

AG

ND

R E S E T

D D

D C

AU DATA 2

AU DATA 1

AU DATA 0

L R C L K

S C L K

M C L K


Figure 14. I2C Control with External Memory

26 DS262F2

CS4923/4/5/6/7/8/9

Figure 15. SPI Control


MIC

RO

CO

NT

RO

LLE

R

SP

I IN

TE

RFA

CE

OSCILLATOR

DACs

DIR orADCs


EMAD_GPIO [8:0]


+3 .3VD+3.3VD

+3.3VA

+3.3VA


4.70

K

4.70

K

4.70

K

10 k

10

k

Res

isto

r P

ack

10k

10

k

F E R R I T E B E A D

3 31

0k

OPT_TX

3 3

3 3

+ 47 uF

+ 2.2 uF

0.22 uF

CS4923/4/5/6/7/8/9

1

2

3

4

5

6

7

8

9

1 0

1 1

12

13

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

23

24

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

34

35

3 6

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4VD

1

DG

ND

1

X M T 9 5 8

W R _ _ G P I O 1 0

R D _ _ G P I O 1 1

S C D I N

S C C L K

G P I O 7

G P I O 6

G P I O 5

G P I O 4

VD

2

DG

ND

2

G P I O 3

G P I O 2

G P I O 1

G P I O 0

C S

S C D O U T

I N T R E Q

G P I O 8

S DATA N

VD

3

DG

ND

3

S C L K N

S L R C L K N

C M P DAT

C M P C L K

C M P R E Q

C L K I N

C L K S E L

FLT2

FLT1

VA

AG

ND

R E S E T

D D

D C

AU DATA 2

AU DATA 1

AU DATA 0

L R C L K

S C L K

M C L K


DS262F2 27

CS4923/4/5/6/7/8/9

Figure 16. SPI Control with External Memory

NOTE: A capaci tor pair (1 u F and 0.1 uF) must be supplied for each power pin.

SYSTEM

MICRO

CONTROL LER

SP

I IN

TE

RFA

CE

D[7:0]

Q[7:0]

D[7:0]

Q[7:0]

OCTAL F/ FOCTAL F/ F

E X T E R N A LR O M

A[7:0 ]

A[15:8]

D[7:0 ]

/CE

/OE

DIR orADCs

DACs

OSCILLATOR

NOTE: +3.3VA is s imply +3.3VD after f i l ter ing through the ferr ite bead. Pin 32 must be referenced to +3.3VA

EMAD[7:0]


+3 .3VD+3.3VD

+3.3VA

+3.3VA


4.70

K

4.70

K

4.70

K

10 k

10k

Res

isto

r P

ack

10k

10k


10k

3 3

OPT_TX

10k

3 3

3 3

+ 47 uF

+ 2.2 uF

0.22 uF

CS4923/4/5/6/7/8/9

1

2

3

4

5

6

7

8

9

1 0

1 1

12

13

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

23

24

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

34

35

3 6

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4VD

1

DG

ND

1

X M T 9 5 8

W R _ _ G P I O 1 0

R D _ _ E M O E

S C D I N

S C C L K

E M A D 7

E M A D 6

E M A D 5

E M A D 4

VD

2

DG

ND

2

E M A D 3

E M A D 2

E M A D 1

E M A D 0

C S

S C D O U T

I N T R E Q _ _ A B O OT

E X T M E M

S DATA N

VD

3

DG

ND

3

S C L K N

S L R C L K N

C M P DAT

C M P C L K

C M P R E Q

C L K I N

C L K S E L

FLT2

FLT1

VA

AG

ND

R E S E T

D D

D C

AU DATA 2

AU DATA 1

AU DATA 0

L R C L K

S C L K

M C L K


28 DS262F2

CS4923/4/5/6/7/8/9

Figure 17. Intel Parallel Control Mode


MIC

RO

CO

NT

RO

LLE

R

INT

IN

TE

RFA

CE

OSCILLATOR

DIR orADCs

DACs


DATA[7:0]


+3 .3VD+3.3VD

+3.3VA

+3.3VA

0.1 uF+ 1 uF 0.1 uF+ 1 uF 0.1 uF+ 1 uF + 1 uF

4.70

K

4.70

K

4.70

K

Res

isto

r P

ack

10k

10k

10k

10k

10k

3 3

3 3

10k

3 3

OPT_TX

+ 47 uF

+ 2.2 uF

0.22 uF

CS4923/4/5/6/7/8/9

1

2

3

4

5

6

7

8

9

1 0

1 1

12

13

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1 2 2

23

24

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

34

35

3 6

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4VD

1

DG

ND

1

X M T 9 5 8

W R

R D

A 1

A 0

DATA 7

DATA 6

DATA 5

DATA 4

VD

2

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2

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DATA 2

DATA 1

DATA 0

C S

P S E L _ G P I O 9

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S L R C L K N

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FLT1

VA

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ND

R E S E T

D D

D C

AU DATA 2

AU DATA 1

AU DATA 0

L R C L K

S C L K

M C L K


0.1 uF


DS262F2 29

CS4923/4/5/6/7/8/9

Figure 18. Motorola Parallel Control Mode


MIC

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CS4923/4/5/6/7/8/9

1

2

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5

6

7

8

9

1 0

1 1

12

13

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1 2 2

23

24

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2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

34

35

3 6

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4VD

1

DG

ND

1

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R / W _ _ R D

A 1

A 0

DATA 7

DATA 6

DATA 5

DATA 4

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2

DATA 3

DATA 2

DATA 1

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C S

P S E L _ G P I O 9

I N T R E Q

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30 DS262F2

CS4923/4/5/6/7/8/9

g. Aerison

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3.3

4. POWER

The CS492X requires a 3.3V digital power supplyfor the digital logic within the DSP and a 3.3Vanalog power supply for the internal PLL. Thereare three digital power pins, VD1, VD2 and VD3,along with three digital grounds, DGND1, DGND2and DGND3. There is one analog power pin, VAand one analog ground, AGND. The DSP willperform at its best when noise has been eliminatedfrom the power supply. The recommendationsgiven below for decoupling and powerconditioning of the CS492X will help to ensurereliable performance.

4.1 Decoupling

It is good practice to decouple noise from thepower supply by placing capacitors directlybetween the power and ground of the CS492X.Each pair of power pins (VD1/DGND,VD2/DGND, VD3/DGND, VA/AGND) shouldhave its own decoupling capacitors. Therecommended procedure is to place both a 0.1uF

and a 1uF capacitor as close as physically possibleto each power pin. The 0.1uF capacitor should beclosest to the device (typically 5mm or closer).

4.2 Analog Power Conditioning

In order to obtain the best performance from theCS4923/4/5/6/7/8/9’s internal PLL, the analopower supply (VA) must be as clean as possibleferrite bead should be used to filter the 3.3V powsupply for the analog portion of the CS492X. Thpower scheme is shown in the typical connectidiagrams.

4.3 Pads

Revision D and all subsequent revisionincorporate 5V tolerant pads. This means that whthe CS492X power supplies require 3.3 volts, 5 vsignals can be applied to the inputs withodamaging the part.

The I/O pads for Revision B of the CS4923/4/5are not 5 volt tolerant. Input levels for revision B othe CS4923/4/5/6 should be no greater than

DS262F2 31

CS4923/4/5/6/7/8/9

)ford

5. CLOCKING

Revision D of the CS4923/4/5/6/7/8/9 alsoincorporates a programmable phase locked loop(PLL) clock synthesizer. The PLL takes an inputreference clock and produces all the internal clocksrequired to run the internal DSP and to providemaster mode timing to the audio input/outputperipherals. The clock manager also includes a33-bit system time clock (STC) to support audioand video synchronization in broadcastapplications.

The PLL can be internally bypassed by connectingthe CLKSEL pin to VD. This connectionmultiplexes the CLKIN pin directly to the DSPclock. Care should be taken to note the minimumCLKIN requirements when bypassing the PLL.

The PLL reference clock has three possible sourcesthat are routed through a multiplexer controlled bythe DSP: SCLKN2, SCLKN1, and CLKIN.Typically, in audio/video environments like set-topboxes, the CLKIN pin is connected to 27 MHz. Inother scenarios such as an A/V receiver design, thePLL can be clocked through the CLKIN pin witheven multiples of the desired sampling rate or withan already available clock source. CLKIN istypically a multiple of a standard samplingfrequency in this scenario (e.g. 11.2896 MHz).

The clock manager is controlled by the DSPapplication software. Please refer to the HardwareUser’s Guide for the CS4923/4/5/6/7/8/9 (AN115and all relevant application code user’s guides information on supported CLKIN frequencies anhow to set up and control the internal PLL.

32 DS262F2

CS4923/4/5/6/7/8/9

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6. CONTROL

Control of the CS4923/4/5/6/7/8/9 can beaccomplished through one of four methods. TheCS492X supports I2C and SPI serialcommunication. In addition the CS492X supportsboth a Motorola and Intel byte wide parallel hostcontrol mode. Only one of the four communicationmodes can be selected for control. The states of theRD, WR, and PSEL pins at the rising edge ofRESET determine the interface type as shown intable 2.

Whichever host communication mode is used, hostcontrol of the CS4923/4/5/6/7/8/9 is handledthrough the application software running on theDSP. Configuration and control of the CS492Xdecoder and its peripherals are indirectly executedthrough a messaging protocol supported by thedownloaded application code. In other wordssuccessful communication can only beaccomplished by following the low level hardwarecommunication format and high level messagingprotocol. The specifications of the messagingprotocol can be found in any of the applicationcode user’s guides.

It should be noted that when using the CS4926 orCS4928 for DTS decoding, an external memoryinterface must be used for DTS tables that arerequired for decoding. (see section 6.5 forinformation on external memory). The externalmemory interface and the parallel interface modescan not be used together. For this reason the systemdesigner must use one of the serial communicationmodes with external memory if designing with the

CS4926 or CS4928 for DTS decode. An imagethe DTS tables is available from the factory.

Below is a brief discussion of each of thcommunication modes available for thCS4923/4/5/6/7/8/9. For a complete description these communication modes along with flocharts, pseudocode and restrictions, please conthe CS4923/4/5/6/7/8/9 Hardware User’s Guide.complete understanding of the decoder and operation can not be accomplished withoconsulting the CS4923/4/5/6/7/8/9 HardwaUser’s Guide and the application code useguides.

6.1 Boot and Control Mode Overview

Regardless of which communication mode is usethe CS4923/4/5/6/7/8/9 must be booted and loadwith code at run time. The general sequence fromhardware perspective is as follows:

5) RESET Low

6) Set Communication Configuration Pins

7) RESET High

8) Download Code

9) Configure Hardware

10) Configure Application Code

11) Kickstart the Decoder

The host has three options for code download:

• Parallel Download through the parallel host interface

• Serial download through either the SPI or I2Cinterface

• Autoboot with external memory when using serial communication mode.

Once again the CS4923/4/5/6/7/8/9 HardwaUser’s Guide should be consulted for a compledescription of the boot and download proceduincluding the necessary communicatiohandshaking. Hardware configuration is als

RD(Pin 5)

WR(Pin 4)

PSEL(Pin 19)

Host Interface Mode

1 1 1 8-bit Motorola1 1 0 8-bit Intel0 1 X Serial I2C1 0 X Serial SPI

Table 2. Host Modes

DS262F2 33

CS4923/4/5/6/7/8/9

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the

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covered in the CS4923/4/5/6/7/8/9 HardwareUser’s Guide. Application configuration isdescribed in the application code user’s guide forthe code being used.

6.2 Parallel Host Interface

The byte wide parallel host interface of theCS492X supports application code download,communication for hardware and applicationconfiguration, compressed data input, and PCMdata input. When using either Intel or Motorolamodes, the parallel interface is implemented usingfour 8-bit internal registers which are selectableusing inputs A1 and A0 as shown in table 3. Table5 shows the individual registers and their bitmapping.

In either the Intel or Motorola mode the INTREQpin can be used to interrupt the host when the DSPhas unsolicited outgoing messages to be read. Forspecific details on the behavior of INTREQ in oneof the parallel modes, please see theCS4923/4/5/6/7/8/9 Hardware User’s Guide.

6.2.1 Intel Parallel Host Mode

Intel parallel host mode is accomplished with CS,RD, WR, A[1:0], and DATA[7:0]. Table 4 showsthe pin name, pin description and pin number of

each signal on the CS4923/4/5/6/7/8/9. RD andWR have no effect when CS is held high.

When the DSP writes a byte to the HOSTMSregister, the HOUTRDY bit in the CONTROLregister is set to indicate that there is data to read. To initiate a read cycle the host should drCS low. When CS is low, RD becomes the outpuenable for DATA[7:0]. When CS and RD are low,the contents of register address A[1:0] are drivon the DATA[7:0] bus. The address A[1:0] must bvalid a minimum time before either CS or RD goeslow. The HOUTRDY bit of the CONTROLregister is cleared after the host reads from HOSTMSG register.

Driving both CS and WR low begins an 8-bit writecycle. The address A[1:0] must be valid minimum time before either CS or WR goes low.On the first rising edge of CS or WR, the writecycle ends and DATA[7:0] are latched internalby the CS492X. Data must be held sufficiently satisfy the hold time as given in the timing sectioThe HINBSY bit is set when the host writes thHOSTMSG register. This bit is cleared when thbyte in the HOSTMSG register is read by the DS

During RESET low, all control signals have noeffect and DATA[7:0] are high impedance.

A1(Pin 6)

A0(Pin 7)

Register Name Register Function

1 1 CMPDATA 8-bit compressed data to input unit (write only)

1 0 PCMDATA 8-bit linear PCM data to input unit (write only)

0 1 CONTROL Multi-bit control regis-ter for setup and handshaking (R/W)

0 0 HOSTMSG 8-bit control pipe message register (R/W)

Table 3. Host Memory Map

Pin Name Pin Description Pin NumberCS Chip Select 18RD Output Enable 5WR Write Enable 4A1 Register Address 1 6A0 Register Address 0 7INTREQ Interrupt Request 20DATA7 Data Bit 7 8DATA6 Data Bit 6 9DATA5 Data Bit 5 10DATA4 Data Bit 4 11DATA3 Data Bit 3 14DATA2 Data Bit 2 15DATA1 Data Bit 1 16DATA0 Data Bit 0 17

Table 4. Intel Parallel Host Mode Pin Assignments

34 DS262F2

CS4923/4/5/6/7/8/9

Host Message (HOSTMSG) Register, A[1:0] = 00b

HOSTMSG7–0 Host data to and from the DSP. A read or write of this register operates handshake bits between the internal DSP and the external host. This register typically passes multibyte messages car-rying microcode, control, and configuration data. HOSTMSG is physically implemented as two independent registers for input and output. (Read and write)

Host Control (CONTROL) Register, A[1:0] = 01b

Reserved Always write a 0 for future compatibility.

CMPRST When set, initializes the CMPDATA compressed data input channel. Writing a one to this bit holds the port in reset. Writing zero enables the port. This bit must be low for normal operation. (Write only)

PCMRST When set, initializes the linear PCM input channel. This bit is toggled to indicate the first sample of the left channel for a PCM stream. Writing a one to this bit holds the port in reset. Writing zero enables the port. This bit must be low for normal operation. (Write only)

MFC When high, indicates that the PCMDATA input buffer is almost full. The input buffer threshold level is application code dependent. (Read only)

MFB When high, indicates that the CMPDATA input buffer is almost full. The input buffer threshold level is application code dependent. (Read only)

HINBSY Set when the host writes to HOSTMSG. Cleared when the DSP reads data from the HOSTMSG register. The host reads this bit to determine if the last host byte written has been read by the DSP. (Read only)

HOUTRDY Set when the DSP writes to the HOSTMSG register. Cleared when the host reads data from the HOSTMSG register. The DSP reads this bit to determine if the last DSP output byte has been read by the host. (Read only)

Reserved Always write a 0 for future compatibility.

PCM Data Input (PCMDATA) Register, A[1:0] = 10b

PCMDATA7–0 The host writes PCM data to the DSP input buffer at this address. (Write only)

Compressed Data Input (CMPDATA) Register, A[1:0] = 11b

CMPDATA7–0 The host writes compressed data to the DSP input buffer at this address. (Write only)

7 6 5 4 3 2 1 0HOSTMSG7 HOSTMSG6 HOSTMSG5 HOSTMSG4 HOSTMSG3 HOSTMSG2 HOSTMSG1 HOSTMSG0

7 6 5 4 3 2 1 0Reserved CMPRST PCMRST MFC MFB HINBSY HOUTRDY Reserved

7 6 5 4 3 2 1 0PCMDATA7 PCMDATA6 PCMDATA5 PCMDATA4 PCMDATA3 PCMDATA2 PCMDATA1 PCMDATA0

7 6 5 4 3 2 1 0CMPDATA7 CMPDATA6 CMPDATA5 CMPDATA4 CMPDATA3 CMPDATA2 CMPDATA1 CMPDATA0

Table 5. Parallel Input/Output Registers

DS262F2 35

CS4923/4/5/6/7/8/9

6.2.2 Motorola Parallel Host Mode

Motorola parallel host mode is accomplished withCS, DS, R/W, A[1:0], and DATA[7:0]. Table 6shows the pin name, pin description and pinnumber of each signal on the CS4923/4/5/6/7/8/9.In Motorola host interface mode, the host interfacepins act as an active-low chip select, CS, an active-low data strobe, DS, and a R/W control signal.Internally to the CS492X, DS and CS are logicallyANDED. Therefore, in some cases, DS and CS canbe externally tied together with a common active-low strobe. Otherwise, in long decoder delayscenarios, read or write cycles can be terminatedearlier by connecting the microprocessor active-low data-strobe signal to the CS492X DS and adelayed final active-low chip select independentlyto the CS pin.

When the DSP writes a byte to the HOSTMSGregister, the HOUTRDY bit in the CONTROLregister is set to indicate that there is data to beread. During read cycles, DATA[7:0] are drivenwhen R/W is high and DS and CS are both low.DATA[7:0] are released with the earliest of CS orDS going high. The HOUTRDY bit of theCONTROL register is cleared after the host readsfrom the HOSTMSG register.

Write cycles occur with R/W low followed by DSand CS both going low. The A[1:0] address pinsselect the specific address of the register to bewritten and DATA[7:0] carry the data to be written.For write cycles, the first of CS and DS going highlatches data. Data must be held sufficiently tosatisfy the hold time as given in the timing section.The HINBSY is set when the host writes theHOSTMSG register. This bit is cleared when thebyte in the HOSTMSG is internally read by theDSP.

6.3 SPI Serial Host Interface

For SPI communications, the CS4923/4/5/6/7/8/9always acts as a slave. Serial SPI communicationwith the CS4923/4/5/6/7/8/9 is accomplished with5 communication lines: CS, SCCLK, SCDIN,SCDOUT and INTREQ. Table 7 shows the pinname, pin description and pin number of eachsignal on the CS4923/4/5/6/7/8/9. CS is an activelow chip select and must be held low for writes toand reads from the part. SCCLK is an input to theCS492X that clocks data in and out of the device onits rising edge. SCDIN is the data input and shouldbe valid on the rising edge of SCCLK. SCDOUT isthe data output and will be valid on the rising edgeof SCCLK. INTREQ is an open drain, active-lowinterrupt request signal that is driven low by theCS492X when there is data to be read out.

Pin Name Pin Description Pin NumberCS Chip Select 18DS Data Strobe 4R/W Read or Write Enable 5A1 Register Address 1 6A0 Register Address 0 7INTREQ Interrupt Request 20DATA7 Data Bit 7 8DATA6 Data Bit 6 9DATA5 Data Bit 5 10DATA4 Data Bit 4 11DATA3 Data Bit 3 14DATA2 Data Bit 2 15DATA1 Data Bit 1 16DATA0 Data Bit 0 17

Table 6. Motorola Parallel Host Mode Pin Assignments

Pin Name Pin Description Pin NumberCS Chip Select 18SCDIN Serial Data Input 6SCCLK Serial Control Clock 7SCDOUT Serial Data Output 19INTREQ Interrupt Request 20

Table 7. SPI Serial Mode Pin Assignments

36 DS262F2

CS4923/4/5/6/7/8/9

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6.3.1 SPI Write

When writing to the device in SPI, the sameprotocol can be used for sending a byte, a word oran entire download image as long as transfers occuron byte boundaries. Figure 19 illustrates therelative timing necessary for a three byte transfer tothe CS492X. The host initiates an SPI write bydriving CS low, followed by a 7-bit address and theread/write bit set low to indicate a write. TheCS4923/4/5/6/7/8/9 internal 7-bit address isinitially assigned to 000 0000b following a reset.The 7-bit address sent to the CS492X must matchits internal address or the incoming data will beignored. Address checking can be changed (eitherdisabled or an actual address change) if desired.Address checking configuration is documented inthe hardware configuration section of theCS4923/4/5/6/7/8/9 Hardware User’s guide.

Data should be shifted into the CS492X mostsignificant bit first with data being valid at therising edge of SCCLK. It should be noted that datais internally transferred to the DSP on the fallingedge of the eighth SCCLK after the eighth data bitof a byte. For this reason SCCLK must transitionfrom high to low on the last bit of each byte or aloss of data will occur. If this final transfer ofSCCLK does not occur the final byte will be lostand successful communication will not be possible.

6.3.2 SPI Read

The CS4923/4/5/6/7/8/9 will always indicate that ithas data to be read by asserting the INTREQ linelow. The host must recognize the request and starta read transaction with the CS492X. The sameprotocol will be used whether reading a byte ormultiple bytes. Figure 19 also illustrates therelative timing of a three byte SPI read.

The host initiates an SPI read by driving CS low,followed by a 7-bit address and the read/write set high to indicate a read. The CS492X internalbit address is initially assigned to 000 0000following a reset. The 7-bit address sent to tCS492X must match its internal address or tincoming data will be ignored. Address checkincan be disabled or the actual address can changed if desired. Address checkinconfiguration is documented in the hardwaconfiguration section of the CS4923/4/5/6/7/8Hardware User’s guide.

After the address byte the host should clock dout of the device one byte at a time until INTREis no longer low. The host shifts data using trising edge of SCCLK. The data is valid on thrising edge of SCCLK and transitions occur on tfalling edge. In SPI mode, the INTREQ pin isdeasserted immediately following the rising edof the second-to-last data bit of the current bybeing transferred if there is no more data to be reThe INTREQ pin is guaranteed to stay deassert(high) until the rising edge of SCCLK for the lasdata bit.

If there is more data to be read from the DSP befthe rising edge of SCCLK for the second-to-ladata bit, then INTREQ remains asserted lowImmediately following the falling edge of SCCLKfor the last data bit of the current byte, the next dbyte loads into the internal serial shift register. Thost should continue to read this new byte. It important to note that once the data is in the shregister, clocks on the SCCLK line shift the dabits out of the shift register as long as CS is low.

For a thorough look at SPI communication ancritical additional comments on INTREQ behaviorreference the CS4923/4/5/6/7/8/9 Hardware UseGuide.

DS262F2 37

CS

4923/4/5/6/7/8/9

38D

S262F

2

D5 D4 D3 D2 D1 D0

Note 1 Note 2

D5 D4 D3 D2 D1 D0

to last bit of

point it may at this point an address

AD6 AD4AD5 AD3 AD2 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6

SCCLK

SCDIN

INTREQ

SPI Write Functional Timing

SPI Read Functional Timing

CS

AD6 AD4AD5 AD3 AD2 AD1 AD0 R/W

SCCLK

SCDIN

CS

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6SCDOUT

Figure 19. SPI Timing

Notes: 1. INTREQ is guaranteed to stay low until the rising edge of SCCLK for the second the last byte to be transferred out of the CS4923/4/5/6/7/8/9

2. INTREQ is guaranteed to stay high until the next rising edge of SCCLK at which go low again if there is new data to be read. The condition of INTREQ going low should be treated as a new read condition and a new start condition followed by byte should be sent

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6.4 I2C Serial Host Interface

For I2C communications the CS4923/4/5/6/7/8/9always acts as a slave. Serial I2C communicationwith the CS4923/4/5/6/7/8/9 is accomplished with3 communication lines: SCCLK, SCDIO andINTREQ. Table 8 shows the mnemonic, pin name,and pin number of each signal on theCS4923/4/5/6/7/8/9. SCCLK is an input to theCS492X that clocks data in and out of the device onits rising edge. It should be noted that the timingspecifications for SCCLK are more stringent thancertain I2C requirements so care should be takenthat the rise and fall specifications for SCCLK aremet as stated in the timing portion of this data sheet.SCDIO is a bidirectional data line whose data mustbe valid on the rising edge of SCCLK. INTREQ isan open drain, active-low request signal that isdriven low by the CS492X when there is data to beread out.

6.4.1 I2C Write

When writing to the device in I2C, the sameprotocol can be used for sending a byte, a word oran entire download image as long as transfers occuron byte boundaries. Figure 20 illustrates therelative timing necessary for a three byte transfer tothe CS492X. The host initiates a transfer with anI2C start condition followed by a 7-bit address andthe read/write bit set low to indicate a write. Thestart condition is defined as the SCDIO falling withSCCLK held high. The CS492X internal 7-bitaddress is initially assigned to 000 0000b followinga reset. The 7-bit address sent to the CS492X mustmatch its internal address or the incoming data willbe ignored. Address checking can be disabled or

the actual address can be changed if desired.Address checking configuration is documented inthe hardware configuration section of theCS4923/4/5/6/7/8/9 Hardware User’s guide. Aftthe address byte the host should then clock acknowledge (ACK) from the part. During a write,an ACK is defined as SCDIO being driven low bthe CS492X for one SCCLK period after each by

Data should be shifted into the CS492X mosignificant byte first with data being valid at the risinedge of SCCLK. The host should then clock out tacknowledge (ACK bit) bit from the CS492X. Afterthe last byte to be sent is acknowledged, the hshould send an I2C stop condition, which is defined athe rising edge of SCDIO while SCCLK is held hig

If the CS492X fails to acknowledge a byte, the hoshould re-transmit the same byte. If the CS492does not acknowledge back to back bytes, then host should reset the part.

6.4.2 I2C Read

The CS4923/4/5/6/7/8/9 will always indicate that has data to be read by asserting the INTREQ linelow. The host must recognize the request and staread transaction with the CS492X. The samprotocol will be used whether reading a byte multiple bytes. Figure 20 also illustrates the relatitiming of a three byte I2C read.

The host initiates a read with an I2C start conditionfollowed by a 7-bit address and the read/write bit high for a read. The start condition is defined as SCDIO falling with SCCLK held high. The CS492Xinternal 7-bit address is initially assigned to 000000b following a reset. The 7-bit address sent to CS492X must match its internal address or tincoming data will be ignored. Address checkincan be disabled or the actual address can be chaif desired. Address checking configuration documented in the hardware configuration sectiof the CS4923/4/5/6/7/8/9 Hardware User’s guid

Pin Name Pin Description Pin NumberSCCLK Serial Control Clock 7SCDIO Serial Data Input and

Output19

INTREQ Interrupt Request 20

Table 8. I2C Serial Mode Pin Assignments

DS262F2 39

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4923/4/5/6/7/8/9

40D

S262F

2

D4 D3 D2 D1 ACKD0

I2C Stop

D5 D4 D3 D2 D1 NACKD0

I2C Stop

Note 3Note 4

Note 5

riven by the

last byte to

f the read

CK/NACK of INTREQ condition

AD6 AD4AD5 AD3 AD2 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 ACKD0ACK D7 D6 D5 D4 D3 D2 D1 ACKD0 D7 D6 D5

I2C Start

SCCLK

SCDIO

AD6 AD4AD5 AD3 AD2 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 ACKD0ACK D7 D6 D5 D4 D3 D2 D1 ACKD0 D7 D6

I2C Start

SCCLK

SCDIO

INTREQ

Note 1 Note 2

I2C Write Functional Timing

I2C Read Functional Timing

Figure 20. I2C Timing

Notes: 1. The ACK for the address byte is driven by the CS4923/4/5/6/7/8/9.

2. The ACKs for the data bytes being read from the CS4923/4/5/6/7/8/9 should be dhost.

3. INTREQ is guaranteed to stay low until the rising edge of SCCLK for last bit of thebe transferred out of the CS4923/4/5/6/7/8/9

4. A NOACK should be sent by the host after the last byte read to indicate the end ocycle.

5. INTREQ is guaranteed to stay high until the next rising edge of SCCLK (for the Abit) at which point it may go low again if there is new data to be read. The conditiongoing low at this point should be treated as a new read condition and a new startfollowed by an address byte should be sent.

CS4923/4/5/6/7/8/9

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Following the address byte the host must clock outan acknowledge from the part.

After the address byte, the host should clock out datafrom the device one byte at a time until INTREQ isno longer low. The host shifts data using the risingedge of SCCLK. The data is valid on the rising edgeof SCCLK and transitions on the falling edge. Aftereach byte the host must send an acknowledge (ACK)to the CS492X. While reading from the CS492X, anacknowledge is defined as SCDIO being driven lowby the host for one SCCLK period after each byte. InI2C mode, the INTREQ pin is deassertedimmediately following the rising edge of the lastdata bit of the current byte being transferred if thereis no more data to be read. The INTREQ pin isguaranteed to stay deasserted (high) until the risingedge of SCCLK for the acknowledge bit.

For a more thorough look at I2C communicationand critical additional information on INTREQbehavior reference the CS4923/4/5/6/7/8/9Hardware User’s Guide.

6.5 External Memory

If using one of the serial modes, i.e. SPI or I2C, thesystem designer has the option of using externalmemory. The external memory interface is notcompatible with the parallel modes since there areshared pins that are needed by each mode. If usingthe CS4926 or CS4928 for DTS decode, externalmemory is required for external DTS tables.

The external memory interface was designedprimarily for two purposes: 1) Autoboot and/or 2)real time external data access. The hardwareimplementation for either mode can be the same butthe ROM access time requirements may differ. TheCS4923/4/5/6/7/8/9 Hardware User’s Guide shouldbe referenced for more information includingmemory paging options to support both autoboot andreal time access as well as ROM speed requirements.

The external memory interface is implemented the CS4923/4/5/6/7/8/9 with the following signalsEMAD[7:0], EXTMEM and EMOE. Table 9 showsthe pin name, pin description and pin number of easignal on the CS4923/4/5/6/7/8/9. EMAD[7:0] servas a multiplexed address and data bus. EMOE is anactive-low external-memory data output enable well as the address latch strobe. EXTMEM serves asthe active low chip select output. Figure 21 illustratone possible external memory architecture for tCS4923/4/5/6/7/8/9. Figure 22 shows the functiontiming of a run-time memory access .

The external memory address is capable of addressingbetween 64 kilobytes and 16 megabytes through a 16to 24 bit addressing scheme. The address comes fromthe DSP writing two or three initial bytes of addressconsecutively on EMAD[7:0]. Each byte of address isexternally latched with the rising edge of EMOE whileEXTMEM is high. After the 2 or 3-byte address islatched externally, the CS4923/4/5/6/7/8/9 then drivesEXTMEM and EMOE low simultaneously to selectthe external memory. During this time the data is readby the CS492X.

Pin Name Pin DescriptionPin

Number/EMOE * External Memory Output

Enable & Address Latch Strobe

5

/EMWR * External Memory Write Strobe

4

/EXTMEM External Memory Select 21EMAD7 Address and Data Bit 7 8EMAD6 Address and Data Bit 6 9EMAD5 Address and Data Bit 5 10EMAD4 Address and Data Bit 4 11EMAD3 Address and Data Bit 3 14EMAD2 Address and Data Bit 2 15EMAD1 Address and Data Bit 1 16EMAD0 Address and Data Bit 0 17

* - These pins must be configured appropriately to select aserial host communication mode for the CS4923/4/5/6/7/8/9at the rising edge of RESET

Table 9. Memory Interface Pins

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CS4923/4/5/6/7/8/9

64K X 8R O M

ADDR[15:8]

ADDR[7:0]

8 BIT'574D F F

D Q

8 BIT'574D F F

D Q

EMAD[7:0] DATA[7:0]

O EE M O E

E X T M E M C S

E M W R

Only one of R1 and R2 shou ld be stuffed.Only one of R3 and R4 shou ld be stuffed.The state of EMOE and EMWR at therising edge of RESET will determine theserial mode that the part comes up inwhile using exter nal memory. Please seesection 2, Serial Communication formore details.

CS4923/4/5/6/7/8/9

ADDR[7:0]

ADDR[15:8]

8

3.3V 3.3V

3.3V

3.3V

R1 R3

R2 R4

Figure 21. External Memory Interface

EXTMEM

EMOE

EMAD7:0 MA15:8 MA7:0 Data7:0

Figure 22. Run-Time Memory Access

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CS4923/4/5/6/7/8/9

Although the memory can use more address bits,typically only 16 bits of address space are used. Forthis reason the memory example shownincorporates a 2 latch memory architecture.

The two latch external memory architecture isrequired for the CS4926 or CS4928 when usingDTS. A three latch architecture can not be usedwith the CS4926 or CS4928 running DTS since therun time memory access uses only 2 address cycles.

6.5.1 External Memory and Autoboot

To configure the CS4923/4/5/6/7/8/9 toautomatically load its code from external memory,the ABOOT signal should be driven low at therising edge of RESET. Once again this mode canonly be chosen if either SPI or I2C serialcommunication is being used. In serial control portmode, holding the ABOOT pin low as the CS492Xleaves the reset state enables an automatic boot.

ABOOT can be released following the rising edgeof RESET. During the automatic boot cycle, theserial control port should remain idle. Figure 23shows an autoboot functional timing example.

The autoboot cycle actually is a 24 bit, or threeaddress byte cycle. It should be noted that forautoboot, the most significant byte is always zero.For this reason a two latch external memoryconfiguration can be used for autoboot. The higherorder address byte simply shifts out of the memorylatch and is discarded. If desired, a three latchinterface could also be used with theCS4923/4/5/7/9 but it is not necessary.

For more information about autoboot and for athorough description of different external memoryarchitectures, reference the CS4923/4/5/6/7/8/9Hardware User’s Guide.

RESET

ABOOT

EXTMEM

EMOE

EMWR

EMAD7:0 MA23:16 MA15:8 MA7:0 Data7:0

Figure 23. Autoboot Timing Diagram

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CS4923/4/5/6/7/8/9

st

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ofperhilerenst

le,ich

7. DIGITAL INPUT & OUTPUT

The CS4923/4/5/6/7/8/9 supports a wide variety ofdata input and output mechanisms through variousinput and output ports. Hardware availability isentirely dependent on whether the softwareapplication code being used supports the requiredmode. This data sheet presents most of the modesavailable with the CS4923/4/5/6/7/8/9 hardware.This does not mean that all of the modes areavailable with any particular piece of applicationcode. Both the CS4923/4/5/6/7/8/9 HardwareUser’s Guide and the application code user’s guidefor the particular code being used should bereferenced to determine if a particular mode issupported.

7.1 Digital Audio Formats

This subsection will describe some common audioformats that the CS4923/4/5/6/7/8/9 supports. Itshould be noted that the input ports use up to 24-bitPCM resolution and 16-bit compressed data wordlengths. The output port of the CS492X providesup to 20-bit PCM resolution.

I2S: Figure 24 shows the I2S format. For I2S, data ispresented most significant bit first, one SCLKdelay after the transition of LRCLK and is valid onthe rising edge of SCLK. For the I2S format, the leftsubframe is presented when LRCLK is low and theright subframe is presented when LRCLK is high.SCLK is required to run at a frequency of 48Fs orgreater on the input ports.

Left Justified: Figure 25 shows the left justifiedformat with a rising edge SCCLK. Data is

presented most significant bit first on the firSCLK after an LRCLK transition and is valid onthe rising edge of SCLK. For the left justifieformat, the left subframe is presented whLRCLK is high and the right subframe is presentwhen LRCLK is low. The left justified format canalso be programmed for data to be valid on tfalling edge of SCLK. SCLK is required to run at frequency of 48Fs or greater on the input ports.

Right Justified: Figure 26 shows the right justifiedformat. The right justified format is similar to thleft justified format except the least significant bis right justified to be valid on the last transition oSCLK before an LRCLK transition. Data is stilpresented most significant bit first. For the rigjustified format, the left subframe is presentewhen LRCLK is high and the right subframe presented when LRCLK is low. The right justifieformat can also be programmed for data being vaon the falling edge of SCLK. SCLK is required trun at a frequency of 48Fs or greater on the inpports.

Multi-Channel: Figure 27 shows the multi-channel format. In this format up to 6 channels audio are presented on one data line with 20 bits channel. Channels 0, 2, and 4 are presented wthe LR-CLK is high and channels 1, 3, 5 apresented while the LRCLK is low. Data is valid othe rising edge of SCLK and is presented mosignificant bit first.

Because each of the ports is fully configurabthere may be modes that can be supported whare not presented.

44 DS262F2

CS4923/4/5/6/7/8/9

LRCK

SCLK

SDATA MSB LSB

Left Right

MSB LSB

Figure 24. I2S Format

LRCK

SCLK

SDATA MSB LSB

Left Right

MSB LSB MSB

Figure 25. Left Justified Format

MSB LSBLSB MSB LSB

Left RightLRCLK

SCLK

SDATA

Figure 26. Right Justified

LRCLK

SCLK

SDATA MSB LSB

M ClocksPer Channel

MSB LSB

M ClocksPer Channel

M ClocksPer Channel

MSB LSB

M ClocksPer Channel

MSB LSB

M ClocksPer Channel

MSB LSB

M ClocksPer Channel

MSB LSB MSB

Figure 27. Multi-Channel Format (M == 20)

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CS4923/4/5/6/7/8/9

7.2 Digital Audio Input Port

The digital audio input port, or DAI, is used forboth compressed and PCM digital audio data input.In addition this port supports a special clockingmode in which a clock can be input to directly drivethe internal 33 bit counter. Table 10 shows the pinnames, mnemonics and pin numbers associatedwith the DAI.

The DAI can be programmed to support I2S, leftjustified and right justified data input. In additionthe DAI can be programmed for slave clocks,where LRCLKN1 and SCLKN1 are inputs, ormaster clocks, where LRCLKN1 and SCLKN1 areoutputs. In order for clocks to be master, theinternal PLL must be used.

STCCLK2 can also be programmed to drive theinternal 33 bit counter. This counter wouldtypically be driven by a 90kHz clock. The internalcounter is used by certain application code foraudio/video synchronization purposes.

7.3 Compressed Data Input Port

The compressed data input port, or CDI, can beused for both compressed and PCM data input.Table 11 shows the mnemonic, pin name and pinnumber of the pins associated with the CDI port onthe CS4923/4/5/6/7/8/9.

The CDI can be configured to support I2S, leftjustified and right justified formats. The CDI canalso be programmed for slave clocks, whereLRCLKN2 and SCLKN2 are inputs, or masterclocks, where LRCLKN2 and SCLKN2 areoutputs. In order for clocks to be mastered, theinternal PLL must be used.

In addition the CDI can be configured for burstycompressed data input. Bursty audio delivery is aspecial format in which only clock (CMPCLK) anddata (CMPDAT) are used to deliver compresseddata to the CS4923/4/5/6/7/8/9 (i.e. no frame clockor LRCLK). A third line, CMPREQ, is used torequest more data from the host. It is an indicatorthat the CS492X internal FIFO is low on data andcan accept another burst. Typically this mode isused for compressed data delivery whereasynchronous data transfer occurs in the system,i.e. in a system such as a set-top box or HDTV.PCM data can not be presented in this mode sincedata is interpreted as a continuous stream with noword boundaries.

7.4 Parallel Digital Audio Data Input

If using the Intel or Motorola Parallel host interfacemode, the system designer can also choose todeliver data through the byte wide parallel port.The compressed data input register receives bytesof data when the host interface writes to address11b (A1 and A0 are both high). The host interfaceport also utilizes the CMPREQ pin and the MFBand MFC flags in the CONTROL register, whichare configurable to supply a data request flag atdifferent input buffer thresholds. CMPREQ acts asan almost full flag. The CS4923/4/5/6/7/8/9 cansafely receive different size blocks of datadepending on the level of the input bufferthreshold. The threshold level is programmable andthe default level may differ between applications.This mode reduces the polling burden associatedwith hand-feeding the compressed data.

Pin Name Pin Description Pin NumberSDATAN1 Serial Data In 22SCLKN1 Serial Bit Clock 25LRCLKN1 Frame Clock 26

Table 10. Digital Audio Input Port

Pin Name Pin Description Pin NumberSDATAN2CMPDATA

Serial Data InCompressed Data In

27

SCLKN2CMPCLK

Serial Bit Clock 28

LRCLKN2CMPREQ

Frame ClockData Request Out

29

Table 11. Compressed Data Input Port

46 DS262F2

CS4923/4/5/6/7/8/9

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In parallel host mode, the CS4923/4/5/6/7/8/9 canaccept PCM data written through the byte-widehost interface to address 10b (A1 high, A0 low). Inthis mode, there is a close connection between theCS4923/4/5/6/7/8/9 application code and the hostprocessor that is delivering the PCM data. ThePCMRST bit of the CONTROL register providesabsolute software/hardware synchronization byinitializing the input channel to uniquely recognizethe first write to the byte-wide PCMDATA port.Toggling PCMRST high and low informs the DSPthat the next sample read from the PCMDATA portis the first sample of the left channel. In thisfashion, the CS492X can translate successive bytewrites into a variable number of channels with avariable PCM sample size. In the most simple case,the CS492X can receive stereo 8-bit PCM one byteat a time with the internal DSP assigning the first8-bit write (after PCMRST) to the left channel andthe second 8-bit write to the right channel. For16-bit PCM, it assigns the first two 8-bit writes(after PCMRST) to the left channel and the nexttwo writes to the right channel.

7.5 Digital Audio Output Port

The Digital Audio Output port, or DAO, is the portused for digital output from the DSP. Table 12shows the signals associated with the DAO. Asthere are many modes that are firmwareconfigurable on the DAO, please consult theHardware User’s Guide and the application codeuser’s guides to determine which modes aresupported by the download code being used.

MCLK is the master clock and is firmwareconfigurable to be either an input or an output.MCLK is to be used as an output, the internal PLmust be used. As an output MCLK can bconfigured to provide a 128Fs, 256Fs or 512clock, where Fs is the output sample rate.

SCLK is the bit clock used to clock data out oAUDATA0, AUDATA1 and AUDATA2. LRCLKis the data framing clock whose frequency typically equal to the sampling frequency. BotLRCLK and SCLK can be configured as eitheinputs (Slave mode) or outputs (Master modeWhen LRCLK and SCLK are configured as inputMCLK is a don’t care as an input. When LRCLKand SCLK are configured as outputs, they aderived from MCLK. Whether MCLK isconfigured as an input or an output, an interndivider from the MCLK signal is used to producLRCLK and SCLK. The ratios shown in table 1give the possible SCLK values for different MCLKfrequencies (all values in terms of the samplinfrequency, Fs).

AUDAT0 is configurable to provide six, four, otwo channels. AUDAT1 and AUDAT2 can bothoutput two channels of data. Typically all threAUDAT outputs are used in left justified, I2S oright justified modes. In this way all six channels surround (Left, Center, Right, Left Surround, RigSurround and Subwoofer) are provideAlternatively the multi-channel mode can bconfigured to provide single data line multchannel support. Please consult the HardwUser’s Guide and the application code use

Pin Name Pin Description Pin NumberAUDAT2 Serial Data In 39AUDAT1 Serial Data In 40AUDAT0 Serial Data In 41LRCLK Frame Clock 42SCLK Serial Bit Clock 43MCLK Master Clock 44XMT958 IEC60958 Transmitter 3

Table 12. Digital Audio Output Port

MCLK(Fs)

SCLK (Fs)32 48 64 128 256 512

128 X X384** X X X256 X X X X512 X X X X X

** For MCLK as an input only

Table 13. MCLK/SCLK Master Mode Ratios

DS262F2 47

CS4923/4/5/6/7/8/9

anised.

guides to determine which modes are supported bythe download code being used.

Serial digital audio data bit placement and samplealignment is fully configurable in theCS4923/4/5/6/7/8/9 including left justified, rightjustified, delay bits or no delay bits, variablesample word sizes, variable output channel count,and programmable output channel pin assignmentsand clock edge polarity to integrate with mostdigital audio interfaces. If a mode is needed whichis not supported, please consult your CrystalRepresentative as to its availability.

7.5.1 IEC60958 Output

The XMT958 output provides a CMOS level biphase encoded output. The XMT958 function canbe internally clocked from the PLL or from anMCLK input if MCLK is 256Fs or 512Fs. Allchannel status information can be used when usingsoftware which supports this functionality. Thisoutput can be used for either 2 channel PCM outputor compressed data output in accordance withIEC61937. To be fully IEC60958 compliant thisoutput would need to be buffered through anRS422 device or an optocoupler as its outputs areonly CMOS. Please consult theCS4923/4/5/6/7/8/9 Hardware User’s Guide andapplication code user’s guide to determine if thpin is supported by the download code being us

48 DS262F2

CS4923/4/5/6/7/8/9

D of

8. PIN DESCRIPTIONS

VA—Analog Positive Supply: Pin 34Analog positive supply for clock generator. Nominally +3.3 V.

AGND—Analog Supply Ground: Pin 35Analog ground for clock generator PLL.

VD1, VD2, VD3—Digital Positive Supply: Pins 1, 12, 23Digital positive supplies. Nominally +3.3 V.

DGND1, DGND2, DGND3—Digital Supply Ground: Pins 2, 13, 24Digital ground.

FILT1—Phase-Locked Loop Filter: Pin 33Connects to an external filter for the on-chip phase-locked loop. This pin does not meet CirrusLogic’s ESD tolerance of 2000 V using the human body model. This pin will tolerate ES1000 V using the human body model.

7891011121314151617

3938373635343332313029

18 19 20 21 22 23 24 25 26 27 28

6 5 4 3 2 1 44 43 42 41 40

CS4923-CL44-pin PLCC

Top View

VD2

DATA4,EMAD4,GPIO4

VA

DATA5,EMAD5,GPIO5

DATA6,EMAD6,GPIO6

DATA7,EMAD7,GPIO7

A0, SCCLK

A1, SCDIN

RD,R/W,EMOE,GPIO11

WR,DS,EMWR,GPIO10

XMT958

DGND1

VD1

SDATAN1

EXTMEM, GPIO8

ABOOT, INTREQ

SCDIO, SCDOUT,PSEL,GPIO9

CS

DATA0,EMAD0,GPIO0

DATA1,EMAD1,GPIO1

DATA2,EMAD2,GPIO2

DATA3,EMAD3,GPIO3

DGND2

RESET

DD

DC

AUDATA2

AUDATA1

AUDATA0

LRCLK

SCLK

MCLK

VD3

DGND3

SCLKN1, STCCLK2

LRCLKN1

CMPDAT, SDATAN2

CMPCLK, SCLKN2

CMPREQ, LRCLKN2

CLKIN

CLKSEL

FILT2

FILT1

AGND

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D of

FILT2—Phase Locked Loop Filter: Pin 32Connects to an external filter for the on-chip phase-locked loop. This pin does not meet CirrusLogic’s ESD tolerance of 2000 V using the human body model. This pin will tolerate ES1000 V using the human body model.

CLKIN—Master Clock Input: Pin 30 CS4923/4/5/6/7/8/9 clock input. When in internal clock mode (CLKSEL == DGND), this inputis connected to the internal PLL from which all internal clocks are derived. When in externalclock mode (CLKSEL == VD), this input is connected to the DSP clock. INPUT

CLKSEL—DSP Clock Select: Pin 31This pin selects the clock mode of the CS4923/4/5/6/7/8/9. When CLKSEL is low, CLKIN isconnected to the internal PLL from which all internal clocks are derived. When CLKSEL ishigh CLKIN is connected to the DSP clock. INPUT

DATA7, EMAD7, GPIO7—Pin 8DATA6, EMAD6, GPIO6—Pin 9DATA5, EMAD5, GPIO5—Pin 10DATA4, EMAD4, GPIO4—Pin 11DATA3, EMAD3, GPIO3—Pin 14DATA2, EMAD2, GPIO2—Pin 15DATA1, EMAD1, GPIO1—Pin 16DATA0, EMAD0, GPIO0—Pin 17

In parallel host mode, these pins provide a bidirectional data bus. If a serial host mode isselected, these pins can provide a multiplexed address and data bus for connecting an 8-bitexternal memory. Otherwise, in serial host mode, these pins can act as general-purpose input oroutput pins that can be individually configured and controlled by the DSP. BIDIRECTIONAL - Default: INPUT

A0, SCCLK—Host Parallel Address Bit Zero or Serial Control Port Clock: Pin 7In parallel host mode, this pin serves as one of two address input pins used to select one of fourparallel registers. In serial host mode, this pin serves as the serial control clock signal,specifically as the SPI clock input or the I2C clock input. INPUT

A1, SCDIN—Host Parallel Address Bit One or SPI Serial Control Data Input: Pin 6In parallel host mode, this pin serves as one of two address input pins used to select one of fourparallel registers. In SPI serial host mode, this pin serves as the data input. INPUT

RD, R/W, EMOE, GPIO11—Host Parallel Output Enable or Host Parallel R/W or External Memory Output Enable or General Purpose Input & Output Number 11: Pin 5

In Intel parallel host mode, this pin serves as the active-low data bus enable input. In Motorolaparallel host mode, this pin serves as the read-high/write-low control input signal. In serial hostmode, this pin can serve as the external memory active-low data-enable output signal. Also inserial host mode, this pin can serve as a general purpose input or output bit. BIDIRECTIONAL - Default: INPUT

50 DS262F2

CS4923/4/5/6/7/8/9

WR, DS, EMWR, GPIO10—Host Write Strobe or Host Data Strobe or External Memory Write Enable or General Purpose Input & Output Number 10: Pin 4

In Intel parallel host mode, this pin serves as the active-low data-write-input strobe. InMotorola parallel host mode, this pin serves as the active-low data-strobe-input signal. In serialhost mode, this pin can serve as the external-memory active-low write-enable output signal.Also in serial host mode, this pin can serve as a general purpose input or output bit.BIDIRECTIONAL - Default: INPUT

CS—Host Parallel Chip Select, Host Serial SPI Chip Select: Pin 18In parallel host mode, this pin serves as the active-low chip-select input signal. In serial hostSPI mode, this pin is used as the active-low chip-select input signal. INPUT

RESET—Master Reset Input: Pin 36Asynchronous active-low master reset input. Reset should be low at power-up to initialize theCS4923/4/5/6/7/8/9 and to guarantee that the device is not active during initial power-onstabilization periods. At the rising edge of reset the host interface mode is selected contingenton the state of the RD, WR and PSEL pins. Additionally, an autoboot sequence can be initiatedif a serial control mode is selected and ABOOT is held low. If reset is low all bidirectional pinsare high impedance inputs. INPUT

SCDIO, SCDOUT, PSEL, GPIO9—Serial Control Port Data Input and Output, Parallel Port Type Select: Pin 19

In I2C mode, this pin serves as the open-drain bidirectional data pin. In SPI mode this pinserves as the data output pin. In parallel host mode, this pin is sampled at the rising edge ofRESET to configure the parallel host mode as an Intel type bus or as a Motorola type bus. Inparallel host mode, after the bus mode has been selected, the pin can function as a general-purpose input or output pin. BIDIRECTIONAL - Default: INPUT In I2C mode this pin is an OPEN DRAIN I/O and requires a 4.7k Pull-Up

EXTMEM , GPIO8—External Memory Chip Select or General Purpose Input & Output Number 8: Pin 21

In serial control port mode, this pin can serve as an output to provide the chip-select for anexternal byte-wide ROM. In parallel and serial host mode, this pin can also function as ageneral-purpose input or output pin. BIDIRECTIONAL - Default: INPUT

INTREQ , ABOOT—Control Port Interrupt Request, Automatic Boot Enable: Pin 20Open-drain interrupt-request output. This pin is driven low to indicate that the DSP hasoutgoing control data and should be serviced by the host. Also in serial host mode, this signalinitiates an automatic boot cycle from external memory if it is held low through the rising edgeof reset. OPEN DRAIN I/O - Requires 4.7k Ohm Pull-Up

AUDATA2—Digital Audio Output 2: Pin 39PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCMoutput defaults to DGND as output until enabled by the DSP software. OUTPUT

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CS4923/4/5/6/7/8/9

AUDATA1—Digital Audio Output 1: Pin 40PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCMoutput defaults to DGND as output until enabled by the DSP software. OUTPUT

AUDATA0—Digital Audio Output 0: Pin 41PCM multi-format digital-audio data output, capable of two-, four-, or six-channel 20-bitoutput. This PCM output defaults to DGND as output until enabled by the DSP software.OUTPUT

MCLK—Audio Master Clock: Pin 44Bidirectional master audio clock. MCLK can be an output from the CS4923/4/5/6/7/8/9 thatprovides an oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs. MCLK can bean input at 128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to derive SCLK and LRCLKwhen SCLK and LRCLK are driven by the CS492X. BIDIRECTIONAL - Default: INPUT

SCLK—Audio Output Bit Clock: Pin 43Bidirectional digital-audio output bit clock. SCLK can be an output that is derived from MCLKto provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs, depending on the MCLK rate and thedigital-output configuration. SCLK can also be an input and must be at least 48Fs or greater.As an input, SCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT

LRCLK—Audio Output Sample Rate Clock: Pin 42Bidirectional digital-audio output-sample-rate clock. LRCLK can be an output that is dividedfrom MCLK to provide the output sample rate depending on the output configuration. LRCLKcan also be an input. As an input LRCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT

XMT958—SPDIF Transmitter Output: Pin 3CMOS level output that contains a biphase-encoded clock for synchronously providing twochannels of PCM digital audio or a IEC61937 compressed-data interface or both. This outputtypically connects to the input of an RS-422 transmitter or to the input of an optical transmitter.OUTPUT

SCLKN1, STCCLK2—PCM Audio Input Bit Clock: Pin 25Bidirectional digital-audio bit clock that is an output in master mode and an input in slavemode. In slave mode, SCLKN1 operates asynchronously from all other CS492X clocks. Inmaster mode, SCLKN1 is derived from the CS492X internal clock generator. In either masteror slave mode, the active edge of SCLKN1 can be programmed by the DSP. For applicationssupporting PES layer synchronization this pin can be used as STCCLK2, which provides a pathto the internal STC 33 bit counter. BIDIRECTIONAL - Default: INPUT

52 DS262F2

CS4923/4/5/6/7/8/9

LRCLKN1—PCM Audio Input Sample Rate Clock: Pin 26Bidirectional digital-audio frame clock that is an output in master mode and an input in slavemode. LRCLKN1 typically is run at the sampling frequency. In slave mode, LRCLKN1operates asynchronously from all other CS492X clocks. In master mode, LRCLKN1 is derivedfrom the CS492X internal clock generator. In either master or slave mode, the polarity ofLRCLKN1 for a particular subframe can be programmed by the DSP. BIDIRECTIONAL - Default: INPUT

SDATAN1—PCM Audio Data Input Number One: Pin 22Digital-audio data input that can accept from one to six channels of compressed or PCM data.SDATAN1 can be sampled with either edge of SCLKN1, depending on how SCLKN1 has beenconfigured. INPUT

CMPCLK, SCLKN2—PCM Audio Input Bit Clock: Pin 28Bidirectional digital-audio bit clock that is an output in master mode and an input in slavemode. In slave mode, SCLKN2 operates asynchronously from all other CS492X clocks. Inmaster mode, SCLKN2 is derived from the CS492X internal clock generator. In either masteror slave mode, the active edge of SCLKN2 can be programmed by the DSP. If the CDI isconfigured for bursty delivery, CMPCLK is an input used to sample CMPDAT.BIDIRECTIONAL - Default: INPUT

CMPREQ, LRCLKN2—PCM Audio Input Sample Rate Clock: Pin 29When the CDI is configured as a digital audio input, this pin serves as a bidirectional digital-audio frame clock that is an output in master mode and an input in slave mode. LRCLKN2typically is run at the sampling frequency. In slave mode, LRCLKN2 operates asynchronouslyfrom all other CS492X clocks. In master mode, LRCLKN2 is derived from the CS492Xinternal clock generator. In either master or slave mode, the polarity of LRCLKN2 for aparticular subframe can be programmed by the DSP. When the CDI is configured for burstydelivery, or parallel audio data delivery is being used, CMPREQ is an output which serves asan internal FIFO monitor. CMPREQ is an active low signal that indicates when another blockof data can be accepted. BIDIRECTIONAL - Default: INPUT

CMPDAT, SDATAN2—PCM Audio Data Input Number Two: Pin 27Digital-audio data input that can accept from one to six channels of compressed or PCM data.SDATAN2 can be sampled with either edge of SCLKN2, depending on how SCLKN2 has beenconfigured. Similarly CMPDAT is the compressed data input pin when the CDI is configuredfor bursty delivery. When in this mode, the CS4923/4/5/6/7/8/9 internal PLL is driven by theclock recovered from the incoming data stream. INPUT

DC—Reserved: Pin 38This pin is reserved and should be pulled up with an external 4.7k resistor.

DD—Reserved: Pin 37This pin is reserved and should be pulled up with an external 4.7k resistor.

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CS4923/4/5/6/7/8/9

9. PACKAGE DIMENSIONS

INCHES MILLIMETERSDIM MIN MAX MIN MAX

A 0.165 0.180 4.043 4.572A1 0.090 0.120 2.205 3.048B 0.013 0.021 0.319 0.533D 0.685 0.695 16.783 17.653D1 0.650 0.656 15.925 16.662D2 0.590 0.630 14.455 16.002E 0.685 0.695 16.783 17.653E1 0.650 0.656 15.925 16.662E2 0.590 0.630 14.455 16.002e 0.040 0.060 0.980 1.524

44L PLCC PACKAGE DRAWING

D1

D

E1 E D2/E2

B

e

A1

A

54 DS262F2

• Notes •

cs4923/4/5/6/7/8/9 multi-channel digital audio decodersalsa-project.org/~james/datasheets/ ·...

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