CS61C L27 Single-Cycle CPU Control (1) Garcia, Spring 2010 © UCB

inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures

Lecture 27 Single-cycle CPU Control

2010-04-02

Success! The large Hadron

collider @ CERN is finally able to get subatomic particles colliding.

No Higgs boson particle yet, but stay tuned. 16 years and 10 G$!

Lecturer SOE Dan Garcia

www.cs.berkeley.edu/~ddgarcia

www.nytimes.com/2010/03/31/science/31collider.html

CS61C L27 Single-Cycle CPU Control (2) Garcia, Spring 2010 © UCB

Review: A Single Cycle Datapath

32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Exten

der

3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWrzero

01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel instrfetchunitclk

• We have everything except control signals

CS61C L27 Single-Cycle CPU Control (3) Garcia, Spring 2010 © UCB

Recap: Meaning of the Control Signals• nPC_sel: “+4” 0 PC <– PC + 4

“br” 1 PC <– PC + 4 + {SignExt(Im16) , 00 }

• Later in lecture: higher-level connection between mux and branch condition

“n”=next

imm16

clk

PC

00

4nPC_sel

PC

Ext

Ad

derA

dder

Mu

x

Inst Address

0

1

CS61C L27 Single-Cycle CPU Control (4) Garcia, Spring 2010 © UCB

Recap: Meaning of the Control Signals• ExtOp: “zero”, “sign”

• ALUsrc: 0 regB; 1 immed

• ALUctr: “ADD”, “SUB”, “OR”

° MemWr: 1 write memory° MemtoReg: 0 ALU; 1 Mem° RegDst: 0 “rt”; 1 “rd”° RegWr: 1 write register

32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Exten

der 3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In

32

MemWr01

0

1

AL

U 0

1

WrEn Adr

DataMemory

5

CS61C L27 Single-Cycle CPU Control (5) Garcia, Spring 2010 © UCB

RTL: The Add Instruction

add rd, rs, rt•MEM[PC] Fetch the instruction

from memory•R[rd] = R[rs] + R[rt] The actual operation

•PC = PC + 4 Calculate the next instruction’s address

op rs rt rd shamt funct

061116212631

6 bits 6 bits5 bits5 bits5 bits5 bits

CS61C L27 Single-Cycle CPU Control (6) Garcia, Spring 2010 © UCB

Instruction Fetch Unit at the Beginning of Add• Fetch the instruction from Instruction memory: Instruction = MEM[PC]

• same for all instructions

imm16

clk

PC

00

4nPC_sel

PC

Ext

Ad

derA

dder

Mu

x

Inst Address

InstMemory Instruction<31:0>

CS61C L27 Single-Cycle CPU Control (7) Garcia, Spring 2010 © UCB

The Single Cycle Datapath during Add

R[rd] = R[rs] + R[rt]op rs rt rd shamt funct

061116212631

32

ALUctr=ADD

clk

busW

RegWr=1

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=1

Exten

der

3216imm16

ALUSrc=0ExtOp=x

MemtoReg=0

clk

Data In32

MemWr=0

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel=+4 instrfetchunitclk

CS61C L27 Single-Cycle CPU Control (8) Garcia, Spring 2010 © UCB

Instruction Fetch Unit at the End of Add• PC = PC + 4

• This is the same for all instructions except: Branch and Jump

imm16

clk

PC

00

4nPC_sel=+4

PC

Ext

Ad

derA

dder

Mu

x

Inst Address

InstMemory

CS61C L27 Single-Cycle CPU Control (10) Garcia, Spring 2010 © UCB

• R[rt] = R[rs] OR ZeroExt[Imm16]op rs rt immediate

016212631

Single Cycle Datapath during Or Immediate?

32

ALUctr=OR

clk

busW

RegWr=1

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=0

Exten

der3216

imm16

ALUSrc=1ExtOp=zero

MemtoReg=0

clk

Data In32

MemWr=0

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel=+4 instrfetchunitclk

CS61C L27 Single-Cycle CPU Control (12) Garcia, Spring 2010 © UCB

The Single Cycle Datapath during Load

• R[rt] = Data Memory {R[rs] + SignExt[imm16]}op rs rt immediate

016212631

32

ALUctr=ADD

clk

busW

RegWr=1

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=0

Exten

der3216

imm16

ALUSrc=1ExtOp=sign

MemtoReg=1

clk

Data In32

MemWr=0

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel=+4 instrfetchunitclk

CS61C L27 Single-Cycle CPU Control (14) Garcia, Spring 2010 © UCB

The Single Cycle Datapath during Store

• Data Memory {R[rs] + SignExt[imm16]} = R[rt]op rs rt immediate

016212631

32

ALUctr=ADD

clk

busW

RegWr=0

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=x

Exten

der3216

imm16

ALUSrc=1ExtOp=sign

MemtoReg=x

clk

Data In32

MemWr=1

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel=+4 instrfetchunitclk

CS61C L27 Single-Cycle CPU Control (16) Garcia, Spring 2010 © UCB

The Single Cycle Datapath during Branch

• if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0op rs rt immediate

016212631

32

ALUctr=SUB

clk

busW

RegWr=0

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=x

Exten

der3216

imm16

ALUSrc=0ExtOp=x

MemtoReg=x

clk

Data In32

MemWr=0

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel=br instrfetchunitclk

CS61C L27 Single-Cycle CPU Control (17) Garcia, Spring 2010 © UCB

Instruction Fetch Unit at the End of Branch• if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ;

else PC = PC + 4

op rs rt immediate

016212631

• What is encoding of nPC_sel?

• Direct MUX select?• Branch inst. / not branch

• Let’s pick 2nd option

nPC_sel zero? MUX0 x 01 0 01 1 1

Adr

InstMemory

nPC_selInstruction<31:0>

Zero

nPC_sel

Q: What logic gate?

imm16 clk

PC

00

4

PC

Ext

Ad

derA

dder

Mu

x

0

1

MUX ctrl

CS61C L27 Single-Cycle CPU Control (19) Garcia, Spring 2010 © UCB

Step 4: Given Datapath: RTL Control

ALUctrRegDst ALUSrcExtOp MemtoRegMemWr

Instruction<31:0>

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel

Adr

InstMemory

DATA PATH

Control

Op

<0:5>

Fun

RegWr

<26:31>

CS61C L27 Single-Cycle CPU Control (20) Garcia, Spring 2010 © UCB

A Summary of the Control Signals (1/2)inst Register Transfer

add R[rd] R[rs] + R[rt]; PC PC + 4

ALUsrc = RegB, ALUctr = “ADD”, RegDst = rd, RegWr, nPC_sel = “+4”

sub R[rd] R[rs] – R[rt]; PC PC + 4

ALUsrc = RegB, ALUctr = “SUB”, RegDst = rd, RegWr, nPC_sel = “+4”

ori R[rt] R[rs] + zero_ext(Imm16); PC PC + 4

ALUsrc = Im, Extop = “Z”,ALUctr = “OR”, RegDst = rt,RegWr, nPC_sel =“+4”

lw R[rt] MEM[ R[rs] + sign_ext(Imm16)]; PC PC + 4

ALUsrc = Im, Extop = “sn”, ALUctr = “ADD”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”

sw MEM[ R[rs] + sign_ext(Imm16)] R[rs]; PC PC + 4

ALUsrc = Im, Extop = “sn”, ALUctr = “ADD”, MemWr, nPC_sel = “+4”

beq if ( R[rs] == R[rt] ) then PC PC + sign_ext(Imm16)] || 00 else PC PC + 4

nPC_sel = “br”, ALUctr = “SUB”

CS61C L27 Single-Cycle CPU Control (21) Garcia, Spring 2010 © UCB

A Summary of the Control Signals (2/2)

add sub ori lw sw beq jump

RegDst

ALUSrc

MemtoReg

RegWrite

MemWrite

nPCsel

Jump

ExtOp

ALUctr<2:0>

1

0

0

1

0

0

0

x

Add

1

0

0

1

0

0

0

x

Subtract

0

1

0

1

0

0

0

0

Or

0

1

1

1

0

0

0

1

Add

x

1

x

0

1

0

0

1

Add

x

0

x

0

0

1

0

x

Subtract

x

x

x

0

0

?

1

x

x

op target address

op rs rt rd shamt funct

061116212631

op rs rt immediate

R-type

I-type

J-type

add, sub

ori, lw, sw, beq

jump

func

op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010Appendix A10 0000See 10 0010 We Don’t Care :-)

CS61C L27 Single-Cycle CPU Control (22) Garcia, Spring 2010 © UCB

Boolean Expressions for Controller

RegDst = add + subALUSrc = ori + lw + swMemtoReg = lwRegWrite = add + sub + ori + lw MemWrite = swnPCsel = beqJump = jump ExtOp = lw + swALUctr[0] = sub + beq (assume ALUctr is 00 ADD, 01: SUB, 10: OR)ALUctr[1] = or

where,

rtype = ~op5 ~op4 ~op3 ~op2 ~op1 ~op0, ori = ~op5 ~op4 op3 op2 ~op1 op0 lw = op5 ~op4 ~op3 ~op2 op1 op0 sw = op5 ~op4 op3 ~op2 op1 op0

beq = ~op5 ~op4 ~op3 op2 ~op1 ~op0 jump = ~op5 ~op4 ~op3 ~op2 op1 ~op0

add = rtype func5 ~func4 ~func3 ~func2 ~func1 ~func0

sub = rtype func5 ~func4 ~func3 ~func2 func1 ~func0

How do we implement this in

gates?

CS61C L27 Single-Cycle CPU Control (23) Garcia, Spring 2010 © UCB

Controller Implementation

add

sub

ori

lw

sw

beq

jump

RegDstALUSrcMemtoRegRegWriteMemWritenPCselJumpExtOpALUctr[0]ALUctr[1]

“AND” logic “OR” logic

opcode func

CS61C L27 Single-Cycle CPU Control (24) Garcia, Spring 2010 © UCB

Peer Instruction

1) MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ?

2) ALUctr=‘add’. Which 1 signal is different for all 3 of: ADD, LW, & SW? RegDst or ExtOp?

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

55 5

Rw Ra Rb32 32-bitRegisters

Rs

Rt

Rt

Rd

RegDst

Exten

der

Mu

x

Mux

3216imm16

ALUSrc

ExtOp

Mu

x

MemtoReg

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr

AL

U

InstructionFetch Unit

Clk

Zero

Instruction<31:0>

0

1

0

1

01

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel

12a) SRb) SEc) BRd) BE

CS61C L27 Single-Cycle CPU Control (25) Garcia, Spring 2010 © UCB

°5 steps to design a processor• 1. Analyze instruction set datapath requirements• 2. Select set of datapath components & establish clock

methodology• 3. Assemble datapath meeting the requirements• 4. Analyze implementation of each instruction to

determine setting of control points that effects the register transfer.

• 5. Assemble the control logic• Formulate Logic Equations• Design Circuits

Summary: Single-cycle Processor

Control

Datapath

Memory

ProcessorInput

Output

CS61C L27 Single-Cycle CPU Control (27) Garcia, Spring 2010 © UCB

32

ALUctr =

Clk

busW

RegWr =

3232

busA

32busB

55 5

Rw Ra Rb32 32-bitRegisters

Rs

Rt

Rt

RdRegDst =

Exten

der

Mu

x

Mux

3216imm16

ALUSrc =

ExtOp =

Mu

x

MemtoReg =

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr =A

LU

InstructionFetch Unit

Clk

Zero

Instruction<31:0>

0

1

0

1

01<

21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

• New PC = { PC[31..28], target address, 00 }

nPC_sel=

The Single Cycle Datapath during Jump

op target address02631

J-type jump25

Jump=

<0:25>

TA26

CS61C L27 Single-Cycle CPU Control (28) Garcia, Spring 2010 © UCB

The Single Cycle Datapath during Jump

32

ALUctr =x

Clk

busW

RegWr = 0

3232

busA

32busB

55 5

Rw Ra Rb32 32-bitRegisters

Rs

Rt

Rt

RdRegDst = x

Exten

der

Mu

x

Mux

3216imm16

ALUSrc = x

ExtOp = x

Mu

x

MemtoReg = x

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 0A

LU

InstructionFetch Unit

Clk

Zero

Instruction<31:0>

0

1

0

1

01<

21:25>

<16:20>

<11:15>

<0:15>

RdRsRt

• New PC = { PC[31..28], target address, 00 }

nPC_sel=?

Jump=1

Imm16

<0:25>

TA26

op target address02631

J-type jump25

CS61C L27 Single-Cycle CPU Control (29) Garcia, Spring 2010 © UCB

Instruction Fetch Unit at the End of Jump

Adr

InstMemory

Ad

derA

dder

PC

Clk

00Mu

x

4

nPC_sel

imm

16

Instruction<31:0>

0

1

Zero

nPC_MUX_sel

• New PC = { PC[31..28], target address, 00 }op target address

02631J-type jump

25

How do we modify this

to account for jumps?

Jump

CS61C L27 Single-Cycle CPU Control (30) Garcia, Spring 2010 © UCB

Instruction Fetch Unit at the End of Jump

Adr

InstMemory

Ad

derA

dder

PC

Clk00

Mu

x

4

nPC_sel

imm

16

Instruction<31:0>

0

1

Zero

nPC_MUX_sel

• New PC = { PC[31..28], target address, 00 }op target address

02631J-type jump

25

Mu

x1

0

Jump

TA

4 (MSBs)

00

Query• Can Zero still

get asserted?

• Does nPC_sel need to be 0? • If not, what?

26