Copyright Cirrus Logic, Inc. 200(All Rights Reserved)

Cirrus Logic, Inc.P.O. Box 17847, Austin, Texas 78760(512) 445 7222 FAX: (512) 445 7581http://www.cirrus.com

AN831

1 JUN 01AN83REV3Application Note

CS8900A ETHERNET CONTROLLERTECHNICAL REFERENCE MANUAL

By Deva Bodas Revised by James Ayres

AN83TABLE OF CONTENTSSCHEMATIC CHECKLIST ...................................................................................................................................4SOFTWARE CHECKLIST ....................................................................................................................................5INTRODUCTION TO CS8900A TECHNICAL REFERENCE MANUAL ..............................................................6HARDWARE DESIGN..........................................................................................................................................7CS8900A: CONNECTING TO NON-ISA BUS SYSTEMS ...................................................................................7

The CS8900A Architecture.............................................................................................................................7ISA Bus ....................................................................................................................................................8CS8900A in I/O Mode ..............................................................................................................................8CS8900A in Memory Mode......................................................................................................................8DMA Interface of the CS8900A................................................................................................................8

Selection of I/O, Memory and DMA Modes ....................................................................................................9Design Example: CS8900A Interface to MC68302 ........................................................................................9

Address Generation .................................................................................................................................9Read and Write Signals .........................................................................................................................10SBHE Signal ..........................................................................................................................................10Other Control Signals.............................................................................................................................10Status Signals from CS8900A ...............................................................................................................11

Databus (SD[0:15]) Connection....................................................................................................................11Checklist for Signal Connections to the CS8900A .......................................................................................11EEPROM Optional........................................................................................................................................11Design Example: CS8900A Interface to Cirrus Logic CL-PS7111 ...............................................................12Design Example: CS8900A Interface to Hitachi SH3 ...................................................................................12Summary ......................................................................................................................................................12

ETHERNET HARDWARE DESIGN FOR EMBEDDED SYSTEMS AND MOTHERBOARDS ..........................15General Description ...............................................................................................................................15Board Design Considerations ................................................................................................................15

Crystal Oscillator .............................................................................................................................15ISA Bus Interface ............................................................................................................................15External Decode Logic ....................................................................................................................15EEPROM.........................................................................................................................................15LEDs................................................................................................................................................1810BASE-T Interface ........................................................................................................................1810BASE-2 and AUI Interfaces.........................................................................................................18

Logic Schematics...................................................................................................................................18 Component Placement and Signal Routing ........................................................................................20Bill of Material ........................................................................................................................................20

Contacting Cirrus Logic SupportFor a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:http://www.cirrus.com/corporate/contacts/

Crystal LAN, StreamTransfer, PacketPage, and SMART Analog are trademarks of Cirrus Logic.Ethernet is a registered trademark of Xerox Corp.. Artisoft and LANtastic are registered trademarks of Artisoft, Inc.. Banyan and VINES are registered trademarksof Banyan Systems.. Digital and PATHWORKS are registered trademarks of Digital Equipment Corporation.. Intel is a registered trademark of Intel Corporation..LAN Server and IBM are registered trademarks of International Business Machines Corp.. Microsoft, LAN Manager, Windows 95, Windows for Workgroups, andWindows NT are registered trademarks of Microsoft.. Novell and Netware are registered trademarks of Novell, Inc.. SCO is a registered trademark of SantaCruz Organization, Inc.. UNIX is a registered trademark of AT&T Technologies, Inc.Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the informationcontained in this document is accurate and reliable. However, the information is subject to change without notice and is provided AS IS without warranty ofany kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rightsof third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part ofthis publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, orotherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, nopart of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufactureor sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearingin this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-2 AN83REV3

marks and service marks can be found at http://www.cirrus.com.

AN83LOW COST ETHERNET COMBO CARD REFERENCE DESIGN: CRD8900 ..................................................21General Description ...............................................................................................................................21Board Design .........................................................................................................................................21

Crystal Oscillator .............................................................................................................................21ISA Bus Interface ............................................................................................................................21External Decode Logic ....................................................................................................................21EEPROM.........................................................................................................................................21Socket for Optional Boot PROM .....................................................................................................21LEDs ...............................................................................................................................................2610BASE-T Interface ........................................................................................................................26AUI Interface ...................................................................................................................................2610BASE-2 Interface ........................................................................................................................27

Logic Schematics...................................................................................................................................27Component Placement and Routing of Signals .....................................................................................27Bill of Material ........................................................................................................................................27

Addressing the CS8900A: I/O Mode, Memory Mode ...................................................................................27I/O Mode ................................................................................................................................................27Memory Mode........................................................................................................................................31

Lower Memory Mode ......................................................................................................................31Extended Memory Mode .................................................................................................................31

Layout Considerations for the CS8900A......................................................................................................35General Guidelines ................................................................................................................................35Power Supply Connections....................................................................................................................35

Two Layered Printed Circuit Board (PCB) ......................................................................................35Multi-layered Printed Circuit Board .................................................................................................35

Routing of the Digital Signals.................................................................................................................35Routing of the Analog Signals ...............................................................................................................35

RECOMMENDED MAGNETICS FOR THE CS8900A.......................................................................................44JUMPERLESS DESIGN.....................................................................................................................................45

Serial EEPROM............................................................................................................................................45Reset Configuration Block .....................................................................................................................45Driver Configuration Information............................................................................................................47Format of Driver Configuration Block.....................................................................................................47

IEEE Physical Address ...................................................................................................................49ISA Configuration Flags ..................................................................................................................49PacketPage Memory Base..............................................................................................................50Boot PROM Memory Base.............................................................................................................50Boot PROM Mask ..........................................................................................................................50Transmission Control ......................................................................................................................50Adapter Configuration Word............................................................................................................51EEPROM Revision..........................................................................................................................51Manufacturing Date.........................................................................................................................52IEEE Physical Address (Copy)........................................................................................................5216-bit Checksum .............................................................................................................................52EISA ID ...........................................................................................................................................52Serial Number .................................................................................................................................53Serial ID Checksum ........................................................................................................................53

Maintaining EEPROM Information.........................................................................................................54Embedded Designs ......................................................................................................................................54

BIOS-Based Design Considerations......................................................................................................54Driver Interface with BIOS-Based Configuration ...................................................................................54

OBTAINING IEEE ADDRESSES .......................................................................................................................55DEVICE DRIVERS AND SETUP/INSTALLATION SOFTWARE.......................................................................56

DOS Setup and Installation Utility ................................................................................................................56Installation Procedure ............................................................................................................................56

CONTACTING CUSTOMER SUPPORT AT CIRRUS .......................................................................................57Cirrus Web Site ............................................................................................................................................57AN83REV3 3

AN83SCHEMATIC CHECKLISTBefore getting into the meat of the technical refer-ence manual here is a schematic checklist. Its pre-sented here, at the beginning, to help the hardwaredesigner implement the design quickly and easily.

- No caps across the crystal. The CS8900A implements these internally.

- 4.99K 1% resistor between pin 93 and pin 94. A common mistake is the resistor is connected to Vcc instead of ground.

- RESET is active high, not active low.- Check addressing. - On non-ISA systems, if the processor is Big

Endian, it may be beneficial to byte swap the data lines to minimize byte swapping in software.

- SBHE (16 bit mode) -- must be low on IO or Mem address. And it must toggle at least once to put the CS8900 in 16 bit mode.

- IO and Memory Accesses: SBHE, AEN, etc. must be stable for 10ns (read) and 20ns (write) before access.

- IOCHRDY - Generally not connected in non-ISA bus.

- CHIPSEL (active low). Tie to ground if not using ELCS.

- Make sure interrupt line is active high. It is best to put a pull down (10K) on INT line since selected IRQ line is tristated during software initiated reset.

- ELCS should be pulled to ground or left floating if not used.

- EEDataIn should be pulled to ground if not used.- 10Base-T circuit -- no caps on TX lines between

isolation transformer and 10 Base-T connector. - 10Base-T circuit -- no center tap caps on

isolation transformer and 10 Base-T connector.

Good to have pads, dont populate except for EMI problems.

- Isolation transformer -- start with one that does not have a common mode choke. If there are EMI considerations, then use one with common mode choke. The pin outs are the same. For 3.3V operation, use a transformer with 1:2.5 turns ration on TX and 1:1 on RX like the Halo TG41-2006N.

- For EMI problems, 1) add choke, 2) add center tap caps on isolation transformer

- If using a shielded RJ45 connector, make sure the shield pins are connected to chassis ground.

- AEN connected to ground if not using DMA.- AEN can be used as an active low chip select if

not using DMA.- AUI Interface -- use a 1AMP fuse. MAU can use

.5amps even better use a thermistor ("poly switch"). Also, use a diode so cant back-drive from an externally powered MAU. Use a Halo TnT integrated module to simplify 10Base2 interface.

- TX series termination resistors are R: 24.3 Ohm 1% (8 or 8.2 Ohm 1% for 3.3V)

- RX shunt termination resistor is 100 Ohm - Put a 68pF shunt across TX on primary side

(560pF for 3.3V)- Dont use split analog/digital power and ground

planes.- Void ground/power plane from transformer to

RJ45- Put .1uF cap on each supply pin very close to

CS8900 The schematic checklist and the example connec-tion diagrams to the Hitachi SH3, Cirrus Logic CL-PS7211 and the Motorola MC68302 microproces-sors should make clear the necessary the hardwareconnections for a wide variety of situations.4 AN83REV3

AN83SOFTWARE CHECKLIST- When servicing the interrupt always read the

Interrupt Status Queue (ISQ) first. Process that individual event before reading the ISQ again.

- Having read an ISQ event indicating a valid recieve frame, never read the ISQ again before either 1) reading in the entire current receive frame or 2) issuing an explicit skip command. Either of these actions will correctly clear that frame from the CS8900As internal memory.

- Always continue reading and processing ISQ events until reading a 0x0000 from the ISQ.

- After a software or hardware reset, always wait until the SelfStatus register, bit 7 (INITD) is set before reading or writing any other registers.

- Allow only one transmit in progress at any given time. Since the chip dynamically allocates memory between transmit and recieve frames, it is possible to fill the internal buffers with transmit frames. This would prevent reception.

- Dont reinvent the wheel. Port one of the sample drivers, if there isnt a driver for your operating system. You can find sample drivers at http://www.cirrus.com/drivers/ethernet/. AN83REV3 5

AN83INTRODUCTION TO CS8900A TECHNICAL REFERENCE MANUALThis Technical Reference Manual provides the in-formation which will be helpful in designing aboard using the CS8900A, programming the asso-ciated EEPROM, and installing and running theCS8900A device drivers. It is expected that theuser of this technical reference manual will have ageneral knowledge of hardware design, Ethernet,the ISA bus, and networking software. Recom-mended sources of background information are:

ISA System Architecture by Shanley andAnderson, Mindshare Press, 1992, ISBN 1-881609-05-7Ethernet, Building a Communication Infra-structure, by Hegering and Lapple, Addison-Wesley, 1993, ISBN 0-201-62405-2Netware Training Guide: Networking Technol-ogies, by Debra Niedenmiller-Chaffis, NewRiders Publishing, ISBN 1-56205-363-9

As shown in the Figure 1, the CS8900A requires aminimum number of external components. TheEEPROM stores configuration information such asinterrupt number, DMA channel, I-O base address,memory base address, and IEEE Individual Ad-dress. The EEPROM can be eliminated on a PCmotherboard if that information in stored in the sys-tem CMOS. Note also that the Boot PROM is onlyneeded for diskless workstations that boot DOS atsystem power up, over the network. Also, the LEDsare optional.The hardware design considerations for both moth-erboards and adapter cards are discussed inHARDWARE DESIGN on page 7. The EE-PROM programming considerations are describedin JUMPERLESS DESIGN on page 45.Cirrus provides a complete set of device drivers, asdiscussed in DEVICE DRIVERS AND SET-UP/INSTALLATION SOFTWARE on page 56.The drivers reside between the networking operat-ing system (NOS) and the CS8900A. On theCS8900A side, the drivers understand how to pro-

Boundary

RAM

ISABusLogic

MemoryManager

Media AccessControl(MAC).

Ethernetprotocol

processing.

EEPROMControl

Encoder,Decoder

&PLL

10BASE-TRX Filters &

Receiver

10BASE-TTX Filters &Transmitter

AUITransmitter

AUICollision

AUIReceiver

Clock

PowerManageScanTest Logic

LEDControl

EEPROM:Stores Configuration

Information &IEEE Address

57pinsISA Bus

Boot PROM:Used to boot diskless

workstations.

AUITransformer(Attachment

UnitInterface)

10BASE-TTransformer6 AN83REV3

Figure 1. Hardware Application Summary

AN83gram and read the CS8900A control and status reg-isters, and how to transfer user data between theCS8900A and the PC main memory via the ISAbus. On the NOS side, the drivers provide the stan-dardized services and functions required by theNOS, and hide all details of the CS8900A hardwarefrom the NOS. The EEPROM device programs theCS8900A whenever the a hardware reset occurs,and call also store state/configuration informationfor the driver.Cirruss Software Driver () Distribu-tion Policy is as follows. The CS8900A developerkit contains a single-user copy of object code whichis available only for internal testing and evaluationpurposes. This object code may not be distributedwithout first signing a LICENSE FOR DISTRIBU-TION OF EXECUTABLE SOFTWARE, whichmay be obtained by contacting your sales represen-tative. The LICENSE FOR DISTRIBUTION OFEXECUTABLE SOFTWARE gives you unlimit-ed, royalty-free rights to distribute Cirrus-providedobject code.HARDWARE DESIGNThis section give design guidance for both embed-ded and adapter card designs, including recommen-dations for dealing with the upper ISA address lines(LA[20:23]), choosing transformers, and laying outthe board.

CS8900A: CONNECTING TO NON-ISA BUS SYSTEMSThe CS8900A includes a direct interface to the ISAbus. At the same time, the CS8900A offers a com-pact, efficient, and cost-effective, full-duplexEthernet solution for non-ISA architectures. Thepurpose of this section is to illustrate how to inter-face the CS8900A to non-Intel and non ISA sys-tems. Design examples include the MC68302,Cirrus Logic CL-PS7211 ARM and Hitachi SH3.

The CS8900A ArchitectureThe CS8900A is a highly integrated Ethernet con-troller chip. It includes the digital logic, RAM andanalog circuitry required for an Ethernet interface.This high level of integration allows a product de-signer to design an Ethernet interface in 1.5 squareinches of space on a printed circuit board. TheCS8900A has a powerful memory manager that dy-namically allocates the on-chip memory betweentransmit and receive functions. The on-chip mem-ory manager performs functions in hardware thatare many times done by software. This reducesloading on the CPU and on the bus connected to theCS8900A. In fact, for 10 Megabit Ethernet, theCS8900A is the highest throughput solution in themarket.The integration of the analog transmit waveformfiltering makes it easier to design a board that willpass EMC testing. When the analog filters are ex-ternal, the PCB traces have fast edge digital wave-forms coming out of the ICs 10BASE-Ttransmitter. The presence of high frequency energyin the fast edges causes major problem during EMCtests, such as FCC Part 15 class (B) or CISPR class(B). The 10BASE-T signals driven out of theCS8900A are internally filtered with a 5th orderButterworth filter and the signals lack fast edges.Lack of high frequency signals makes it straightforward to design a card that meets FCC class (B)or even CISPR class (B) requirements.

Applications

Operating System Softwaree.g., File Manager

Network Operating Systeme.g., Novell or Microsoft

CS8900 - specific device drivers:e.g., NDIS & ODI compatible drivers

CS8900 Registers & Memory EEPROM

Figure 2. Software Application SummaryAN83REV3 7

AN83ISA BusAn ISA bus is a simple, asynchronous bus that caneasily be made to interface to most synchronous orasynchronous buses. An ISA bus has separate ad-dress and data lines as well as separate control linesfor read and write. ISA supports IO address spaceof 64K bytes and Memory address space 32 Megabytes.

CS8900A in I/O ModeWhen the CS8900A is used in an IO mode, it re-sponds in the IO address space of the ISA. TheCS8900A responds to an IO access when

- Either of the bus IO command lines (IOR or IOW) is active,

- The address on bus signals SA[0:15] matches the address in the CS8900A IO base address register, and

- Bus signals AEN, REFRESH, TEST, SLEEP and RESET are inactive.

All other control signals are ignored for the IO op-eration.In an IO mode, the CS8900A uses 16 bytes of IOaddress space. The address map for this mode isdescribed in Table 4.5 in the CS8900A datasheet.

CS8900A in Memory ModeWhen the CS8900A is used in memory mode, theCS8900A responds in the memory address space ofthe ISA bus. The CS8900A responds to a memorymode access when

- The CHIPSEL pin is active,- Either of the bus memory command lines

(MEMR or MEMW) is active,- Both of the IO command lines (IOR and IOW)

are inactive,- the address on bus signals SA[0:19] matches

the address in the CS8900As Memory Base address register,

- MemoryE (Bit A) in the CS8900As BusCTL (Register 17) is active and,

- Bus signals AEN, REFRESH, TEST, SLEEP

In memory mode, all the internal registers of theCS8900A can be accessed directly via memoryreads/writes. Please refer to the CS8900Adatasheet for the memory address map.

DMA Interface of the CS8900AThe CS8900A can interface to an external 16-bitDMA channel for receive operations. A DMA-mode receive operation can be selected by settingeither RxDMAOnly (bit 9) or AutoRxDMA (bit10) in the CS8900As RxCFG (Register 3) register.The CS8900A will request services of an externalDMA after a receive frame is accepted by theCS8900A, completely received and stored in onchip RAM of the CS8900A. The CS8900A gener-ates a request for DMA access (DRQx) signal whenit has at least one receive frame that can be trans-ferred to the system memory. The external DMAchannel should assert DMACK signal when it isready to transfer data. The DMA controller gener-ates address for the system memory and asserts theAEN signal. When DMACK and AEN signals areasserted, the CS8900A provides 16 bits of framedata for every pulse of the IOR signal. Notice thatthe CS8900A ignores address on the SA addresslines for this operation. In this way the CS8900Asupports direct mode of operation of DMA. Indirect mode, the external DMA controller gener-ates addresses for the system RAM, and generatesthe appropriate control signals for the RAM and IOdevice. The data moves directly from the IO deviceto the RAM. In the case of the CS8900A, the DMAcontroller generates a write signal for RAM and aread signal for the CS8900A. The data flows di-rectly from the CS8900A to the system RAM. Thedirect mode of DMA operation is 100% more effi-cient than typical read-followed-by-write DMAoperation. The length of time that the CS8900A holds theDRQ signal active depends upon the DMABurst(bit B) bit of the BusCTL (Register 17) register. Ifthe DMABurst is clear, the DRQ remains active as8 AN83REV3

and RESET are inactive.

AN83long as the CS8900A contains frames completelyreceived. If n words are to be transferred from theCS8900A to the system RAM, the DRQ signal re-mains active until the (n-1)th word is transferred. Ifthe DMABurst is set, then the CS8900A deassertsDRQ signal for 1.3 s after every 28 s. This op-tion is provided so that in a system where multipleDMA channels are operational, the DMA used forthe CS8900A will not take over the system bus forlong periods of time.

Selection of I/O, Memory and DMA ModesThe CS8900A always responds to all IO-mode re-quests. After any reset, the CS8900A responds todefault IO base address of 0300h. However, thisdefault IO address can be changed by writing a dif-ferent base address into a EEPROM connected tothe CS8900A. After any reset, the CS8900A readsthe contents of the EEPROM. If the EEPROM isfound valid, then the information in the EEPROMis used by the CS8900A to program its internal reg-isters.Memory mode in the CS8900A can be enabled byprogramming a proper base-address value in theMemory Base Address register and setting theMemoryE bit. Enabling of the memory mode canbe done by software or through an EEPROM con-nected to the CS8900A. In an IO mode, the CS8900A takes the minimumspace (16 bytes) in the system address space. Forsystems where the address space limited, the IOmode is a proper choice.In the memory mode the CS8900A occupies 4K ofthe address space. The software can access any ofthe internal registers of the CS8900A directly. Thisreduces accesses to the CS8900A by half when ac-cessing registers.In a system design, even if CS8900A is used in thememory mode, the designer should make provi-sions for accessing the CS8900A in the IO mode.This dual-mode access has two advantages.

1) If an EEPROM is not used in the Ethernet de-sign, the application can address the CS8900Ain IO mode (0300h) in order to enable memorymode.

2) When the EEPROM is used, the EEPROM isusually blank when a board is manufactured.The CS8900A must be accessed in IO mode inorder to program the EEPROM.

Use of DMA for receive is efficient in a multi-task-ing environment where the CPU could be busy ser-vicing several higher priority tasks before it canservice receive frames off the Ethernet wire.

Design Example: CS8900A Interface to MC68302In this example the CS8900A is connected to Mo-torola micro-controller MC68302. Please refer toFigure 3 to check the connection of control signalsbetween CS8900A and Motorolas micro-control-ler MC68302.

Address GenerationThe MC68302 has address decode generation logicinternal to the micro-controller. It generates chipselect signals such as CS1. In this example the CS1is used to access the CS8900A in IO as well as inMemory mode. The behavior of the CS1 signalfrom the MC68302 is governed by values pro-grammed in the CS1 base address register and theCS1 option register. For example, if the CS1 baseaddress register is programmed as 3A01h, the CS1will have a base address of D00xxxh. The CS1 op-eration register controls the address range, numberof wait states (to be inserted automatically), etc. Itis recommended that the CS8900A be assigned 8Kof address space (0D00000h-0D01FFFh). Memo-ry mode of the CS8900A is enabled with the mem-ory base address register with a value 001000h.The address line A12 separates IO address spaceand memory address space. When A12 is low, theCS8900A is accessed in an IO mode and when A12AN83REV3 9

is high, the CS8900A is accessed in memory mode.

AN83When the MC68302 generates address 0D00300h,the address seen by the CS8900A will be 00300hwith one of the IO commands (IOR or IOW) active.Similarly when the MC68302 generates address0D01400h, the address seen by the CS8900A willbe 01400h with one of its memory commands(MEMR or MEMW) active. For a MC68302, youcan also specify the number of wait states thatshould be inserted automatically when addressspace assigned to CS1 is accessed. The number ofwait states used depends upon the clock input to theMC68302. Please do a complete timing analysisbefore defining wait states.

Read and Write SignalsThe combination of OR gates and an invertershown in Figure 3, generates IO commands (IOR,IOW) as well as memory commands (MEMR,MEMW) for the CS8900A. Since the CS1 gatesthese signals, the IO or memory commands are not

generated unless the address on the address bus isstable. Further, for an access in memory mode, anIO command is not active.

SBHE SignalThe CS8900A is a 16 bit device and it should beused as a 16 bit device. However, after a hardwareor software reset, the CS8900A behaves as an 8 bitdevice. Any transition on pin SBHE places theCS8900A into 16-bit mode. Further, for a 16-bitaccess, the SBHE pin of the CS8900A must be low.In the design example, the CPU address line A0 isconnected to SBHE. Before any access to theCS8900A, the design must guarantee one transitionon SBHE pin.

Other Control SignalsAll other control signals can be tied HIGH orLOW. The signal REFRESH, TEST, SLEEP,AEN should be tied inactive.

74F32

74F3274F32

74F3274F04

74F04

CS1*R/W*

SBHE*SA0

SA[1:11]

SA12SA[13:19]MEMW*

IOW*

MEMR*

IOR*

INTRQ0

UDS*/A0

A[1:11]

A12

CS1*R/W*

INT*

CS8900MC68302

InterruptController

Figure 3. Connection of CS8900A to MC6830210 AN83REV3

AN83Status Signals from CS8900AThere are several status signals that are output fromthe CS8900A, such as IOCHRDY, IOCS16,MCS16, etc. In the most embedded designs, theyare not needed. Those pins from the CS8900Ashould be left open.

Databus (SD[0:15]) ConnectionAll the internal registers of the CS8900A are 16 bitwide. For all the registers, bit F of the register is ac-cess via SD15 and bit 0 of register is accessed viaSD0.To be compatible with byte ordering with ISA bus,the CS8900A provides the bytes received from theEthernet wire in the following fashion. Assumethat the data received from the Ethernet wire is 01,02, 03, 04, 05, ... where the 01 is the first byte, 02is the second byte and so on. When the CS8900Atransfers that data to the host CPU, the data wordsare read from the CS8900A as 0201, 0403, etc. Forcertain microprocessor systems, the designer mayprefer to read the data as 0102, 0304, etc. In sucha case, the databus connections to the CS8900Acan be altered by connecting the CPU databusD[0:7] to the SD[8:15] pins of the CS8900A andthe CPU databus D[8:15] to the SD[0:7] pins of theCS8900A. In such a case, make sure that all theregister and bit definitions in the CS8900A are alsobyte swapped. Information that is normally appearsat bits [0:7] will now appear on bits [8:15], and in-formation that usually appears on bits [8:15] willnow appear on bits [0:7].Checklist for Signal Connections to the CS8900APlease refer to the datasheet for the CS8900A forthe pin assignment and pin descriptions of varioussignals discussed in this section.Clock: There are two options for the clock connec-tion to the CS8900A. You may connect a 20.000MHz crystal between XTL1 (pin 97) and XTL2

MHz clock available in the system, it can be con-nected to the XTL1 (pin 97) pin of the CS8900A.It is important that this clock be TTL or CMOSwith 40/60 duty cycle and 50 ppm accuracy.SBHE signal: It is recommended that theCS8900A be used in 16-bit mode. After a hard-ware or software reset, the CS8900A comes up asan 8-bit device. A transition on SBHE signal (pin36) makes the CS8900A function as a 16-bit de-vice. After this transition, the SBHE can be keptlow. For a 16-bit access of the CS8900A, theSBHE and address line SA0 (pin 37) must be low.Un-aligned word accesses to the CS8900A are notsupported. In a system, the SBHE line can be con-nected to address line SA0. In such a case, after ahardware or software reset, do a dummy read froman odd address to provide transition on the SBHEline. For memory mode, there is one more alterna-tive for the SBHE connection. For a memory modeoperation, if a CHIPSEL pin is controlled by an ex-ternal chip select, the CHIPSEL can be connectedto the SBHE. In this case, after a hardware andsoftware reset, do a dummy access to the CS8900Aand ignore data.

EEPROM OptionalThe CS8900A has an interface for a serial EE-PROM. Most of the networking applications usethis EEPROM to store IEEE MAC (Media AccessControl) address. Since the CS8900A supports 1 or2 Kbits of EEPROM, the EEPROM is also used tostore information such as hardware configuration,software driver configuration, etc. Any location inthe EEPROM can be read or written through theCS8900A.You will require EEPROM if the IO address for theCS8900A has to be other then 0300h, or the onlymode supported by the CS8900A is memory mode.For all other cases an EEPROM is optional. How-ever, most of the software drivers supplied by Cir-rus assume that there is an EEPROM connected toAN83REV3 11

(pin 98) pins of the CS8900A. Or, if there a 20 the CS8900A or driver configuration data is stored

AN83in BIOS. If the designer intends to use Cirrus sup-plied drivers and does not use an EEPROM or storedriver configuration data in BIOS, then Cirrus sup-plied drivers must be modified by the designer. We recommend that the system store the individualIEEE MAC address in a non-volatile memorysomewhere in the system, and that the end-user ofthe system not be allowed to create an arbitrary ad-dress. In a LAN, the existence of network nodesthat use the same MAC address will cause severenetwork problems including destruction of data andfailure of various network nodes.

Design Example: CS8900A Interface to Cirrus Logic CL-PS7211This design is similar to the MC68302 except thatonly the I/O mode data access is supported. Thiscompletely elimiates glue logic. See Figure 4. Thehighlights of the design are:

- CS8900A I/O space mapped into 7211 memory- 3 address lines - A8 and A9 tied high- AEN used as active low chip select- SBHE tied to 7211 chip select- Only 16 bit accesses

Design Example: CS8900A Interface to Hitachi SH3This design is almost identical to the CL-PS7211connection diagram. It uses I/O mode only, elimi-nating glue logic. See Figure 5. The highlights ofthe design are:

- CS8900A I/O space mapped into SH3 memory- 3 address lines - A0 is tied to ground.- A8 and A9 tied high- AEN used as active low chip select- SBHE tied to SH3 chip select- Inverter on the IRQ line.- Only 16 bit accesses

SummaryThe CS8900A can be interfaced to most non-ISAsystem with very minimum or no external logic.This allows a low cost, small size and very efficientEthernet solution for non-ISA systems. CirrusLogic will provide support for non-ISA designs,including logic schematic review and layout reviewfor design engineers. Those reviews help preventlogic errors, and help to minimize EMI emissions.12 AN83REV3

AN83LINK

ACTIVITY

D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15

nMWEnMOE

A1A2A3

nCS2

CS8900_RST

D[15:0]

A[3:1]

CS8900_RSTnURESET

EINT3

VDD

VDD

VDD

VDD

VDD VDDVDD VDD VDD

VDD

VDD

VDD

VDD

VDD

GND

GND

GND

GND

GND

GND GND GND GND GND GND GND

C62560pF

R97100K

U21CS8900A

93

3738394041424344454647485051525354585960

65666768717273742726252421201918

728296261493663757776

2

3456

9798

9978100

8483

8281

8079

9291

8887

32313035

343364

151311

161412

17

9 22 56 698 10 23 55 57 70

1 89 86 94 96 90 85 95

RES

SA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19

SD0SD1SD2SD3SD4SD5SD6SD7SD8SD9SD10SD11SD12SD13SD14SD15

CHIPSELMEMWMEMRIOWIORREFRESHSBHEAENRESETSLEEPTESTSELELCS

EECSEESK

EEDATAOUTEEDATAIN

XTLIXTLO

LED0/HC0BSTATUS/HC1

LANLED

DO-DO+

CI-CI+

DI-DI+

RXD-RXD+

TXD-TXD+

INTRQ0INTRQ1INTRQ2INTRQ3

MEMCS16IOCS16

IOCHRDY

DMARQ0DMARQ1DMARQ2

DMACK0DMACK2DMACK3

CSOUT

VC

CV

CC

VC

CV

CC

GN

DG

ND

GN

DG

ND

GN

DG

ND

AV

SS

0A

VS

S1

AV

SS

2A

VS

S3

AV

SS

4

AV

DD

1A

VD

D2

AV

DD

3R948R

R958R

R964K99 1%

X3

20MHz

R91

4K7

R89390R

C89100nF

C90100nF

R93100R

D7LED

2 1

C93100nF

C92100nF

C94100nF

R90390R

D6LED2 1

C88100nF

U30A

74LVX04

1 2

C91100nF

D[15:0]

A[3:1]

nMWEnMOE

nCS2

nURESET

RxD-

RxD+

TxD-

TxD+

Figure 4. CS8900A Interface to Cirrus Logic CL-PS7211AN83REV3 13

AN83SH3 A2

SH3 IRQ0

RESET

SH3 RO#

Chip Select#

SH3 WE1#

SH3 [D15:D0]

SH3 A1

SH3 A3RDX-

RXD+

TXD-

TXD+

3.3V

3.3V

3.3V

3.3V

510

0.1u

F

510

CS8900A-CQ3

373839404142434445464748505152535458596065666768717273742726252421201918

28 29 62 61 49 63 75 34 33 64 32 31 30 35 15 13 11 16 14 12 3654

9 22 56 6990 85 958 10 23 55 57 70 189 86 94 96

77 76 93

8483

8079

8281

92918887

789910017

97

98

2 7 36

SA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19SD0SD1SD2SD3SD4SD5SD6SD7SD8SD9SD10SD11SD12SD13SD14SD15 M

EMW

MEM

RIO

WIO

RRE

FRES

HAE

NRE

SET

MEM

CS16

IOCS

16IO

CHRD

YIN

TRQ0

INTR

Q1IN

TRQ2

INTR

Q3DM

ARQ0

DMAR

Q1DM

ARQ2

DMAC

K0DM

ACK1

DMAC

K2

EECS

EEDA

TAIN

EEDA

TAOU

TEE

SK

DVDD

1

DVDD

2

DVDD

3

DVDD

4

AVDD

1

AVDD

2

AVDD

3

DVSS

1

DVSS

1A

DVSS

2

DVSS

3

DVSS

3A

DVSS

4

AVSS

0

AVSS

1

AVSS

2

AVSS

3

AVSS

4

HWSL

EEP

TEST

SEL

RES

DO-DO+

DI-DI+

CI-CI+

RXD-RXD+TXD-TXD+

BSTATUS/HC1LINKLED/HC0

LANLEDCSOUT

XTAL1

XTAL2

ELCS

CHIP

SEL

SBHE

LED

4.99K

0.1u

F

LED

0.1u

F

20MHz

0.1u

F

0.1u

F

0.1u

F

0.1u

F

560pF

8

8

100

Figure 5. CS8900A Interface to Hitachi SH314 AN83REV3

AN83ETHERNET HARDWARE DESIGN FOR EMBEDDED SYSTEMS AND MOTHERBOARDSThis section describes the hardware design of afour-layer, 10BASE-T solution intended for use onPC motherboards, or in other embedded applica-tions. The goal of this design is minimal boardspace and minimal material cost. Therefore, a num-ber of features (BootPROM, AUI, 10BASE-2) arenot supported in this particular PCB design. An ex-ample of this circuit is included in this technicalreference manual, and is implemented in an ISAform factor. This same circuit can be implementeddirectly on the processor PCB.

General DescriptionThe small footprint, high performance and low costof the CS8900A Ethernet solution, makes theCS8900A an ideal choice for embedded systemslike personal computer (PC) mother boards. Thevery high level of integration in the CS8900A re-sults in a very low component count Ethernet de-sign. This makes it possible to have a completesolution fit in an area of 1.5 square inches.

Board Design Considerations

Crystal OscillatorThe CS8900A, in this reference design, uses a20.000 MHz crystal oscillator. The CS8900A hasinternal loading capacitance of 18pF on theXTAL1 and XTAL2 pins. No external loading ca-pacitors are needed. Please note that the crystalmust be placed very close to XTL1 and XTL2 pinsof the CS8900A.This crystal oscillator can be eliminated if accurateclock signal (20.00 MHz 0.01% and 45-55 dutycycle) available in the system.ISA Bus InterfaceThe CS8900A has a direct ISA bus interface. Notethat the ISA bus interface is simple enough to allow

the CS8900A to interface with variety of micro-processors directly or with the help of simple pro-grammable logic like a PAL or a GAL.This reference design uses the ISA adapter cardform factor. All the ISA bus connections from theCS8900A are directly routed to the ISA connector.The pin-out of the CS8900A is such that if theCS8900A is placed as shown in Figures 6 and 7,there will be almost no cross-over of the ISA sig-nals.

External Decode LogicThe CS8900A can be accessed in I/O mode ormemory mode. For this reference design, in mem-ory mode the CS8900A is in the conventional orupper memory of the PC. That is, it resides in thelower 1 Mega bytes of address space.To use the CS8900A in extended memory addressspace requires an external address decoder. Thisdecoder decodes upper 4 bits (LA[20:23]) of 24 bitISA address lines. In many embedded micropro-cessors such decodes are available though the mi-croprocessors itself. Please refer to Extended Memory Mode onpage 31 for further information.

EEPROMA 64 word (64 X16 bit) EEPROM (location U3) isused in the reference design to interface with theCS8900A. This EEPROM holds the IEEE as-signed Ethernet MAC (physical) address for the-board (see Obtaining IEEE Addresses onpage 55). The EEPROM also holds other configu-ration information for the CS8900A. The last fewbytes of the EEPROM are used to store informationabout the hardware configuration and software re-quirements.In an embedded system, such as a PC, the systemCMOS RAM or any other non-volatile memorycan be used to store the IEEE address and Ethernetconfiguration information. In such a case an EE-AN83REV3 15

AN83Figure 6. Placement of Components, Top Side

CS8

900

EVAL

REV

. BC

DB8

900B

C

OPY

RIG

HT

1994

CRYS

TAL

SEM

ICO

NDUC

TOR

CORP

ORA

TIO

NCS

8900

EVA

L BO

ARD

REV.

BP/

N CD

B890

0B16 AN83REV3

AN83Figure 7. Placement of Components, Solder Side

CRYS

TAL

SEM

ICO

NDUC

TOR

CORP

ORA

TIO

NCS

8900

EVA

L BO

ARD

REV

. CP/

N CD

B890

0BAN83REV3 17

AN83PROM is not necessary for the CS8900A, and theCS8900A will respond to IO addresses 0300hthrough 030Fh after a reset.Please refer to the CS8900A data sheet for informa-tion about programming the EEPROM. Please re-fer to JUMPERLESS DESIGN on page 45 ofthis document for information about EEPROM in-ternal word assignments.

LEDsMany embedded systems do not require LEDs forthe Ethernet traffic. Therefore this reference de-sign does not implement any LEDs. However, theCS8900A has direct drives for the three LEDs.Please refer to the data sheet for the CS8900A for adescription of the LED functions available on theCS8900A.

10BASE-T InterfaceThe 10BASE-T interface for the CS8900A isstraight forward. Please refer to Figure 8 (3.3V)and Figure 10 (5V) for connections and compo-nents of this circuit. Transmit and receive signallines from the CS8900A are connected to an isola-

tion transformer at location T1. This isolationtransformer has a 1:1 ratio between the primary andthe secondary windings on the receive side. It hasa 1:2 (1:1.414) ratio between the primary and thesecondary windings for the transmit lines for 5Voperation or a ratio of 1:2.5 for 3.3V operation. Re-sistor R1 provides termination for the receive lines.Resistors R2 and R3 are in series with the differen-tial pair of transmit lines for impedance matching.

10BASE-2 and AUI InterfacesAs many embedded systems require only a10BASE-T interface, this reference design imple-ments only the 10BASE-T interface. However,should a user require a 10BASE-2 or AUI inter-face, the CS8900A provides a direct interface to theAUI. Please refer to Low Cost Ethernet ComboCard Reference Design: CRD8900 on page 21 ofthis document for details about the AUI interface.

Logic SchematicsFigures 8, 9 and 10 detail the logic schematics forthe various circuits used in the reference design.

10BT_RD-100R2

8R4

8R5

.1uF .1uFC23

.1uF 2KVC28

.1uF 2KV C29

1

1

2

2

3

34

455

6

6

7

7

8

812345678

16(1-3) (16-14) 1:1

(6-8) (11-9) 1:2.5

10BaseT Transformer

151413121110

10J21

9

161514131211109

9

Do NotPopulate

560pFC30

10BT_RD+

10BT_TD-

10BT_TD+

Do NotPopulate

Figure 8. 10BASE-T Schematic 3.3V18 AN83REV3

AN83SA00SA01SA02SA03SA04SA05SA06SA07SA08SA09SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19

ISA0ISA1ISA2ISA3ISA4ISA5ISA6ISA7ISA8ISA9ISA10ISA11ISA12ISA13ISA14ISA15ISA16ISA17ISA18ISA19

3738394041424344454647485051525354585960

CHIPSELMEMWMEMRIOWIORREFRESHSBHEAEN

728296261493663

SMEMWSMEMR

IOWIOR

REFRESHSBHE

AEN

76

7775

TSTSEL

RESET

TESTSEL

SLEEPRESET

+5V

XTAL20.0 MHz

X11 2

9798

93

XTL1XTL2

RES

R44.99k, 1%

ELC

SD

VSS3

A

DVS

S1A

DVS

S4D

VDD

4D

VSS3

DVD

D3

DVS

S2D

VDD

2D

VSS1

DVD

D1

AVSS

3

AVD

D3

AVSS

2AV

DD

2

AVSS

1

AVD

D1

AVSS

4

AVSS

0EE

DAT

AIN

EESK

2 57 10 70 69 55 56 23 22 8 9 94 95 86 85 89 90 96 1 6 4

C12

C14

C13

C9 C8

C11

C10

0.1

F

+5V

EE_CLK

+5V

0.1F C7

1235

84

76

VCCD0

NC2NC1

1K_EEPROM_S

CSCLKD1VSS

U3

EECSEEDATAOUT

35

12

U1CS8900

RXD+TXD-TXD+

INTRQ0INTRQ1INTRQ2INTRQ3

MEMCS16I0CS16

I0CHRDYDMARQ0DMARQ1DMARQ2

CSOUT

91888732313035343364151311

17

10BT_RD+10BT_TD-10BT_TD+IRQ10IRQ11IRQ12IRQ5MEMCS16I0CS16I0CHRDYDRQ5DRQ6DRQ7

ISA_

D0

ISA_

D1

ISA_

D2

ISA_

D3

ISA_

D4

ISA_

D5

ISA_

D6

ISA_

D7

ISA_

D8

ISA_

D9

ISA_

D10

ISA_

D11

ISA_

D12

ISA_

D13

ISA_

D14

ISA_

D15

65 66 67 68 71 72 73 74 27 26 25 24 21 20 19 18

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD8

SD9

SD10

SD11

SD12

SD13

SD14

SD15

DM

ACK

0D

MA

CK2

DM

ACK

3

16 14 12D

ACK5

DAC

K6D

ACK7

8079

8281

8483

78100

99

RXD- 92 10BT_RD-

DI-DI+

CI-CI+

DO-DO+

BSTATUS / HC1LED2

LED0/HC0

0.1

F

0.1

F

0.1

F

0.1

F

0.1

F

0.1

FAN83REV3 19

Figure 9. Overall Schematic

AN83 Component Placement and Signal RoutingPlease refer to Layout Considerations for theCS8900A on page 35 of this document for moredetails on the placement of components on theboard. It is important to provide very clean and ad-equate +5 V and ground connections to theCS8900A.

Bill of MaterialTable 1 has a list components that are typicallyused to assemble this adapter card. For most of thecomponents, there are several alternative manufac-turers.

1

2

3

4

5

6

7

8

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

9

10

11

12

13

14

15

16

(1-3) (16-14) 1:1

(6-8) (11-9) 1:1.414

10 BaseT Transformer

100R2

24.3R4

24.3R5

68 pFC30

.1 FC23

Do Not Populate

.1 F 2KVC29

.1 F 2KVC28

J1

10

87654321

9

.1 F

Do Not Populate

10BT_RD-

10BT_RD+

10BT_TD-

10BT_TD+

Figure 10. 10BASE-T Schematic 5V

C17TANT TANT TANT

22F 22F 22F

C16 C15+

+5V

GND

++

Figure 11. Decoupling Capacitors Schematic

Item Reference # Description Quantity Vendor Part Number1 C2, C5, C7..C14 Capacitor, 0.1 F, X7R, SMT0805 102 C15, C16, C17 Capacitor, 22 F, SMT7343 33 R2, R3 Resistor, 24.3, 1%, 1/8W, SMT0805 24 R1 Resistor, 100, 1%, 1/8W, SMT0805 15 R4 Resistor, 4.99K, 1%, SMT0805 16* X1 Crystal, 20.000 MHz 1 M-tron ATS-49,20.000 MHz,18 pF7 J1 Connector, RJ45, 8 pin 1 AMP 555164-18 T1 Transformer, 2, 1:1, 1:1.41 1 Valor ST7011 (SOIC)9 U1 ISA Ethernet Controller 1 Crystal CS8900A

10* U3 1K EEPROM 1 Microchip 93C46 (8 pin SOIC)* Depending on system resources, these parts may not be needed.

Table 1. CS8900A Design Bill of Materials20 AN83REV3

AN83LOW COST ETHERNET COMBO CARD REFERENCE DESIGN: CRD8900This section describes the hardware design of a low-cost, two-layer, full-featured Ethernet solution in-tended for use in PC ISA-bus. The goal of this designis a high degree of application flexibility. Therefore,a number of features (BootPROM, AUI, 10BASE-2)are supported. An example of this circuit is includedin this Technical Reference Manual.

General DescriptionThe CS8900A ISA Ethernet controller is used inthis low cost, high performance ISA Ethernetadapter card. This card has AUI, 10BASE-T and10BASE-2 interfaces. The very high level of inte-gration of the CS8900A results in a very low com-ponent count. This makes it possible to design ahalf height, two layered 16 bit ISA Ethernet adaptercard. Since the analog filters are integrated on theCS8900A, the card may be compliant with FCCpart 15 class (B) compliant.Board DesignA recommended component placement is shown inFigure 12, and a recommended board schematicsare shown in Figures 10 and 13 through 17.

Crystal OscillatorThe CS8900A, in the reference design, uses a20.000 MHz crystal oscillator. Please note that thecrystal must be placed very close to XTL1 andXTL2 pins of the CS8900A.

ISA Bus InterfaceThe ISA bus connections from the CS8900A can beeasily routed to the ISA connector. If the pin-out ofthe CS8900A is placed as shown in Figure 12, therewill be almost no cross-over of the ISA signals. Itis also important to provide very clean and ade-quate +5 V and ground connections to theCS8900A.

External Decode LogicThe CS8900A can be accessed in both I/O andmemory modes. The CS8900A internally decodesthe SA[0:19] address lines for the lower 1 M ofmemory. The reference design uses an external de-code logic to allow the card to also decode decodesthe upper 4 bits of the ISA address (LA[23:20]),thus allowing the CS8900A to reside anywhere inextended memory. This decode logic is implement-ed using a 16R4 PAL at location U4. This logic isconfigured by the CS8900A. The PAL then de-codes the upper 4 bits of the ISA address. Please re-fer to Addressing the CS8900A: I/O Mode,Memory Mode on page 27 of this document forfurther information.

EEPROMA 64 word (64 X16) EEPROM (location U3) isused in the reference design to interface with theCS8900A. This EEPROM holds the IEEE as-signed Ethernet MAC (physical) address for theboard. (see Embedded Designs on page 54) TheEEPROM also holds other configuration informa-tion for the CS8900A. The last few bytes of theEEPROM are used to store information about thehardware configuration and software requirements.Please refer to the CS8900A datasheet for informa-tion about programming the EEPROM. Please re-fer to JUMPERLESS DESIGN on page 45 ofthis document for information about EEPROM in-ternal word assignment.

Socket for Optional Boot PROMA socket is provided at location U6 for the optionalBoot PROM. This Boot PROM is required in sys-tems that require remote boot capability, for exam-ple diskless work stations. The 74LS245 databuffer at U7 is provided for the Boot PROM (SeeFigure 15). Inside the CS8900A there are registersthat hold the Boot PROM base address (Pack-etPage base + 030h) and the Boot PROM addressAN83REV3 21

mask (PacketPage base + 034h). A 20 bit address

AN83U6

CS8

900

CO

MBO

EVA

L R

EV. B

CD

B890

0B

CO

PYR

IGH

T 19

94

CRY

STA

L SE

MIC

OND

UCTO

R CO

RPO

RATI

ON

CS8

900

CO

MB

O E

VAL

BOAR

D R

EV. B

P/N

CDB

8900

B

C1

C2 U6

U7

C10

C4

C7 C8

U1

C3 U4

C17C1

6

++

C6C9

C11

R3C1

2C1

3

R4R5

X1R2

C30

U3C5

1

R6

C14 R

7R

8C1

5 R9

C18

U5

C1P

+C2

0

R10U

2

C21

T1

U9

C27

J3

D1R

16R

17

R15

C24

R11

R12

R13

R14

T2

C26

F1

C29

C23

T3

C22

C28

R19 J1

J4

LED

1T

B

R18

J2

Figure 12. Placement of Components22 AN83REV3

AN83SA00SA01SA02SA03SA04SA05SA06SA07SA08SA09SA10SA11SA12SA13SA14SA15SA16SA17SA18SA19

ISA0ISA1ISA2ISA3ISA4ISA5ISA6ISA7ISA8ISA9ISA10ISA11ISA12ISA13ISA14ISA15ISA16ISA17ISA18ISA19

3738394041424344454647485051525354585960

CHIPSELMEMWMEMRIOWIORREFRESHSBHEAEN

728296261493663

CHIPSELMEMWMEMR

IOWIOR

REFRESHSBHE

AEN

76

7775

TSTSEL

RESET

TESTSEL

SLEEPRESET

+5V

XTAL20.0 MHz

X1

1 2

ELCS

9798

93

XTL1XTL2

RES

R34.99k

ELCS

DVS

S3A

DVS

S1A

DV

SS4

DVD

D4

DV

SS3

DVD

D3

DV

SS2

DVD

D2

DV

SS1

DVD

D1

AVS

S3AV

DD

3

AVSS

2AV

DD

2

AVSS

1

AVD

D1

AVSS

4

AVSS

0EE

DAT

AIN

EES

K

2 57 10 70 69 55 56 23 22 8 9 94 95 86 85 89 90 96 1 6 4

C16

C17

C8

C7 C1

1

C13

C12

0.1

F

+5V

EE_C

LK

EE_D

IN

EE_CLK

+5V

0.1F C5

1235

84

76

VCCD0

NC2NC1

1K_EEPROM_S

CSCLKD1VSS

U3

EECSEEDATAOUT

35

12

U1CS8900

RXD-RXD+

TXD-TXD+

INTRQ0INTRQ1INTRQ2INTRQ3

MEMCS16I0CS16

I0CHRDY

DMARQ0DMARQ1DMARQ2

CSOUT

92918887

32313035

343364

151311

17 PROM CS

10BT_RD-10BT_RD+

10BT_TD-10BT_TD+

IRQ10IRQ11IRQ12IRQ5MEMCS16I0CS16I0CHRDYDRQ5DRQ6DRQ7

PROM_CS

ISA

_D

0IS

A_D

1IS

A_D

2IS

A_D

3IS

A_D

4IS

A_D

5IS

A_D

6IS

A_D

7IS

A_D

8IS

A_D

9IS

A_D

10IS

A_D

11IS

A_D

12IS

A_D

13IS

A_D

14IS

A_D

15

65 66 67 68 71 72 73 74 27 26 25 24 21 20 19 18

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD8

SD9

SD10

SD11

SD12

SD13

SD14

SD15

DM

ACK0

DM

ACK2

DM

ACK3

16 14 12D

ACK

5D

ACK

6D

ACK7

DI-DI+

8079

CI-CI+

8281

DO-DO+

8483

DI-DI+

CI-CI+

DO-DO+

BSTATUS / HC1LED2

78100

LED0/HC0 99

BSTATUS / HC1

R18 680

R19 680

3

1

4

2

LED_T

LED_B

0.1

F

0.1

F

0.1

F

0.1

F

0.1

F

0.1

F

Figure 13. CS8900A Schematic (Combo Card Application)AN83REV3 23

AN83Figure 14. Power Supply Decoupling Schematic

Figure 15. Boot PROM Schematic

C19TANT TANT TANT

22F 22F 22F

C10 C1+

+5V

GND

++

SA00SA01SA02SA03SA04SA05SA06SA07SA08SA09SA10SA11SA12SA13SA14

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14

109876543

252421232

2627

DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0

27C256

CEOEVPP

PROM_CS

12220

1918171615131211

PD7 2PD6 3PD5 4PD4 5PD3 6PD2 7PD1 8PD0 9

A1A2A3A4A5A6A7A8

B1B2B3B4B5B6B7B8

18171615

131211

14

OEDIR1

19R1

4.7k

+5V

C4 0.1F

U7

SD7SD6SD5SD4SD3SD2SD1SD0

74LS245

U6

C2 0.1F24 AN83REV3

AN83Figure 16. AUI Schematic

Figure 17. 10BASE-2 Schematic

Figure 18. PAL Decode of LA[20-23]

+12V

0.1FBSTATUS/HCI

124578

16151312109

AUI_XFR_S

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CLKG1011121314151617

I/00I/01I/02I/03

12131819

14151617

00010203

CHIPSEL_B (CS8900 Pin7)

PAL16R4

ELCSEEDOUT

BALELA23LA22LA21LA20

RESET

EE_SK

(CS8900 Pin2)CS8900 Pin5)(ISA B28)(ISA C02)(ISA C03)(ISA C04)(ISA C05)(ISA B02)

(CS8900 Pin 4)AN83REV3 25

AN83loaded at the Boot PROM base address register in-dicates the starting location in host memory wherethe Boot PROM is mapped. The Boot PROM ad-dress mask indicates the size of the Boot PROM.The lower 12 bits of the mask are ignored andshould be 000h. This limits the 434 Boot PROMsize to increments of 4K bytes. The CS8900A willnot generate an address decode for the Boot PROMuntil the Boot PROM base address register and themask register are loaded. For example, say a 16KBoot PROM is used and it is to be located startingat address 0D0000h. Before this Boot PROM isaccessed, load the following registers with the val-ues shown in Table 2.

The address mask that will be used by theCS8900A is 0FC000h. The CS8900A will com-pare SA[19:14] with the value 0D0h. Wheneverthere is a match, it will assert the signal CSOUT togenerate an address decode for the Boot PROM. Inthe reference design, the same signal is also used toenable the data buffer, 74LS245, at location U7.

LEDsA pair of LEDs are provided in the reference designto indicate link OK and line active status. The pairof LEDs are packaged one on the top of the other atlocation LED1. The top LED is driven by the LIN-KLED pin while the bottom LED is driven by theLANLED pin of the CS8900A. The top LED lights

up when the CS8900A has the link pulse. The bot-tom LED lights up when the CS8900A transmits orreceives a packet or senses a collision. The LEDsare directly driven by the CS8900A. Two 680 Ohmresistors limit the current flowing through the LEDcircuitry.

10BASE-T InterfaceThe 10BASE-T interface for the CS8900A isstraight forward. Please refer to Figure 8 or 10 forconnections and components of this circuit. Trans-mit and receive signal lines from the CS8900A areconnected to an isolation transformer at locationT3. For 5V operation this isolation transformer hasa 1:1 ratio between the primary and the secondarywindings on the receive side and 1:2 (1:1.41) ratiobetween the primary and secondary windings forthe transmit lines. For 3.3V operation the receiveside is 1:1 and the transmit side is 1:2.5. ResistorR2 provides termination for the receive lines. Re-sistors R4 and R5 are in series with the differentialpair of transmit lines for impedance matching.

AUI InterfacePlease refer to Figure 16 for connection of AUI sig-nals to the CS8900A. The AUI lines from the 15-pin sub-D connector (location J2) are connected tothe CS8900A through an isolation transformer atT2. This isolation transformer has three windingsfor three pairs of differential AUI signals: transmit,receive and collision. All three windings have aturns ratio of 1:1 between the primary and second-ary windings. Circuitry consisting of R6, R7 andC14 provides impedance termination for the colli-sion differential pair. Circuitry consisting of R8,R9 and C15 provides impedance termination forthe receive differential pair. The +12 volt powergoing out to the AUI connector is safeguarded bythe fuse at F1. The AUI interface at J2 can be usedto connect external Media Access Units (MAU).These MAUs allow the AUI interfaced to be usedto interface with 10BASE-5 or 10BASE-F.

Register Word Offset

PacketPage Base +

Hex value Description

30h 0000h Boot PROM Base address - low word

32h 000Dh Boot PROM Base address - high word

34h C000h Boot PROM address mask - low word

36h 000Fh Boot PROM address mask - high word

Table 2. BootPROM Descriptions Stored in CS8900A PacketPage26 AN83REV3

AN8310BASE-2 InterfaceA 10BASE-2 transceiver IC, the 83C92C, is usedto generate a 10BASE-2 interface for the referencedesign. Please refer to Figure 17 for details aboutthe components and connection.A 12 volt to -9 volt DC to DC voltage converter (lo-cation U5) is used to generate an isolated -9 voltsupply for the 83C92C. The DC-DC converterused in the reference design has an enable pin. Thisenable pin is connected to the HC1 pin of theCS8900A. Usually the DC-DC converter is dis-abled when the 10BASE-2 interface is not used.This not only reduces power used by the adaptercard but also eliminates any noise the 10BASE-2circuitry can induce on the 10BASE-T or AUI in-terface that may be in use. This reference designuses a low enable DC-DC converter. That is, theDC-DC converter is enabled when the enable pin islogic low. However, the board can be built with ahigh enable DC-DC converter. In such a case,software that controls the enable and disable oper-ations of the DC-DC converter should be modified.An optional method is to use an integrated modulethat includes all the needed 10Base2 components.Contact Halo Electronics for information on theirTnT integrated 10Base2 modules.

Logic SchematicsFigures 10 and 13 through 17 detail logic schemat-ics for the various circuits used in the reference de-sign.

Component Placement and Routing of Sig-nalsFigure 12 shows the component placement used forthe reference design. Figure 19 shows the routingof signals on the component side of the printed cir-cuit board (PCB) while Figure 20 shows routing onthe solder side. Please refer to Layout Consider-ations for the CS8900A on page 35 of this docu-

ment for an explanation and information aboutplacement of components on the board.

Bill of MaterialTable 3 contains a list of components that are typi-cally used to assemble this adapter card. For mostof the components, there are several alternativemanufacturers.

Addressing the CS8900A: I/O Mode, Memory ModeThe CS8900A, integrated Ethernet controller, has20 address pins that directly connect to SA[19:0] ofthe ISA bus. The CS8900A has an internal addresscomparator to compare the ISA address with itsbase address registers.

I/O ModeIn IO mode, the lower 16 bits of the ISA address arecompared with the address stored in IO Base Ad-dress register (Packet Page base + 020h). When anaddress match occurs and one of the IO command(IOR or IOW) lines is active, the CS8900A re-sponds to that IO access. The lower 4 bits of ad-dress lines are ignored by the address comparator.This dictates that the CS8900A must always be at a16 byte address boundary of the ISA IO addressspace. The pin CHIPSEL is ignored for an IO modeaccess.

After RESET the CS8900A responds to IO address0300h. However, this condition can be modifiedwith use of an EEPROM or by software. Immedi-ately after a reset, the CS8900A reads the EE-PROM interfaced to it. If the EEPROM has validdata (valid start data and correct checksum), it willread information stored in the EEPROM to initial-ize its own registers including the IO base addressregister. Please refer to the CS8900A datasheet fordetails about EEPROM configuration and pro-gramming. A CS8900A will always respond to val-id IO address (even if its memory mode is enabled).AN83REV3 27

AN83Figure 19. CRD8900 Top-Side Routing28 AN83REV3

AN83Figure 20. CRD8900 Bottom Side RoutingAN83REV3 29

AN83Item Reference # Description Quantity Vendor Part NumberBase Configuration: I/O Mode with 10BASE-T Interface

1 C5, C7, C8, C11..13, C16, C17, C22, C23, C27

Capacitor, 0.1 F, SMT0805, X7R 11

2 C1, C10, C19 Capacitor, 22 F, SMT7343 33 R3 Resistor, 4.99K, 1%, SMT0805 14 R18, R19 Resistor, 681, 5%, 1/8W, SMT0805 25 X1 Crystal, 20.000MHz,18 pF 1 M-tron ATS-496 J4 Board Bracket 1 Globe G4367 U1 ISA Ethernet Controller 1 Crystal CS8900A8 U3 1K EEPROM 1 Microchip 93C46 9 R4, R5 Resistor, 24.3, 1%, 1/8W, SMT0805 210 R2 Resistor, 100, 1%, 1/8W, SMT0805 111 C30 Capacitor, 68 pF, SMT0805 112 T3 Transformer, 2, 1:1, 1:1.41 1 Valor ST7010 (SOIC)13 J1 Connector, RJ45, 8 pin 1 AMP 555164-1

Memory Mode Option1 C3 Capacitor, 0.1 F, SMT0805, X7R 12 U4 PAL 1 AMD PAL16R4B

Boot PROM Options1 C2, C4 Capacitor, 0.1 F, SMT0805, X7R 22 R1 Resistor, 4.7K, 5%, 1/8W, SMT0805 13 U6 32K X 8 EPROM Socket 14 U7 Octal Transceiver 1 TI 74LS245 (SOIC)

AUI Option1 C14, C15 Capacitor, 0.1 F, SMT0805, X7R 22 R6..R9 Resistor, 39.2, 1%, 1/8W, SMT0805 43 F1 Fuse, 1A 14 T2 Transformer, 3, 1:1, 100 H 1 Valor ST7033 (SOIC)5 J2 Connector, 15-pin sub-D 1 AMP 745782-16 J2 AUI Slide Latch 1 AMP 745583-5

10BASE2 Option1 C18, C20, C21 Capacitor, 0.1 F, SMT0805, X7R 32 C24 Capacitor, 0.01 F, 1kV 1 NIC Components NCD103M1KVZ5U3 R11..R14 Resistor, 510, 1%, 1/8W, SMT0805 44 R10 Resistor, 1K, 1%, 1/8W, SMT0805 15 R17 Resistor, 1M, 10%, 1/2W, TH 16 R15 Resistor, 10K, 1%, 1/8W, SMT0805 17 R16 Resistor, 121, 1%, 1/8W, SMT0805 18 D1 Diode 1 1N9169 T1 Transformer, 3, 1:1, 100 H 1 Valor ST7033 (SOIC)10 U2 Ethernet Coax Transceiver 1 83C92C(PLCC)11 U5 DC-DC Converter, 12V - 9V 1 Valor PM721512 J3 Connector, BNC, 50 Ohm 1 AMP 227161-7

LED Option1 LED1 Bilevel LEDs 1 Ledtronics 21PCT110T4-G/Y

Table 3. CS8900A COMBO Card Reference Design Bill of Materials30 AN83REV3

AN83Memory ModeIn the memory mode, there are two options wherethe CS8900A can be placed in the ISA memory ad-dress map, lower memory (below 1 Meg) or ex-tended memory (above 1 Meg). The lowermemory typically consists of the conventionalmemory (up to 640K) and upper memory (640K to1 Meg. boundary). To access anything in extendedmemory, the processor (386 and above) is used inthe Enhanced Mode. The CS8900A will respond to IO addresses pro-grammed in its IO Base Address Register (PacketPage Base + 020h) even if memory mode is en-abled. To enable memory mode, first write a prop-er 20 bit value to Memory Base Address register atPacket page base + 02Ch & 02Eh. Then set Mem-oryE (bit 0Ah) in the Bus CTL register (Register17) to one. These operations can be performed either by doingwrites using IO mode accesses or using an EE-PROM as described in Sections 3.4 and 3.5 of theCS8900A datasheet. The CS8900A will respondto an ISA memory access, if the CHIPSEL pin isactive (LOW), and the SA[19:0] match the valuestored in Memory Base Address Registers. Thelower 12 bits of the address lines are always ig-nored. This dictates that the CS8900A must alwaysbe placed at a 4K boundary in the ISA memory ad-dress space.

Lower Memory ModeTo use a CS8900A in the lower 1 Meg addressspace, SMEMRD and SMEMWR lines from theISA bus are connected to MEMR and MEMW pinsof CS8900A respectively. The SMEMRD andSMEMWR signals become active only for the low-er 1 Meg of the ISA address space. The CHIPSELpin of the CS8900A should be connected toground.

Extended Memory ModeThe CS8900A can also be mapped in to the extend-ed memory of a Personal Computer (PC) system.This provides flexibility and more options whenseveral components are installed in a PC withCS8900A based network cards.To address the CS8900A in extended memorymode, the processor is used in an enhanced mode.In an enhanced mode, 24 bits of ISA address linesare used for address generation. Since theCS8900A accepts 20 bits of address lines, an exter-nal address decoder circuit is required to decode the4 upper address bits. The CS8900A has interfacepins for external decoder circuit. This arrangement makes provisions so that theCS8900A can be placed anywhere in the extendedmemory address map as long as it is at a 4K addressboundary. The MEMR and MEMW signals of theISA bus are active for any ISA memory space ac-cess, therefore, for extended memory mode opera-tion, these signals are connected to the MEMR andMEMW pins of the CS8900A respectively.The external address decoder circuit consists of asingle and simple Programmable Array Logic likea 16R4 or GAL16V8. Please refer to the schematicshown in Figure 21 as an example of such a decod-er circuit. The PAL16R4 has 4 registers Q[23:20].These registers are programmed by the serial inputvia the inputs EESK (clock), ELCS (enable pin)and EEDataOut (serial data out). This decodercompares the 4 upper address bits, namelyLA[23:20], with the internal programmable regis-ter, Q[23:20]. Before memory mode of theCS8900A is enabled, Q[23:20] must be initializedto a proper value.In the design example, Q[23:20] form a left shiftregister. The ELCS pin of the CS8900A is used in-conjunction with EESK and EEDataOut pins toshift in the data for Q[23:20] serially. To programa value, set the ELSEL bit (bit A in Packet PageAN83REV3 31

base + 040h) to HIGH. Then the EEPROM inter-

AN83face is used to generate the serial data stream onEEDataOut pin (serial data out) with the EESK (se-rial clock). Whenever ELSEL bit is set, ELCS pinbecomes active (LOW) instead of EECS pin duringthe EEPROM operations. Since the EECS pin re-mains inactive, the EEPROM that is interfaced tothe CS8900A is not enabled. For the PAL in the design example, one should usea Program disable EEPROM command. (Opcode00000b). For example, if the CS8900A is to beplaced at PC memory space of 0A00000h, thatmeans the Q[23:20] should be 0Ah. To programthe 16R4, write 040Ah at Packet Page Base + 040h.The instruction will take about 10 micro-seconds toexecute.

The electrical connections required to use externallogic are shown in Figure 21. At reset, the

CS8900A samples ELCS pin and if it is not"LOW", it realizes presence of external address de-code logic. The same reset signal also makesADD_VALID inactive, and thus prevents a signalCHIPSEL_b from becoming active until Q[23:20]are initialized. When a host CPU writes to Pack-etPage base address + 040h to program values forQ[23:20], the CS8900A then shifts that data serial-ly in to the PAL or GAL. This makesADD_VALID signal active.From this point onwards LA[23:20] are monitoredwhenever ALE is active (HIGH). When the decodelogic finds a match, CHIPSEL_b signal is asserted.This signal remains asserted until ALE becomesactive and the LA[23:20] do not match withQ[23:20]. The internal decoder of the CS8900A isactive only when CHIPSEL_b is active (LOW).

111

23456789

CLKG1011121314151617

I/00I/01I/02I/03

12131819

14151617

00010203

CHIPSEL_B (CS8900 Pin7)

PAL16R4

ELCSEEDOUT

BALELA23LA22LA21LA20

RESET

EE_SK

(CS8900 Pin2)CS8900 Pin5)(ISA B28)(ISA C02)(ISA C03)(ISA C04)(ISA C05)(ISA B02)

(CS8900 Pin 4)

Figure 21. PAL Decode of LA[20-23]

CS8900

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Figure 22. Typical CS8900A Ethernet Connection32 AN83REV3

AN83Figure 23 shows a simple PALASMTM programfor the 16R4 PAL that is used in the design shownin Figure 21.

;PALASM Design Description;---------------------------------- Declaration Segment ------------TITLE High address decoder PATTERN REVISION

AUTHOR Deva BodasCOMPANY Crystal SemiconductorDATE 04/01/1994

CHIP _decoder PAL16R4

;--------------------------------- PIN Declarations ---------------PIN 1 SCLK ; Serial clock from the CS8900A pin 4 (EESK)PIN 2 CS_EL_b ; External Logic enable from the CS8900A pin 2 (ELCS*)PIN 3 SDATA ; Serial data in from the CS8900A pin 5 (EEDataOut)PIN 4 ALE ; Address latch enable from the ISA busPIN 5 LA23 ; Address 23PIN 6 LA22 ; Address 22PIN 7 LA21 ; Address 21PIN 8 LA20 ; Address 20PIN 9 RESET ; ISA reset pinPIN 11 OE ; Output enable for the registered outputsPIN 12 ADD_VALID COMB ; When high, Q[23:20] are programmedPIN 13 EQUALH COMB ; Upper 2 bits of address matchPIN 19 EQUALL COMB ; Lower 2 bits of address matchPIN 18 CHIPSEL_b COMB ; CHIPSEL to the CS8900A pin 7PIN 14 Q20 ; REGPIN 15 Q21 ; REGPIN 16 Q22 ; REGPIN 17 Q23 ; REG;----------------------------------- Boolean Equation Segment ------EQUATIONS

; Serial shift register; When CS_EL_b is inactive (1), no change; When CS_EL_b is active (0), shift in dataAN83REV3 33

AN83Q20 := (Q20 * CS_EL_b) + (/CS_EL_b * SDATA)Q21 := (Q21 * CS_EL_b) + (/CS_EL_b * Q20)Q22 := (Q22 * CS_EL_b) + (/CS_EL_b * Q21)Q23 := (Q23 * CS_EL_b) + (/CS_EL_b * Q22)

; Decode logic

EQUALL = (Q20:*:LA20) * (Q21:*:LA21) ; :*: -> Exclusive NOR operatorEQUALH = (Q22:*:LA22) * (Q23:*:LA23)ADD_VALID = /RESET * CS_EL_b * ADD_VALID ; stay clear till any write + /RESET * /CS_EL_b ; Set when address write + /RESET * ADD_VALID ; Remain set until reset

CHIPSEL_b = RESET ; Get set at RESET+ /ADD_VALID ; Remain set till address is valid+ (/ALE * CHIPSEL_b ; Do not change when ALE is LOW+ (ALE * /(EQUALL * EQUALH)) ; Clear during ALE if address matches

; When ALE is active; CS_b goes active if EQUAL[1:2] are true; When ALE is inactive; previous state of CS_b is latched.

Figure 23. PAL Program34 AN83REV3

AN83Layout Considerations for the CS8900AThe CS8900A is a mixed signal device having dig-ital and analog circuits for an Ethernet communica-tion. While doing the PCB layout and signalconnections, it is important to take the followingprecautions:

- Provide a low inductive path to reduce power and ground connection noise.

- Provide proper impedance matching especially to the Ethernet analog signals.

- Provide low inductive path, wider and short traces, for all analog signals.

It is important that a PCB designer follow sugges-tions made in this document for proper and reliableoperation of the CS8900A. These guidelines willalso benefit the design with good EMI test results.

General GuidelinesFigure 24 shows component placement for an ISACOMBO Ethernet adapter card using a CS8900A.The placement of the CS8900A should be such thatthe routes of the analog signals and the digital sig-nals are not intermixing. No signal should routebeneath the CS8900A on any plane.

Power Supply ConnectionsThe CS8900A has 3 analog and 4 digital power pinpairs (Vcc and GND). Additional ground connec-tions are provided. Each power pin pair should beconnected to a 0.1 F bypass capacitor. Connectthe extra ground pins directly the ground plane.

Two Layered Printed Circuit Board (PCB)A two layered PCB has signal traces on the compo-nent and solder side of the PCB. Fill unused areaswith copper planes. Typically, planes on the com-ponent side of the PCB are connected to groundand those on the solder side are connected to VCCor +5 volts.Provide each pair of power pin with a 0.1 F bypasscapacitor. Place each bypass capacitor as close aspossible to the corresponding power pin pair. Con-

nect the capacitor to the pads of the power pins byshort, wide traces, the other end of these tracesshould be connected to VCC and GND planes. Fig-ure 19 and Figure 20 illustrate ground and power(Vcc) plane connections, respectively.Multi-layered Printed Circuit BoardA multi-layered printed circuit board (PCB) typi-cally has separate ground and power (Vcc) planes.Multi-layered PCBs are required when the compo-nent and trace density is high. Often discrete com-ponents like resistors and capacitors are placed onthe solder side of a printed circuit board.For a multi-layer PCB with all components on oneside of the board, follow the power connectionguide lines as explained in Two Layered PrintedCircuit Board (PCB) on page 35. Instead of con-necting the ground and Vcc to the copper fills onthe component and solder side of the board, con-nect them to the internal ground and Vcc planes.Figures 27 through 30 show the four layers of thefour-layer card.For a multi-layered board the discrete componentsare to be placed on the solder side of the PCB, by-pass capacitors for the CS8900A can be placed onthe solder side of the PCB. Each bypass capacitorshould be placed beneath the CS8900A and closestto its corresponding power pin pair. Figures 31and 32 illustrate the placement and routing of onebypass capacitor.

Routing of the Digital SignalsMost of the digital signals from the CS8900A go tothe ISA bus connector. Route these signals directlyto the connector. Isolate the digital signals fromanalog signals.

Routing of the Analog SignalsRouting of the clock signals: Place the20.000 MHz crystal within one inch of XTL1 (pin#97) and XTL2 (pin #98) pins of the CS8900A.AN83REV3 35

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Figure 24. General placement on an ISA adapter card36 AN83REV3

AN83Figure 25. Placement of Components, Top Side

CS8

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AN83Figure 26. Placement of Components, Solder Side

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AN83Figure 2.4.6. Component (top) side of four-layer boardFigure 27. Component (top) side of four-layer boardAN83REV3 39

AN83Figure 2.4.7. +5V Plane of four-layer boardFigure 28. +5V Plane of four-layer board40 AN83REV3

AN83Figure 2.4.8. Ground Plane of four-layer boardFigure 29. Ground Plane of four-layer boardAN83REV3 41

AN83Figure 2.4.9. Solder side (bottom) of four-layer boardFigure 30. Solder side (bottom) of four-layer board42 AN83REV3

AN83The 20.000 MHz crystal traces should be short,have no via, and run on the component side.Biasing resistor at RES pin of the CS8900A: A4.99 K resistor is connected between pins RES(pin #93) and AVSS3 (pin #94) of the CS8900A.This resistor biases internal analog circuits of theCS8900A, and should be placed as close as possi-ble to RES pin (pin #93) of the CS8900A.Routing of the 10BASE-T signals: Four signalsare used for 10BASE-T communication, two dif-

ferential transmit signals and two differential re-ceive signals. An isolation transformer is placedbetween the transmit and receive traces and a RJ-45(modular phone jack) connector. The isolationtransformer should be placed as close as possible tothe RJ-45 connector. Both transmit and receivesignal traces should be routed so they are paralleland of equal length. The signal traces should be onthe component side and should have direct andshort paths. The widths of the receive signal tracesshould at least be 25 mil. while widths of the trans-

Figure 31. Placement of Decoupling Capacitor (Bottom side, under CS8900A)

Figure 32. Routing of Decoupling Capacitor (Top side, component side)AN83REV3 43

AN83mit signal traces should be at least 100 mil. Thiswill provide a good impedance matching for thetransmit and receive circuitry inside the CS8900A.A ground trace should be run parallel to the trans-mit traces. Also, a ground plane should run under-neath the transmit and receive traces on the solderside of a two layered PCB. Please refer to the Fig-ures 33 and 34 for illustration of the above guidelines.Routing of the AUI signals: The CS8900A hasthree pairs of differential signals connecting it to anAuxiliar