csci 641 – eeng 641 1 csci-641/eeng-641 computer architecture khurram kazi

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  • Slide 1
  • CSCI 641 EENG 641 1 CSCI-641/EENG-641 Computer Architecture Khurram Kazi
  • Slide 2
  • Course Outline CSCI 641 EENG 641 2 Studying Computer architecture from different perspective Processors such as General Purpose Processors (RISC) Specialty processors (Network Processors, security processors ) Single Board Computers Typical PC architecture Buses (AMBA Bus) Memory architectures SRAM, DRAM, Non-volatile RAM (Flash, SD Card), Hard Disk Addressing Inputs/Outputs USB, HDMI, Video Port, Mouse, Keyboard Hardware design simulations VHDL (VHSIC Hardware Description Language) Firmware Assembly Language Assembly Language Hardware functional blocks
  • Slide 3
  • Desired outcomes CSCI 641 EENG 641 3 Have a solid fundamental understanding of processors architectures Memory and I/O architectures Instruction level parallelism and related it to pipelining Calculate the throughput with and without stalls Hardware and Assembly language design fundamentals Using processors to build single board computers Partitioning of a design in hardware and firmware/software
  • Slide 4
  • Recommend Books CSCI 641 EENG 641 4 1.Computer Architecture: A Quantitative Approach, 4 th Edition, Morgan Kaufman Publishers, Elsevier, 2007, ISBN: 0-12-370490-1 2.Digital Design and Computer Architecture, David Harris and Sarah Harris, Elsevier, 2007, ISBN 13: 978-0-120370497-9 3.HDL Programming Fundamentals; VHDL and Verilog, Nazeih, B. Botros, Da Vinci Engineering Press, 2006, ISBN: 1-58450-855-8
  • Slide 5
  • Software Tools Used CSCI 641 EENG 641 5 Mentor Graphics ModelSim VHDL simulator You can download student version of it from http://model.com/content/modelsim-pe-student- edition-hdl-simulation Will be using it extensively RISC instruction set simulator http://sourceforge.net/projects/spimsimulator/files/
  • Slide 6
  • Grading Policy CSCI 641 EENG 641 6 Homework/Short Quizzes 30% 1 Midterm Test30% Final Project40% Will start to discuss Final Projects towards the mid-semester Oral and written communication skills will be stressed in this course and taken into account in the final grade Cheating/ plagiarism Automatic F
  • Slide 7
  • CSCI 641 EENG 641 7 Dos and Donts for the Final Project DO NOT use any off the shelf general purpose microprocessor or any other circuit taken from the publicly available information base and claim it is your work. I will know if you did!! Come up with your own functional idea and Implement it. Be creative ! Have a systems perspective and see how your design fits in the system. By mid semester have a good idea of your project Team of 2 students working on the same project is allowed. Each team members task within the project should be explicitly defined.
  • Slide 8
  • CSCI 641 EENG 641 8 Teamwork Encouraged: How much collaboration is acceptable Since time will be short, I would encourage you to help out your fellow students with the Usage of the Tools but not the Design. Informing me of the help received is strongly encouraged, i.e. give credit where credit is due!! Helping fellow students with Tools usage and class participation will be rewarded in the final grade.
  • Slide 9
  • CSCI 641 EENG 641 9 Block Diagram of a Generic Processor
  • Slide 10
  • CSCI 641 EENG 641 10 Basic Microcomputer Design Clock: Synchronizes internal operations of the CPU with other components of the system ALU: performs arithmetic operations such as +, -, *, /, and logic operations such as AND, OR, NOT Memory Storage: Instructions and data are held while computer program is running. Receives request for data from CPU, transfers data from RAM to CPU, or CPU into memory Bus: is a group of wires that transfer data from one part of the computer to another. Data bus: transfers instructions and data between CPU and memory Control bus: synchronizes actions of all devices attached to the system bus Address bus: holds address of the instructions and data when the currently executing instruction transfers data between CPU and memory
  • Slide 11
  • CSCI 641 EENG 641 11 Instruction Execution Cycle Fetch: The control unit fetches instruction from instruction queue and increments the instruction pointer (IP), AKA, Program Counter Decode: Control Unit decodes the instructions function to determine what the instruction will do and sends the appropriate signals to the ALU Fetch Operands: If instruction uses an input operand located in memory, the control unit uses a read operation to retrieve the operand and copy it into internal registers. Execute: ALU executes the instruction using the named registers and internal registers as operands and sends the output to the named registers and/or memory. ALU then updates status flags to indicate the processor state Store output operand: If the output operand is in memory, the control unit uses a write operation to store the data
  • Slide 12
  • CSCI 641 EENG 641 12 Testbench (Generator In C or HDL) Testbench (Analyzer In C or HDL) HDL Design (VHDL or Verilog Reference Model ( In C or Functional HDL) HDL (Hardware Description Language) can typically be either VHDL or Verilog Typical HDL Design Environment
  • Slide 13
  • CSCI 641 EENG 641 13 Overview of VHDL Library and Library Declarations Entity Declaration Architecture Configuration
  • Slide 14
  • CSCI 641 EENG 641 14 Overview of VHDL Package (typically compiled into the destination library) contains commonly used declarations Constants maybe defined here Enumerated data types (Red, Green, Blue) Combinatorial functions (performing a decode function; returns single value) Procedures (can return multiple values) Component declarations
  • Slide 15
  • CSCI 641 EENG 641 15 Overview of VHDL Package (typically compiled into the destination library) contains commonly used declarations Constants maybe defined here Enumerated data types (Red, Green, Blue) Combinatorial functions (performing a decode function; returns single value) Procedures (can return multiple values) Component declarations
  • Slide 16
  • CSCI 641 EENG 641 16 Overview of VHDL: Example of Library Declaration LIBRARY library_name;--comments USE library_name.package_name.package_parts;-- VHDL is case -- insesitive Typically there are three different libraries used in a design 1) ieee.std_logic_1164 (from the ieee library) 2) standard (from the std library) 3) work ( work library) std_logic_1164 : Specifies the STD_LOGIC (8 levels) and the STD_ULOGIC (9 levels) multi-values logic systems std : It is a resource library (data types, text i/o, etc.) work : This is where the design is saved Library ieee;-- A semi-colon (;) indicates the end of a statement or a declaration USE ieee.std_logic_1164.all;-- double dash indicates a comment. Library std; USE std.standard.all; Library work; USE work.all;
  • Slide 17
  • CSCI 641 EENG 641 17 Overview of VHDL: Entity Entity Defines the component name, its inputs and outputs (I/Os) and related declarations. Can use same Entity for different architecture to study various design trade offs. Use std_logic and std_logic_vector(n downto 0) : they are synthesis friendly. Avoid enumerated type of I/Os. Avoid using port type buffer or bidir (unless you have to)
  • Slide 18
  • CSCI 641 EENG 641 18 Overview of VHDL: Syntax of an Entity 1.ENTITY entity_name IS PORT ( port_name: signal_modesignal type; .); END entity_name; 2.ENTITY nand_gate IS PORT ( a:INstd_logic; b:INstd_logic; x:OUTstd_logic); END nand_gate; or 3.ENTITY FiveInput_nand_gate IS PORT ( a:INstd_logic_vector (4 downto 0); x:OUTstd_logic); END FiveInput_nand_gate;
  • Slide 19
  • CSCI 641 EENG 641 19 Overview of VHDL: Architecture Architecture Defines the functionality of the design Normally consists of processes and concurrent signal assignments Synchronous and/or combinatorial logic can be inferred from the way functionality is defined in the Processes. Avoid nested loops Avoid generate statements with large indices Always think hardware when developing code! One way of looking at is how would you implement the digital design on the breadboard; mimic the same thought process in writing VHDL code
  • Slide 20
  • CSCI 641 EENG 641 20 Overview of VHDL: Syntax of an Architecture ARCHITECTURE architecture_name OF entity_name IS [declarations] BEGIN (code) END architecture_name; ARCHITECTURE myarch OF nand_gate IS BEGIN x

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