cse 260 – digital computers: organization and logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1...

21
- 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold. entity cpu ... end cpu; architecture cpuArch of cpu is type state_type is ( resetState, pauseState, fetch, halt, negate, nott, branch, brZero, brPos, brNeg, brInd, mLoad, dLoad, iLoad, dispLoad, dStore, iStore, dispStore, add, andd, orr, lshift, rshift ); ... begin ... alu <= (not acc) + x"0001" when state = negate else not acc when state = nott else acc + dbus when state = add else acc and dbus when state = andd else acc or dbus when state = orr else leftShift(acc, dbus(3 downto 0)) when state = lshift and dBus(15 downto 4) = "x"000" else rightShift(acc, dbus(3 downto 0)) when state = rshift and dBus(15 downto 4) = "x"000" else (alu'range => '0'); process (clk) function decode(instr: word) return state_type is begin -- Instruction decoding. case instr(15 downto 12) is when x"0" => case instr(11 downto 8) is when x"0" => if instr(11 downto 0) = x"000" then return halt; elsif instr(11 downto 0) = x"001" then CSE 260 – Digital Computers: Organization and Logical Design Design Problem 5 Solutions Jon Turner

Upload: others

Post on 17-Apr-2020

1 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 1 -

The modifications to the CPU VHDL appear below, with the changes shown in bold.

entity cpu ... end cpu; architecture cpuArch of cpu is type state_type is ( resetState, pauseState, fetch, halt, negate, nott, branch, brZero, brPos, brNeg, brInd, mLoad, dLoad, iLoad, dispLoad, dStore, iStore, dispStore, add, andd, orr, lshift, rshift ); ... begin ... alu <= (not acc) + x"0001" when state = negate else not acc when state = nott else acc + dbus when state = add else acc and dbus when state = andd else acc or dbus when state = orr else leftShift(acc, dbus(3 downto 0)) when state = lshift and dBus(15 downto 4) = "x"000" else rightShift(acc, dbus(3 downto 0)) when state = rshift and dBus(15 downto 4) = "x"000" else (alu'range => '0'); process (clk) function decode(instr: word) return state_type is begin -- Instruction decoding. case instr(15 downto 12) is when x"0" => case instr(11 downto 8) is when x"0" => if instr(11 downto 0) = x"000" then return halt; elsif instr(11 downto 0) = x"001" then

CSE 260 – Digital Computers: Organization and Logical Design Design Problem 5 Solutions

Jon Turner

Page 2: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 2 -

return negate; elsif instr(11 downto 0) = x"002" then return nott; else return halt; end if; when x"1" => return branch; ... when others => return halt; end case; .... when x"c" => return andd; when x"d" => return orr; when x"e" => return lshift; when x"f" => return rshift; when others => return halt; end case; end function decode; begin if rising_edge(clk) then if reset = '1' then ... else tick <= tick + 1; -- advance time by default if state = resetState then state <= fetch; tick <= x"0"; elsif state = pauseState then ... elsif state = fetch then ... else case state is when negate | nott => acc <= alu; wrapup; ... -- arithmetic and logic instructions when add | andd | orr | lshift | rshift => if tick = x"1" then acc <= alu; wrapup; end if; when others => state <= halt; end case; end if; end if; end if; end process; process (ireg,pc,iar,acc,pcTop,state,tick) begin -- Memory control section (combinational) -- default values for memory control signals en <= '0'; rw <= '1'; aBus <= (others => 'Z'); dBus <= (others => 'Z'); case state is

Page 3: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 3 -

when fetch => ... when brInd => ... when dLoad | add | andd | orr | lshift | rshift => if tick = x"0" then en <= '1'; aBus <= pcTop & iReg(11 downto 0); end if; ... when others => end case; end process; end cpuArch;

Page 4: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 4 -

The modifications to commonDefs.vhd are shown below.

library IEEE; ... package commonDefs is constant wordSize: integer := 16; ... function leftShift(x: word; s: std_logic_vector(3 downto 0)) return word; -- Return value obtained by shifting x to the left by s bits. -- Fill with zeros. function rightShift(x: word; s: std_logic_vector(3 downto 0)) return word; -- Return value obtained by shifting x to the right by s bits. -- Fill with zeros. end package commonDefs; ... package body commonDefs is ... function leftShift(x: word; s: std_logic_vector(3 downto 0)) return word is ... return x1; end function leftShift; function rightShift(x: word; s: std_logic_vector(3 downto 0)) return word is -- Return value obtained by shifting x to the left by s bits. -- Fill with zeros. variable x8, x4, x2, x1: word; begin if s(3) = '1' then x8 := x"00" & x(15 downto 8); else x8 := x; end if; if s(2) = '1' then x4 := x"0" & x8(15 downto 4); else x4 := x8; end if; if s(1) = '1' then x2 := "00" & x4(15 downto 2); else x2 := x4; end if; if s(0) = '1' then x1 := "0" & x2(15 downto 1); else x1 := x2; end if; return x1; end function rightShift; end package body commonDefs;

Page 5: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 5 -

The modifications to console.vhd appear below.

entity console ... end console; architecture a1 of console is ... begin ... process(clk) begin if rising_edge(clk) then prevDBtn <= dBtn; end if; end process; -- process for controlling single step operation process(clk) begin ... end process; ... -- snooping process process(clk) begin if rising_edge(clk) then memEn <= '0'; memRw <= '1'; aBus <= (others => 'Z'); dBus <= (others => 'Z'); if reset = '1' then ... else ... -- update snoopAdr or snoopData in response to knob signals if tick = '1' then if knobMode = '0' then if clockwise = '1' then snoopAdr <= snoopAdr + delta; else snoopAdr <= snoopAdr - delta; end if; else if clockwise = '1' then snoopData <= snoopData+delta; else snoopData <= snoopData - delta; end if; -- if snoopData changes when swt(2) is high and no -- write is currently in progress, request a write if swt(2) > writing then writeReq <= '1'; end if; end if; end if; end if; end if; end process; selekt <= dispCntr(4 downto 0); -- process for updating display process(clk) begin ... end process; end a1;

Page 6: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 6 -

The program is shown below, with additions highlighted in bold.

-- mazeRunner() -- ... -- while (true) 16#1039# => x"2001", -- if (M[1001] >> 8) <= 31 then 16#103a# => x"f0a7", -- 16#103b# => x"50ac", -- 16#103c# => x"80ab", -- 16#103d# => x"0303", -- 16#103e# => x"20ac", -- x = (M[1001] >> 8) 16#103f# => x"50a2", -- 16#1040# => x"2001", -- if (M[1001] & xff) <= 23 then 16#1041# => x"c0a9", -- 16#1042# => x"50ac", -- 16#1043# => x"80aa", -- 16#1044# => x"0303", -- 16#1045# => x"20ac", -- y = (M[1001] & xff) 16#1046# => x"50a3", -- 16#1047# => x"20a2", -- if x != oldx or y != oldy then 16#1048# => x"0001", -- 16#1049# => x"80a4", -- 16#104a# => x"0202", -- 16#104b# => x"0105", -- 16#104c# => x"20a3", -- 16#104d# => x"0001", -- 16#104e# => x"80a5", -- 16#104f# => x"0229", -- 16#1050# => x"20a4", -- eraseCursor(oldx, oldy, lc, bc) 16#1051# => x"605c", -- 16#1052# => x"20a5", -- 16#1053# => x"605d", -- 16#1054# => x"20a0", -- 16#1055# => x"605e", -- 16#1056# => x"20a1", -- 16#1057# => x"605f", -- 16#1058# => x"2061", -- 16#1059# => x"6060", -- 16#105a# => x"0501", -- 16#105b# => x"1505", -- 16#105c# => x"1500", -- 16#105d# => x"1501", -- 16#105e# => x"1502", -- 16#105f# => x"1503", -- 16#1060# => x"1504", -- 16#1061# => x"1062", --

Page 7: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 7 -

16#1062# => x"20a2", -- showCursor(x, y, lc, bc) 16#1063# => x"606e", -- 16#1064# => x"20a3", -- 16#1065# => x"606f", -- 16#1066# => x"20a0", -- 16#1067# => x"6070", -- 16#1068# => x"20a1", -- 16#1069# => x"6071", -- 16#106a# => x"2073", -- 16#106b# => x"6072", -- 16#106c# => x"0501", -- 16#106d# => x"1405", -- 16#106e# => x"1400", -- 16#106f# => x"1401", -- 16#1070# => x"1402", -- 16#1071# => x"1403", -- 16#1072# => x"1404", -- 16#1073# => x"1074", -- 16#1074# => x"20a2", -- oldx = x; oldy = y 16#1075# => x"50a4", -- 16#1076# => x"20a3", -- 16#1077# => x"50a5", -- 16#1078# => x"0002", -- bitwise complement - just for testing 16#1079# => x"01c0", -- end loop 16#10a0# => x"0000", -- lc 16#10a1# => x"0000", -- rc 16#10a2# => x"0000", -- x 16#10a3# => x"0000", -- y 16#10a4# => x"0000", -- oldx 16#10a5# => x"0000", -- oldy 16#10a6# => x"0007", -- constant 7 16#10a7# => x"0008", -- constant 8 16#10a8# => x"0017", -- constant 23 16#10a9# => x"00ff", -- constant xff 16#10aa# => x"ffe9", -- constant -23 (-x17) 16#10ab# => x"ffe1", -- constant -31 (-x1f) 16#10ac# => x"001f", -- temporary -- writeMaze(lc, bc) -- ... -- random() -- ... -- writeSquare(x, y, type, lc, bc) -- ...

Page 8: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 8 -

16#1322# => x"2304", -- blankLine = (bc << 12) | (bc << 9) | 16#1323# => x"e376", -- (bc << 6) | (bc << 3) | bc 16#1324# => x"d304", -- 16#1325# => x"e376", -- 16#1326# => x"d304", -- 16#1327# => x"e376", -- 16#1328# => x"d304", -- 16#1329# => x"e376", -- 16#132a# => x"d304", -- 16#132b# => x"5373", -- 16#132c# => x"2302", -- if type = 0 then ... 16#1349# => x"2372", -- else *p = leftLine; p += x20; 16#134a# => x"6370", -- 16#134b# => x"1020", -- 16#134c# => x"8370", -- 16#134d# => x"5370", -- 16#134e# => x"2372", -- *p = leftLine; p += x20; 16#134f# => x"6370", -- 16#1350# => x"1020", -- 16#1351# => x"8370", -- 16#1352# => x"5370", -- 16#1353# => x"2372", -- *p = leftLine; p += x20; 16#1354# => x"6370", -- 16#1355# => x"1020", -- 16#1356# => x"8370", -- 16#1357# => x"5370", -- 16#1358# => x"2372", -- *p = leftLine; p += x20; 16#1359# => x"6370", -- 16#135a# => x"1020", -- 16#135b# => x"8370", -- 16#135c# => x"5370", -- 16#135d# => x"2372", -- *p = leftLine; p += x20; 16#135e# => x"6370", -- 16#135f# => x"1020", -- 16#1360# => x"8370", -- 16#1361# => x"5370", -- 16#1362# => x"05a3", -- return 16#1370# => x"F000", -- p 16#1371# => x"0000", -- topline 16#1372# => x"0000", -- leftline 16#1373# => x"0000", -- blankline 16#1374# => x"0001", -- constant 1 16#1375# => x"0002", -- constant 2 16#1376# => x"0003", -- constant 3 16#1377# => x"0005", -- constant 5 16#1378# => x"f000", -- start of display buffer

Page 9: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 9 -

-- showCursor(x, y, lc, bc) -- p = xF000 + (y * xA0) + x + x40 -- line = (*p & xfe07) | (lc << 6) | (lc << 3) -- *p = line -- p += x20 -- line = (*p & xfe07) | (lc << 6) | (lc << 3) -- *p = line -- return -- .... -- eraseCursor(x, y, lc, bc) -- p = xF000 + (y * xA0) + x + x40 -- line = (*p & xfe07) | (bc << 6) | (bc << 3) -- *p = line -- p += x20 -- line = (*p & xfe07) | (bc << 6) | (bc << 3) -- *p = line -- return -- 16#1500# => x"0000", -- x 16#1501# => x"0000", -- y 16#1502# => x"0000", -- line color 16#1503# => x"0000", -- background color 16#1504# => x"0000", -- return address 16#1505# => x"2501", -- p = xF000 + (y * xA0) + x + x40 16#1506# => x"e532", -- 16#1507# => x"8501", -- 16#1508# => x"e534", -- 16#1509# => x"8500", -- 16#150a# => x"8535", -- 16#150b# => x"5530", -- 16#150c# => x"3530", -- line = (*p & xfe07) | (bc << 6) | (bc << 3) 16#150d# => x"c536", -- 16#150e# => x"5531", -- 16#150f# => x"2503", -- 16#1510# => x"e533", -- 16#1511# => x"d503", -- 16#1512# => x"e533", -- 16#1513# => x"d531", -- 16#1514# => x"5531", -- 16#1515# => x"6530", -- *p = line 16#1516# => x"1020", -- p += x20 16#1517# => x"8530", -- 16#1518# => x"5530", -- 16#1519# => x"3530", -- line = (*p & xfe07) | (bc << 6) | (bc << 3) 16#151a# => x"c536", -- 16#151b# => x"5531", --

Page 10: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 10 -

16#151c# => x"2503", -- 16#151d# => x"e533", -- 16#151e# => x"d503", -- 16#151f# => x"e533", -- 16#1520# => x"d531", -- 16#1521# => x"5531", -- 16#1522# => x"6530", -- *p = line 16#1523# => x"05e1", -- return 16#1530# => x"0000", -- p 16#1531# => x"0000", -- line 16#1532# => x"0002", -- constant 2 16#1533# => x"0003", -- constant 3 16#1534# => x"0005", -- constant 5 16#1535# => x"f040", -- constant xf040 16#1536# => x"fe07", -- constant xfe07

Page 11: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 11 -

The testbench appears below.

------------------------------------------------------------------------- -- Testbench for top level circuit -- Jon Turner - 10/2010 -- -- This just resets the processor and lets a memory-resident program run. ------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.commondefs.all; entity testtop is end testtop; architecture behavior of testtop is component top is port( clk: in std_logic; btn: in buttons; knob: in knobsigs; swt: in switches; led: out leds; -- signals for controlling lcd display lcd: out lcdsigs; -- vga signals hsync, vsync: out std_logic; dispval: out std_logic_vector(2 downto 0)); end component; --inputs signal clk : std_logic := '0'; signal btn : buttons; signal knob: knobsigs := (others => '0'); signal swt : switches := (others => '0'); signal rot: std_logic_vector(1 downto 0); signal press: std_logic; signal reset, load: std_logic; --outputs signal led : leds;

Page 12: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 12 -

signal lcd : lcdsigs; signal hsync, vsync: std_logic; signal dispval: std_logic_vector(2 downto 0); -- clock period definitions constant clkP : time := 20 ns; constant pause : time := 100 ns; begin -- instantiate the unit under test (uut) uut: top port map ( clk, btn, knob, swt, led, lcd, hsync, vsync, dispval ); -- clock process definitions process begin clk <= '0'; wait for clkP/2; clk <= '1'; wait for clkP/2; end process; knob(2 downto 1) <= rot; knob(0) <= press; btn(0) <= reset; btn(1) <= load; btn(3 downto 2) <= "00"; process begin reset <= '0'; load <= '0'; swt <= "0000"; rot <= "00"; press <= '0'; wait for pause; reset <= '1'; wait for pause; reset <= '0'; wait for 30 ms; -- leave time for maze to be displayed -- set snoopAdr = 1000 press <= '1'; wait for pause; press <= '0'; wait for pause; press <= '1'; wait for pause; press <= '0'; wait for pause; press <= '1'; wait for pause; press <= '0'; wait for pause; for i in 1 to 1 loop rot <= "01"; wait for pause; rot <= "11"; wait for pause; rot <= "10"; wait for pause; rot <= "00"; wait for 2 ms; end loop; press <= '1'; wait for pause; press <= '0'; wait for pause; -- modify both bytes of snoopData and load M[1000] swt(3) <= '1'; wait for pause; for i in 1 to 1 loop rot <= "10"; wait for pause; rot <= "11"; wait for pause; rot <= "01"; wait for pause; rot <= "00"; wait for 2 ms;

Page 13: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 13 -

end loop; press <= '1'; wait for pause; press <= '0'; wait for pause; press <= '1'; wait for pause; press <= '0'; wait for pause; for i in 1 to 1 loop rot <= "01"; wait for pause; rot <= "11"; wait for pause; rot <= "10"; wait for pause; rot <= "00"; wait for 2 ms; end loop; press <= '1'; wait for pause; press <= '0'; wait for pause; press <= '1'; wait for pause; press <= '0'; wait for pause; load <= '1'; wait for pause; load <= '0'; wait for 5 us; -- set snoopAdr = 1001 swt(3) <= '0'; wait for pause; for i in 1 to 1 loop rot <= "01"; wait for pause; rot <= "11"; wait for pause; rot <= "10"; wait for pause; rot <= "00"; wait for 2 ms; end loop; -- now move cursor around swt(3 downto 2) <= "11"; for i in 1 to 3 loop rot <= "01"; wait for pause; rot <= "11"; wait for pause; rot <= "10"; wait for pause; rot <= "00"; wait for 2 ms; end loop; press <= '1'; wait for pause; press <= '0'; wait for pause; press <= '1'; wait for pause; press <= '0'; wait for pause; for i in 1 to 5 loop rot <= "01"; wait for pause; rot <= "11"; wait for pause; rot <= "10"; wait for pause; rot <= "00"; wait for 2 ms; end loop; for i in 1 to 2 loop rot <= "10"; wait for pause; rot <= "11"; wait for pause; rot <= "01"; wait for pause; rot <= "00"; wait for 2 ms; end loop; press <= '1'; wait for pause; press <= '0'; wait for pause; press <= '1'; wait for pause; press <= '0'; wait for pause; for i in 1 to 1 loop rot <= "10"; wait for pause; rot <= "11"; wait for pause; rot <= "01"; wait for pause; rot <= "00"; wait for 2 ms; end loop; -- regenerate maze in new colors reset <= '1'; wait for pause; reset <= '0'; wait for 30 ms; -- leave time for maze to be displayed assert (false) report "simulation ended normally." severity failure; end process; end;

Page 14: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 14 -

An overview of the simulation appears below. At the bottom left, we see the snoop address and data registers plus four pairs of monitoring registers. The first pair shows the values in M[1000], M[1001]. These are the locations used to input the color values and the x, y coordinates of the cursor. The second pair of monitoring registers shows the values in M[10a0] and M[10a1]. These locations are used by the program to store the color values separately. The next pair shows M[1140] and M[1141] which are used to store the x and y positions of the maze square being written (not the cursor values). The last pair shows all values written to the display buffer and the address at which they are written. In the first part of the output, we can see where the maze is being written when the program starts. In the center section, the color values are changed and the cursor is moved in both the x and y directions, resulting in updates to the display buffer to show the cursor position. In the right-hand section, a new maze is written using the new colors.

Page 15: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 15 -

This section is a closeup of the first part of the simulation. At this scale, all we can really observe is the updating of the y values as the maze is being written.

Page 16: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 16 -

Here, we see a more detailed view that shows the writing of several blocks of the maze. Note the changing x and y values. While we can’t see the details of each word, we can clearly see the address and data for the last word of each block. So we can see that the first of the two blocks circled has a last line that’s all white (implying that the line is at the top of the block), while the second has a black pixel at left, indicating that the block has a line on the left side.

Page 17: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 17 -

Here we have a more detailed view, showing all words of one block being written.

Page 18: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 18 -

Here we see the detail of the initial writing of the cursor after the last block of the maze is written.

Page 19: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 19 -

This section shows M[1001] responding continuously as the knob is being turned to change snoopData. We can also observe the program making changes to the display buffer, in response to the changes in M[1001]. While we can’t see the erasing of the old cursor values at this time scale, we can see the update to the second word of the new cursor locations.

Page 20: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 20 -

Here is a more detailed view showing the display buffer being updated to show cursor movement.

Page 21: CSE 260 – Digital Computers: Organization and Logical ...jst/cse/260/labs/2010/dp5sol.pdf · - 1 - The modifications to the CPU VHDL appear below, with the changes shown in bold

- 21 -

This final section shows the first block of the new maze being written. Note that the new colors (1, 6) are being used this time around.