CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab

Flip Flops

Tajana Simunic Rosing

1Source: Vahid, Katz

Timing: Definitionsg

T TT su 1 8

T h 0 5

D

T su 1.8ns

T h 0.5ns

T w 3 3

1.8ns

0.5 ns

T w 3 3

Clk

Q

3.3 ns

T pd3 6

T pd3.6 ns 1.1 ns

3.3 ns

dataD Q D Q• Cascaded FFs:

3.6 ns 1.1 ns

1.1 ns

clock

– Tpd > Th– Tperiod > Tpd + Tsu

2

Clock skewD-FF original state: IN = 0, Q0 = 1, Q1 = 1due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

CLK0

IND Q D Q

CLK1

100

CLK1 is a delayedversion of CLK0

InQ0Q1

CLK0CLK1

• Cascaded FFs:

3

– Tpd > Tskew + Th– Tperiod + Tskew > Tpd + Tsu

Metastabilityyclk

D

ai

D

setup timeviolation

ai

Q

violation

metastable

synchronizer

• Violating setup/hold time can lead to a metastable state– Metastable state: Any flip-flop state other than a stable 1 or 0

E ll l h b d ’ k hi h

metastablestate

• Eventually settles to one or other, but we don’t know which– Fix: for internal circuits make sure to observe setup time; not possible for external

inputs (e.g. button press)• Partial solution

a

4

– Insert synchronizer flip-flop for asynchronous input• flip-flop w very small setup/hold time, but doesn’t completely prevent metastability

Metastabilityy

veryProbability of flip-flop being metastable is…

ai

lowverylow

verylow

incrediblylow

synchronizers

• One flip-flop doesn’t completely solve problemp p p y p– Add more synchronizer flip-flops to decrease the probability of

metastability– Can’t solve completely – just decrease the likelihood of failure

5

Can t solve completely just decrease the likelihood of failure

Metastability and asynchronous inputsy y p

• Clocked synchronous circuits– inputs, state, and outputs sampled or changed in relation to a clock– e.g., edge-triggered FFs

• Asynchronous circuitsAsynchronous circuits– inputs, state, and outputs sampled or changed independently of a

common reference signal (glitches/hazards a major concern)e g R S latch– e.g., R-S latch

• Asynchronous inputs to synchronous circuits– inputs can change at any time, will not meet setup/hold times– dangerous, synchronous inputs are greatly preferred– cannot be avoided (e.g., reset signal, memory wait, user input)

6

Synchronization failure

logic 1

y

logic 0 logic 1logic 0

small, but non-zero probability that the FF output will get stuck

in an in-between state

oscilloscope traces demonstratingsynchronizer failure and eventual

decay to steady statey y

• Occurs when FF input changes close to clock edge– the FF may enter a metastable state – neither a logic 0 nor 1 –

7

y g– it may stay in this state an indefinite amount of time– this is not likely in practice but has some probability

Dealing with synchronization failureg y• Reduce the probability of failure:

– (1) slow down the system clock (2) use fastest possible logic technology in the synchronizer(3) cascade two synchronizers

D DQ Qasynchronous

inputsynchronized

input

Clk

synchronous system

Clk

• (1) slow down the system clock: this gives the synchronizer more time to decay into a ( ) y g y ysteady state; synchronizer failure becomes a big problem for very high speed systems

• (2) use fastest possible logic technology in the synchronizerthis makes for a very sharp "peak" upon which to balance

8

this makes for a very sharp peak upon which to balance• (3) cascade two synchronizers

this effectively synchronizes twice (both would have to fail)

Handling asynchronous inputsClocked

Synchronous System

Synchronizer

g y p

D QQ0

Clock

Async Input

System

D QQ0

Clock

Async Input D Q

D Q

Clock

Cl k

Q1 D Q

Clock

Cl k

Q1

Clock Clock

In is asynchronous and fans out to D0 and D1

one FF catches the

In

Q0

9

one FF catches the signal, one does not

inconsistent state may be reached!

Q1

CLK

Glitchingg

• Glitch: Temporary values on outputs that appear soon after input changes, before stable new output values

• Designer must determine whether glitching outputs may pose a problempose a problem– If so, may consider adding flip-flops to outputs

• Delays output by one clock cycle, but may be OK

10

CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab

Counters and FSMs

Tajana Simunic Rosing

11Source: Vahid, Katz

Mobius Counter in Verilogg

D Q D Q D Q D Q

OUT1 OUT2 OUT3 OUT4

D Q D Q D Q D QIN

CLK

initialbegin

A = 1’b0;B = 1’b0;B = 1 b0;C = 1’b0;D = 1’b0;

end

always @(posedge clk)begin

A <= ~D;B <= A;C <= B;

12

C <= B;D <= C;

end

Light Game FSMg

• Tug of War gameTug of War game– 7 LEDs, 2 push buttons (L, R)

RESET

LED(3)

LED(2)

LED(1)

LED(0)

LED(6)

LED(5)

LED(4)

RRRRR

( ) ( ) ( ) ( )( ) ( ) ( )LLLLL

13

Light Game FSM Verilogg gmodule Light_Game (LEDS, LPB, RPB, CLK, RESET);

input LPB ;input RPB ; combinational logicinput RPB ;input CLK ;input RESET;output [6:0] LEDS ;

wire L, R;assign L = ~left && LPB;assign R = ~right && RPB;assign LEDS = position;

g

reg [6:0] position;reg left;reg right;

assign LEDS = position;

sequential logicreg right;

always @(posedge CLK)begin

left <= LPB;i hright <= RPB;

if (RESET) position <= 7'b0001000;else if ((position == 7'b0000001) || (position == 7'b1000000)) ;else if (L) position <= position << 1;else if (R) position <= position >> 1;

14

else if (R) position <= position >> 1; end

endmodule

Finite string pattern recognizer• Output a 1 when …010… appears in a bit string, and

stop when …100 appearsstop when …100 appears

S0[0]

10

reset

S4[0]

S1[0]

10

1 0...1...0

10

1

1...01

S2[0]

1

0

S5[0]

0

0...10

1

1

1

...010 ...1000 or 1S3

[1]

0 0

S6[0]

15

Finite string pattern recognizer in Verilogg p g g• Verilog description including state assignment

module string (clk, X, rst, Q0, Q1, Q2, Z);input clk, X, rst;

always @(posedge clk) beginif (rst) state = S0;

output Q0, Q1, Q2, Z;

parameter S0 = [0,0,0]; //reset stateparameter S1 = [0,0,1]; //strings ending in ...0parameter S2 = [0,1,0]; //strings ending in ...01

elsecase (state)

S0: if (X) state = S4 else state = S1;S1: if (X) state = S2 else state = S1;S2: if (X) state = S4 else state = S3;

parameter S3 = [0,1,1]; //strings ending in ...010parameter S4 = [1,0,0]; //strings ending in ...1parameter S5 = [1,0,1]; //strings ending in ...10parameter S6 = [1,1,0]; //strings ending in ...100

S3: if (X) state = S2 else state = S6;S4: if (X) state = S4 else state = S5;S5: if (X) state = S2 else state = S6;S6: state = S6;default: begin

reg state[0:2];

assign Q0 = state[0];assign Q1 = state[1];assign Q2 = state[2];

de au t: beg$display (“invalid state reached”);state = 3’bxxx;

endendcase

end

16

assign Q2 = state[2];assign Z = (state == S3);

end

endmodule

Controller Design3.4

g• Five step controller design process

17

Laser Timer3.3

• Pressing button (b) once turns on laser for 3 clock cycles

Controllerx

blasery

• Step 1: Capture the FSM clk

patient

clk

Inputs:b

Off OffOn1Off Off Off On2 On3OffState

Outputs:

b

x

18

Controller Design: Laser Timer Exampleg p• Step 1: Capture the FSM

– Already donex=0

b’00

Inputs: b; Outputs: x

y

• Step 2: Create architecture– 2-bit state register (for 4 states)

I t b t tx=1 x=1 x=1

b

b’

01

00

10 11On2On1

Off

On3– Input b, output x– Next state signals n1, n0

• Step 3: Encode the states

01 10 11On2On1 On3

xbSM

puts M putsp

– Any encoding with each state unique will work

a

Combinationallogic

s1 s0

n1

n0

FS inp

FS outp

State registerclk

19

Controller Design: Laser Timer Example (cont)g p ( )• Step 4: Create state table

x=0b’00

Off

Inputs: b; Outputs: x

x=1 x=1 x=1b

b

01 10 11On2On1

Off

On3

Combinational 1xb

FSM

nput

s FSMoutpu

Combinationallogic

State register

s1 s0

n1

n0

clk

in ts

20

Controller Design: Laser Timer Example (cont)g p ( )• Step 5: Implement

combinational logic Combinationallogic

n1xb

FSM

inpu

ts FSMoutputsg logic

State register

s1 s0n0

clk

x = s1 + s0

n1 = s1’s0b’ + s1’s0b + s1s0’b’ + s1s0’bn1 = s1’s0 + s1s0’

n0 = s1’s0’b + s1s0’b’ + s1s0’bn0 = s1’s0’b + s1s0’

21

Controller Design: Laser Timer Example (cont)g p ( )• Step 5: Implement

combinational logic (cont)C bi ti l

xb

FSM puts FSM

outpuCombinational Logic

b x

g ( )Combinational

logic

State register

s1 s0

n1

n0

clk

F in

Muts

n1FSM inputs

n0

s0s1

clk State register

x = s1 + s0n1 = s1’s0 + s1s0’n0 = s1’s0’b + s1s0’

22

Understanding the Controller’s Behaviorg

x=1 x=1 x=1b

Off00 b’x=0

bx=1 x=1 x=1

b’Off00x=0

x=1 x=1 x=1

x=0

b

b’00Off

b x

n1

01 10 11On2On1 On3

00 00

01

0

b x

n1

01 10 11On2On1 On3

000

b x

n1

01 10 11On2On1 On3

1 1110

n1

n0

0

00

0

0

1

0

0

10

n1

n0

n1

n00

1

0

00

s0s10 0

00

clk

clk

10

s0s1clk 0 0

state=00 state=00

s0s1clk 0 101

state=01clk

Inputs:

Outputs:b

x

23

x