cse477 l17 static sequential logic.1irwin&vijay, psu, 2003 cse477 vlsi digital circuits fall...

CSE477 L17 Static Sequential Logic.1 Irwin&Vijay, PSU, 2003

CSE477VLSI Digital Circuits

Fall 2003

Lecture 17: Static Sequential Circuits

Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477

[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]


Review: How to Choose a Logic Style

Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing

Style # Trans Ease Ratioed? Delay Power

Comp Static 8 1 no 3 1

CPL* 12 + 2 2 no 4 3

domino 6 + 2 4 no 2 2 + clk

DCVSL* 10 3 yes 1 4

4-input NAND

* Dual Rail

Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling.


A time was probably coming when components would operate so quickly that the distance that signals had to travel would intimately affect the speed of most commercial computers. Then miniaturization and speed would become more nearly synonymous.

The Soul of a New Machine, Kidder, pg. 160


Sequential Logic

CombinationalLogic

clock

Outputs

Sta

teR

egis

ters

NextState

CurrentState

Inputs


Timing Metrics

clock

In

Out

datastable

outputstable

outputstable

time

time

time

clock

D QIn Out

tsu thold

tc-q


System Timing Constraints

CombinationalLogic

clock

Outputs

Sta

teR

egis

ters

NextState

CurrentState

Inputs

T tc-q + tplogic + tsutcdreg + tcdlogic thold

T (clock period)


Static vs Dynamic Storage

Static storage preserve state as long as the power is on have positive feedback (regeneration) with an internal

connection between the output and the input useful when updates are infrequent (clock gating)

Dynamic storage store state on parasitic capacitors only hold state for short periods of time (milliseconds) require periodic refresh usually simpler, so higher speed and lower power


Latches vs Flipflops

Latches level sensitive circuit that passes inputs to Q when the clock is

high (or low) - transparent mode input sampled on the falling edge of the clock is held stable

when clock is low (or high) - hold mode

Flipflops (edge-triggered) edge sensitive circuits that sample the inputs on a clock

transition- positive edge-triggered: 0 1

- negative edge-triggered: 1 0

built using latches (e.g., master-slave flipflops)


Positive and Negative Latches

clock

D QIn Out

clock

D QIn Out

clk

Out

In

clk

Out

In


Review: The Regenerative Property

If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point.

A

Vi2 Vo2

Vi1 = Vo2

Vi2

= V

o1

B

C

Vo1Vi1

cascaded inverters


Bistable Circuits

The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states)

Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1

done by applying a trigger pulse at Vi1 or Vi2

the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter)

Two approaches used cutting the feedback loop (mux based latch) overpowering the feedback loop (as used in SRAMs)

Vi1

Vi2


Review (from CSE 271): SR Latch

S R Q !Q

0 0 Q !Q memory

1 0 1 0 set

0 1 0 1 reset

1 1 0 0 disallowed

S

RQ

!Q


Review (from CSE 271): Clocked D Latch

clock

D L

atch

QD

D

Q

!Q

clock

clock

transparent mode

hold mode


MUX Based Latches

Q

D

clk

0

1

Positive Latch

Q

D

clk

1

0

Negative Latch

Q = !clk & Q | clk & DQ = clk & Q | !clk & D

feedback

transparent when the clock is low

transparent when the clock is high

feedback

Change the stored value by cutting the feedback loop


TG MUX Based Latch Implementation

Q

D

clk

clk

!clk

!clk

clk

input sampled(transparent mode)

feedback(hold mode)

clk

D L

atch

QD


PT MUX Based Latch Implementation

QD

clk !Q

!clk

!clk

clk

input sampled(transparent mode)

feedback(hold mode)

Reduced area and clock load, but a threshold drop at output of pass transistors so reduced noise margins and performance


Latch Race Problem

CombinationalLogic

clk

Sta

teR

egis

ters

clk

B B’

Two-sided clock constraint

T tc-q + tplogic + tsu

Thigh tc-q + tcdlogic

B

Which value of B is stored?


Master Slave Based ET Flipflop

QMD 0

1 Q1

0

SlaveMaster

QMD

clk

0

1 Q

clk

1

0

SlaveMaster

clk

QM

Q

D

clock

D F

F

QD

clk = 0 transparent hold

clk = 01 hold transparent


MS ET Implementation

Q

D

clk

QM

I1

I2 I3

I4

I5 I6T2

T1T3

T4

Master Slave

!clk

clk

master transparentslave hold

master holdslave transparent


MS ET Timing Properties

Assume propagation delays are tpd_inv and tpd_tx, that the contamination delay is 0, and that the inverter delay to derive !clk is 0

Set-up time - time before rising edge of clk that D must be valid

Propagation delay - time for QM to reach Q

Hold time - time D must be stable after rising edge of clk

tsu = 3 * tpd_inv + tpd_tx

tc-q = tpd_inv + tpd_tx

thold = zero


Set-up Time Simulation

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.2 0.4 0.6 0.8 1

Vo

lts

Time (ns)

D clk

Q

QM

I2 out

tsu = 0.21 ns

works correctly

tsetup


Set-up Time Simulation

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.2 0.4 0.6 0.8 1

Vo

lts

Time (ns)

D clk

Q

QM

I2 out tsu = 0.20 ns

fails

tsetup


Propagation Delay Simulation

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Vo

lts

Time (ns)

tc-q(LH) = 160 psec

tc-q(HL) = 180 psectc-q(LH) tc-q(HL)


Power PC Flipflop

D Q

!clk

clk

clk

!clk

01

10 1

!clk

clk



01 01


Reduced Load MS ET FF

!clkclk

QD

!clk clk

I1

I2 I4

I3

QM T2T1

reverse conduction

Clock load per register is important since it directly impacts the power dissipation of the clock network.

Can reduce the clock load (at the cost of robustness) by making the circuit ratioed

to switch the state of the master, T1 must be sized to overpower I2

to avoid reverse conduction, I4 must be weaker than I1


Non-Ideal Clocks

1-1 overlap

0-0 overlap

!clk

clk

Ideal clocks

!clk

clk

Non-ideal clocksclock skew


Example of Clock Skew Problems

D

clkX

!clk

!Q

!clk Q

clk

B

AP1

P2

P3

P4

I1 I2I3 I4

Race condition – direct path from D to Q during the short time when both clk and !clk are high (1-1 overlap)

Undefined state – both B and D are driving A when clk and !clk are both high

Dynamic storage – when clk and !clk are both low (0-0 overlap)


Pseudostatic Two-Phase ET FF

D

clk1X

clk2

!Q

clk2 Q

clk1

B

AP1

P2

P3

P4

I1 I2I3 I4

clk2

clk1



dynamicstorage

tnon_overlap


Two Phase Clock Generator

clk

clk1

clk2

A

clk

A

B

B

clk1

clk2


Ratioed CMOS Clocked SR Latch

1

10

0

onoff

off onoff on

0

1

on

off

off

on

on

on

off

offM1

S R

clkclk

!QQ

M2

M3

M4

M5

M6

M7

M8 0 10 1


Sizing Issues

0

0.5

1

1.5

2

2 2.5 3 3.5 4

W/L5and6

!Q (

Vol

ts)

W/L2and4 = 1.5m/0.25 m

W/L1and3 = 0.5m/0.25 m

so W/L5and6 > 3


Transient Response

0

1

2

3

0.9 1 1.1 1.2 1.3 1.4 1.5

Q &

!Q (

Vo

lts)

SET

!QQ

Time (ns)

tc-!Q tc-Q


6 Transistor CMOS SR Latch

clkclk

SR

M1

SR

clk

!QQ

M2

M3

M4

M5M6

clk


Next Lecture and Reminders Next lecture

Dynamic sequential circuits - Reading assignment – Rabaey, et al, 7.3, 7.7

Reminders Project prototypes due on-line by 5:00pm on Oct 30th

HW#4 due November 11th (not Nov 4th as on outline) HW#5 will be optional (due November 20th) Final exam scheduled

- Tuesday, December 16th from 10:10 to noon in TBD

Project final reports due December 5th

cse477 l17 static sequential logic.1irwin&vijay, psu, 2003 cse477 vlsi digital circuits fall...

Documents

t clock period slide

logic style

t cq slide

infrequent clock

nikolic slide

negative latches clock

store state

preserve state