cse477 lecture8
TRANSCRIPT
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CSE477 L08 Capacitance.1 Irwin&Vijay, PSU, 2002
CSE477VLSI Digital Circuits
Fall 2002
Lecture 08: MOS & WireCapacitances
Mary Jane Irwin ( www.cse.psu.edu/~mji )www.cse.psu.edu/~cg477
[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]
http://www.cse.psu.edu/~mjihttp://www.cse.psu.edu/~cg477http://www.cse.psu.edu/~cg477http://www.cse.psu.edu/~mji -
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CSE477 L08 Capacitance.2 Irwin&Vijay, PSU, 2002
Review: Delay Definitions
t
Vout
Vin
input
waveform
output
waveform
tp = (tpHL + tpLH)/2
Propagation delay
t
50%
tpHL
50%
tpLH
tf
90%
10%
tr
signal slopes
Vin Vout
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CSE477 L08 Capacitance.3 Irwin&Vijay, PSU, 2002
CMOS Inverter: Dynamic
VDD
Rn
Vout = 0
Vin = VDD
CL tpHL = f(Rn, CL)
Todays focus
Next lectures focus
Transient, ordynamic, response determines themaximum speed at which a device can be operated.
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CSE477 L08 Capacitance.4 Irwin&Vijay, PSU, 2002
Sources of Capacitance
Cw
CDB2
CDB1
CGD12
CG4
CG3
wiring (interconnect) capacitance
intrinsic MOS transistor capacitances
Vout2Vin
extrinsic MOS transistor (fanout) capacitances
Vout
VoutVin
M2
M1
M4
M3
Vout2
CL
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CSE477 L08 Capacitance.5 Irwin&Vijay, PSU, 2002
MOS Intrinsic Capacitances
Structure capacitances
Channel capacitances
Depletion regions of the reverse-biasedpn-junctions of the drain andsource
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CSE477 L08 Capacitance.6 Irwin&Vijay, PSU, 2002
MOS Structure Capacitances
xdSource
n+
Drain
n+W
Ldrawn
xd
Poly Gate
n+n+
tox
Leff
Top view
lateral diffusion
CGSO = CGDO = Cox xd W = Co W
Overlap capacitance (linear)
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MOS Channel Capacitances
SD
p substrate
B
GVGS +
-
n+n+
depletion
regionn channel
CGS = CGCS + CGSO CGD = CGCD + CGDO
CGB = CGCB
The gate-to-channel capacitance depends uponthe operating region and the terminal voltages
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8/34CSE477 L08 Capacitance.8 Irwin&Vijay, PSU, 2002
Review: Summary of MOS Operating Regions
Cutoff (really subthreshold) VGS VTq Exponential in V
GSwith linearV
DSdependence
ID = IS e(qV
GS/nkT) (1 - e -(qV DS /kT) ) (1 - VDS ) where n 1
Strong Inversion VGS >VT
q Linear (Resistive) VDS
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Average Distribution of Channel Capacitance
Operation
Region
CGCB CGCS CGCD CGC CG
Cutoff Cox WL 0 0 Cox WL Cox WL + 2CoW
Resistive 0 Cox WL/2 Cox WL/2 Cox WL Cox WL + 2CoW
Saturation 0 (2/3)Cox WL 0 (2/3)Cox WL (2/3)Cox WL +2CoW
q
Channel capacitance components are nonlinear andvary with operating voltage
q Most important regions are cutoff and saturation
since that is where the device spends most of its time
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10/34CSE477 L08 Capacitance.10 Irwin&Vijay, PSU, 2002
MOS Diffusion Capacitances
S D
p substrate
B
GVGS +
-
n+n+
depletionregionn channel
CSB = CSdiff CDB = CDdiff
The junction (or diffusion) capacitance is from thereverse-biased source-body and drain-body pn-junctions.
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Source Junction View
side walls
channel
W
xj
channel-stop
implant (NA+)
source
bottom plate
(ND)
LS
substrate (NA)
Cdiff = Cbp + Csw = CjAREA + Cjsw PERIMETER
= Cj LS W + Cjsw (2LS + W)
junctiondepth
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Review: Reverse Bias Diode
All diodes in MOS digital circuits are reverse biased;the dynamic response of the diode is
determined by depletion-region charge orjunction capacitance
Cj = Cj0/((1 VD)/ 0)m
where Cj0 is the capacitance under zero-bias conditions (afunction of physical parameters), 0 is the built-in potential
(a function of physical parameters and temperature)
and m is the grading coefficient
q m = for an abruptjunction (transition from n to p-material isinstantaneous)
q m = 1/3 for a linear(or graded) junction (transition is gradual)
Nonlinear dependence (that decreases with increasingreverse bias)
+
-
VD
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Junction Capacitance
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CSE477 L08 Capacitance.14 Irwin&Vijay, PSU, 2002
Reverse-Bias Diode Junction Capacitance
0
0 . 5
1
1 . 5
2
- 5 - 4 - 3 - 2 - 1 0 1
VD (V)
Cj(
fF)
linear (m=1/3)
abrupt (m=1/2)
Cj0
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CSE477 L08 Capacitance.15 Irwin&Vijay, PSU, 2002
MOS Capacitance Model
CGS
CSB CDB
CGD
CGB
S
G
B
D
CGS = CGCS + CGSO CGD = CGCD + CGDO
CGB = CGCB
CSB = CSdiff CDB = CDdiff
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CSE477 L08 Capacitance.16 Irwin&Vijay, PSU, 2002
Transistor Capacitance Values for 0.25
Cox
(fF/ m2)
Co
(fF/ m)
Cj
(fF/ m2)
mj b
(V)
Cjsw
(fF/ m)
mjsw bsw
(V)
NMOS 6 0.31 2 0.5 0.9 0.28 0.44 0.9
PMOS 6 0.27 1.9 0.48 0.9 0.22 0.32 0.9
Example: For an NMOS with L = 0.24 m, W = 0.36 m,LD = LS = 0.625 m
CGC = Cox WL =
CGSO = CGDO = Cox xd W = Co W =
so Cgate_cap = CoxWL + 2CoW =
Cbp = Cj LS W =
Csw = Cjsw (2LS + W) =
so Cdiffusion_cap =
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CSE477 L08 Capacitance.17 Irwin&Vijay, PSU, 2002
Transistor Capacitance Values for 0.25
Cox
(fF/ m2)
Co
(fF/ m)
Cj
(fF/ m2)
mj b
(V)
Cjsw
(fF/ m)
mjsw bsw
(V)
NMOS 6 0.31 2 0.5 0.9 0.28 0.44 0.9
PMOS 6 0.27 1.9 0.48 0.9 0.22 0.32 0.9
Example: For an NMOS with L = 0.24 m, W = 0.36 m,LD = LS = 0.625 m
CGC = Cox WL = 0.52 fF
CGSO = CGDO = Cox xd W = Co W = 0.11 fF
so Cgate_cap = CoxWL + 2CoW = 0.74 fF
Cbp = Cj LS W = 0.45 fF
Csw = Cjsw (2LS + W) = 0.45 fF
so Cdiffusion_cap = 0.90 fF
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CSE477 L08 Capacitance.18 Irwin&Vijay, PSU, 2002
Review: Sources of Capacitance
Vout
Cw
VinCDB2
CDB1
CGD12
M2
M1
M4
M3
Vout2
CG4
CG3
wiring (interconnect) capacitance
intrinsic MOS transistor capacitances
Vout2Vin
extrinsic MOS transistor (fanout) capacitances
Vout
CL
ndrain
pdrain
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CSE477 L08 Capacitance.19 Irwin&Vijay, PSU, 2002
Gate-Drain Capacitance: The Miller Effect
A capacitor experiencing identical but opposite voltageswings at both its terminals can be replaced by acapacitor to ground whose value is two times the originalvalue
Vin
CGD1
M1
Vout V
V
VinM1
Vout
V
V
2CGB1
M1 and M2 are either in cut-off or in saturation.
The floating gate-drain capacitor is replaced by acapacitance-to-ground (gate-bulk capacitor).
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CSE477 L08 Capacitance.20 Irwin&Vijay, PSU, 2002
Drain-Bulk Capacitance: Keq s (for 2.5 m)
high-to-low low-to-high
Keqbp Keqsw Keqbp Keqsw
NMOS 0.57 0.61 0.79 0.81PMOS 0.79 0.86 0.59 0.7
We can simplify the diffusion capacitance calculations
even further by using a Keq to relate the linearizedcapacitor to the value of the junction capacitance underzero-bias
Ceq = Keq Cj0
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CSE477 L08 Capacitance.21 Irwin&Vijay, PSU, 2002
Extrinsic (Fan-Out) Capacitance
The extrinsic, or fan-out, capacitance is the total gate capacitanceof the loading gates M3 and M4.
Cfan-out = Cgate (NMOS) + Cgate (PMOS)
= (CGSOn + CGDOn + WnLnCox ) + (CGSOp + CGDOp + WpLpCox )
Simplification of the actual situation
q Assumes all the components of Cgate are between Vout and GND (orVDD )
q
Assumes the channel capacitances of the loading gates are constant
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CSE477 L08 Capacitance.22 Irwin&Vijay, PSU, 2002
Layout of Two Chained Inverters
InOut
Metal1
VDD
GND
1.2 m=2
1.125/0.25
0.375/0.25
PMOS
NMOS
Polysilicon
W/L AD ( m2) PD ( m) AS ( m2) PS ( m)NMOS 0.375/0.25 0.3 1.875 0.3 1.875
PMOS 1.125/0.25 0.7 2.375 0.7 2.375
0.125 0.5
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CSE477 L08 Capacitance.23 Irwin&Vijay, PSU, 2002
Components of CL (0.25 m)C Term Expression Value (fF)
HLValue (fF)
LHCGD1 2 Con Wn 0.23 0.23
CGD2 2 Cop Wp 0.61 0.61
CDB1 Keqbpn ADnCj + Keqswn PDnCjsw 0.66 0.90
CDB2 Keqbpp ADpCj + Keqswp PDpCjsw 1.5 1.15
CG3 (2 Con )Wn + Cox WnLn 0.76 0.76
CG4 (2 Cop )Wp + Cox WpLp 2.28 2.28
Cw from extraction 0.12 0.12CL 6.1 6.0
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CSE477 L08 Capacitance.24 Irwin&Vijay, PSU, 2002
Wiring Capacitance
The wiring capacitance depends upon the length andwidth of the connecting wires and is a function of thefan-out from the driving gate and the number of fan-outgates.
Wiring capacitance is growing in importance with thescaling of technology.
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CSE477 L08 Capacitance.25 Irwin&Vijay, PSU, 2002
Parallel Plate Wiring Capacitance
electrical field lines
W
H
tdi dielectric (SiO2)
substrate
Cpp = ( di /tdi )
WL
current flow
permittivity
constant
(SiO2= 3.9)
L
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CSE477 L08 Capacitance.26 Irwin&Vijay, PSU, 2002
Permittivity Values of Some Dielectrics
Material di
Free space 1Teflon AF 2.1
Aromatic thermosets (SiLK) 2.6 2.8
Polyimides (organic) 3.1 3.4
Fluorosilicate glass (FSG) 3.2 4.0
Silicon dioxide 3.9 4.5
Glass epoxy (PCBs) 5
Silicon nitride 7.5
Alumina (package) 9.5
Silicon 11.7
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CSE477 L08 Capacitance.27 Irwin&Vijay, PSU, 2002
Sources of Interwire Capacitance
interwire
fringe
pp
Cwire = Cpp + Cfringe + Cinterwire
= ( di /tdi )WL
+ (2 di )/log(tdi /H)
+ ( di /tdi )HL
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CSE477 L08 Capacitance.28 Irwin&Vijay, PSU, 2002
Impact of Fringe Capacitance
(from [Bakoglu89])
H/tdi = 1
H/tdi = 0.5
Cpp
W/tdi
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CSE477 L08 Capacitance.29 Irwin&Vijay, PSU, 2002
Impact of Interwire Capacitance
(from [Bakoglu89])
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CSE477 L08 Capacitance.30 Irwin&Vijay, PSU, 2002
Insights
For W/H < 1.5, the fringe component dominates theparallel-plate component. Fringing capacitance can
increase the overall capacitance by a factor of 10 or more.
When W < 1.75H interwire capacitance starts to dominate
Interwire capacitance is more pronounced for wires in the
higher interconnect layers (further from the substrate) Rules of thumb
q Never run wires in diffusion
q Use poly only for short runs
q Shorter wires lower R and C
q Thinner wires lower C but higher R
Wire delay nearly proportional to L2
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CSE477 L08 Capacitance.31 Irwin&Vijay, PSU, 2002
Wiring Capacitances
Field Active Poly Al1 Al2 Al3 Al4
Poly 88
54
Al1 30 41 57
40 47 54
Al2 13 15 17 36
25 27 29 45
Al3 8.9 9.4 10 15 41
18 19 20 27 49
Al4 6.5 6.8 7 8.9 15 35
14 15 15 18 27 45
Al5 5.2 5.4 5.4 6.6 9.1 14 3812 12 12 14 19 27 52
fringe in aF/ m
pp in aF/ m2
Poly Al1 Al2 Al3 Al4 Al5
Interwire Cap 40 95 85 85 85 115
per unit wire length in aF/ m for minimally-spaced wires
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CSE477 L08 Capacitance.32 Irwin&Vijay, PSU, 2002
Dealing with Capacitance
Low capacitance (low-k) dielectrics (insulators) such as
polymide or even air instead of SiO2q family of materials that are low-k dielectrics
q must also be suitable thermally and mechanically and
q compatible with (copper) interconnect
Copper interconnect allows wires to be thinner withoutincreasing their resistance, thereby decreasing interwirecapacitance
SOI (silicon on insulator) to reduce junction capacitance
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CSE477 L08 Capacitance.33 Irwin&Vijay, PSU, 2002
Next Time: Dealing with Resistance
MOS structure resistance - Ron
Wiring resistance
Contact resistance
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Next Lecture and Reminders Next lecture
q MOS resistance
- Reading assignment Rabaey, et al, 4.3.2, 4.4.1-4.4.4
Reminders
q Lecture lectures 9+10 will be combined on the 26th
q HW2 due today
q Project specifications dues October 3rd
q HW3 due Oct 10th
q Evening midterm exam scheduled
- Wednesday, October 16th from 8:15 to 10:15pm in 260 Willard
- Only one midterm conflict filed for so far