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Application Note | CST AG

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2012

from layout to eye diagram CST STUDIO SUITE 2012 and the EDA Workf lowEnsuring good Signal Integrity (SI) in high-speed communication PCBs is becoming more challenging as layouts become more complex, the number of layers increases and the boards get smaller.A full-wave three dimensional (3D) electromagnetic simulator can be used to simulate and visualize the propagation of electromagnetic fields across PCBs. This article will describe how CST MICROWAVE STUDIO® can be successfully used to characterize the response of high-speed channels, and how typical SI results such as S-parameters, Time Domain Reflectometry (TDR) data and eye diagrams can be numerically calculated to predict the response of a channel. The article will also discuss how to modify layouts in order to improve channel performance, and provide some design guidelines.

This paper presents an overview of the simulation of a high-speed differential channel using CST STUDIO SUITE®. The first section will introduce the CST STUDIO SUITE PCB import, a very power-ful tool which allows the user to set up the model quickly, auto-matically configuring ports, layout simplification, components, meshing and boundary conditions. The next section will introduce simulation setup, with the main focus on solver overview and 3D mesh setup and a particular emphasis on the hexahedral mesh. This section will also present results from the simulation, includ-ing scattering or S-parameter, Time Domain Reflectometry (TDR) data and an eye diagram. The last section will discuss the visualiza-tion of the field distribution, which is one of the main strengths of

using 3D simulation, and the use of simulation results to provide guidelines on how to improve the performance of the design.

EDA links

The called CST STUDIO SUITE PCB import (also called the EDA link) allows the user to import PCB layout databases into CST STUDIO SUITE. It supports a number of formats, as sum-marized by the following table.

The EDA link is composed of three parts: the layer stack-up defi-nition, the parts editor, and the PCB preview section.

EDA Vendor Tool Versions Supported

Import type (pcb, package) Files required Important Information, requirements

Valor ODB++ 6.4, 7.0 PCB ODB++ ODB++ is common format and can be generated from almost any PCB tool

Cadence PCB Editor, PCB Router 16.01, 16.2, 16.3, 16.5 PCB .brd Must first install CST Link on Cadence Tool, then export portion of design file

Cadence Package Designer 16.01, 16.2, 16.3, 16.5 Package .mcm Must first install CST Link on Cadence Tool, then export portion of design file

Cadence SiP Layout 16.01, 16.2, 16.3, 16.5 SIP (System in Package) .sip Must first install CST Link on Cadence Tool, then export portion of design file

Altium Designer v2009, v10 PCB ODB++

Altium P-CAD PCB ODB++ Old software, replaced by Designer

Altium Protel SE PCB ODB++ Old software, replaced by Designer

Mentor Graphics BoardSta-tion PCB ASCII Old software, replaced by Expedition

Mentor Graphics Expedition PCB ASCII or ODB++ If ASCII import is used, Expedition ASCII files are exported in encrypted format, which cannot be read by external tools. Need to obtain decrypting program from Mentor Graphics

Mentor Graphics Hyperlynx PCB .hyk

Mentor Graphics PADS v2005.0, v2005.2, v2007.0 v9.0, v9.2 PCB ASCII Ensure that 'flood' and 'hatch' operations are run in PADS, to fill copper pour areas.

Zuken CR-500 12.01 and below PCB PCB ASCII (.pcf), Footprint ASCII (.ftf)

Generated using batch commands 'pcout, 'ftout'. ASCII files must have same base filename as PCB filename

Zuken Visula PCB PCB ASCII (.pcf), Footprint ASCII (.ftf)

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The first part of the EDA link allows the user to specify the stack-up of layers of the PCB. In order to properly convert the PCB layout for-mat, the thickness of each metallic layer and the substrate layers needs to be defined. The “filling from” lets the user decide for each metal layer whether it lies above, below or in the middle of the dielectric. “Effective thickness” should only be selected if the thick-ness of the dielectric layers is defined between the faces of the conductive layers, rather than the faces of the dielectrics. Figure 2 shows the differences between the “effective” and “nominal” thick-ness and demonstrates the effect of the filling form parameter.

Figure 1: PCB import dialog showing the 4 different tabs, with the stack-up tab selected

Figure 2: PCB Import: Stack-up filling form and the different interpretations of the

dielectric thickness

To ensure the layers have the right material properties, the conduc-tivity of the metal layers (defined in S/m), the permittivity ( ) and the dielectrics losses (tan (δ)) should be specified. This information is often already included in the PCB layout database; as a result, it is not usually necessary to manually input anymore data.

It is also possible to import components on the PCB into CST STUDIO SUITE. Only R, L, and C components are supported di-rectly by the import tools. Other active devices, which are marked “not supported” here, can be examined by using the circuit simu-lator, CST DESIGN STUDIO™ (CST DS), or by enabling the EM-co-simulation feature, which is also available within the transient task of CST DS.

Inside the component library editor, the component names are listed within the “Refdes” (reference designator) column. The “load” button inside the component library editor provides the ability to import the component values from CSV files, Cadence report files or a CR-5000 part list. The CST STUDIO SUITE PCB im-port interface also allows you to set up the R, L and C values of any component, using the part library editor.

Figure 3: PCB import – Component and part library editor dialogs

The PCB preview dialogue offers a quick view of the original lay-out. The display in the main window can be controlled by the layer visibility matrix and the list of the net names. Selecting the names of nets in the “Net highlighting” section automatically highlights the nets in the main window.

Figure 4: PCB import – PCB preview dialog showing the PCB preview tab

The imported nets can be also simplified. If the simulation needs only a small part of the layout area or a few nets, the option “Restrict to selected” can be used. Several operations can be ap-plied to produce the right simplification:

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1. Restriction to the selected area: A part of the layout will be im-ported, including all the nets inside this area. The area can be either rectangular or polygonal.

2. Restriction to the selected nets: The whole area of layout will be imported, but with only the selected nets.

3. Restriction to the selected nets and area: A part of the layout will be imported, but with only the selected nets inside this area. The area can be either rectangular or polygonal.

4. Restrict to the selected layers: Imports only some of the layers.

The results of different combinations of the “Restrict to selected” options are summarized in Figure 5.

Figure 5: PCB import

(a) Restriction to the selected area

(b) Restriction the selected net

(c) Restriction to the selected area and nets (1 signal net and 1 ground net)

The EDA link offers also the ability to define excitations, ports and terminals. An arbitrary port can be defined by moving the mouse pointer to the chose location in the PCB preview. This offers two port orientations: a vertical port that is oriented in z-direction be-tween two different metal layers, and a horizontal port which can be defined in arbitrary position along the xy plane.

The “Ports” button also allows a pin-based automatic port defini-tion. There are two different types of ports supported: the single-ended port and the differential port. For the single-ended port definition, the pin of the component and the corresponding refer-ence net, (GND net, for example) needs to be specified. For the dif-ferential port definition however, a pin pair selection from the two different nets, for example “DP_CLKP” and “DP_CLKN”, is required.

Figure 6: PCB import – automatic port generation for vertical and horizontal port

orientations

Figure 7: PCB import – a pin based port definition dialog including both the single-

ended and the differential port type definition

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If the full layout is used for the simulation, we can skip the import restriction function and import the layout directly. Once all the layout import settings are defined, the layout will be converted in-to a 3D-model inside CST STUDIO SUITE, as it is shown in Figure 8.

3D-Simulation Setup

As in any other 3D simulation tool, a proper simulation setup is necessary to achieve a reasonable simulation time and accurate results. In this section, we will briefly discuss the two main simula-tion settings that are relevant to performing the Signal Integrity simulation in CST STUDIO SUITE.

There are several solvers available within the CST STUDIO SUITE and as each of the solvers is specialized for a certain application, the choice of solver is important, especially for SI calculation. In general, the frequency domain and time domain solvers can both be applied to this class of problem. The frequency domain solver is based on the Finite Element Method (FEM), whereas the time domain solver is based on the Finite Integration Technique[1] which uses a hexahedral based grid to mesh the structure. Unique solver methods such as the Perfect Boundary Approximation (PBA)® for curvature and Thin Sheet Technique (TST)™[2] for the thin-sheet structure reduce computational effort needed by the simulation, so the time domain solver is typically the most suitable solver for SI simulation. However, the frequency domain solver can be better suited to problems where the structure is much smaller than the wavelength and contains multiple ports, which is very common in packaging applications.

Figure 8: A full 3D Model of a PCB layout imported into CST MICROWAVE STUDIO

The Meshing

When using the time domain solver, only the hexahedral mesh will be available. With the unique features mentioned above, the

PBA and the TST, the hexahedral mesh offers a good compromise between simulation time, memory requirement and results ac-curacy. The hexahedral mesh view is depicted in Figure 9.

Figure 9: A hexahedral mesh preview in CST MICROWAVE STUDIO

Be aware that, in order to generate the mesh, the frequency set-ting has to have already been specified; this is done with Solve4 Frequency. With the hexahedral mesh grid, the density of the mesh is determined by the cell size in the x, y, and z directions. The smaller the mesh cell size is, the greater the number of the cells, which will certainly lead to a higher mesh density. Using the CST PCB import interface, the mesh density can be automatically adjusted based on the complexity of the structure, and the ad-justment can be configured within the “special” settings as it is shown in Figure 10.

Figure 10: PCB Import: Special Mesh Settings

The parameter “Lateral reference length” is used as the reference value for defining the mesh density in the x and y directions. The value of the “lateral reference length” is determined automatically based on the smallest distance between two neighboring nets. There are three different parameter settings to specify the mesh density along the x and y directions: “very fine”, “fine” and “coarse”. The “very fine” setting uses the factor 0.4 relative to the lateral reference length, whereas the “fine” setting uses the factor 0.7 and the “coarse” setting uses the factor 3. The parameter “Fixpoints within the substrate layers” controls the number of meshlines within each substrate layer.

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In CST MICROWAVE STUDIO, the mesh density value can be found within the local mesh properties of the substrate object, which is accessible within the navigation tree under the mesh groups. By default, the PCB is divided into two mesh groups by the EDA link: meshgroup1, which unites all the PCB nets, and meshgroup2, which unites the substrates.

By changing the mesh setting for one particular mesh group, the mesh setting for every object in this group will be automatically changed. Figure 11 shows the mesh groups navigation tree and the related mesh properties.

Figure 11: Mesh groups and its local mesh properties with the mesh step width value

in x and y directions

Simulation Results

This section covers the simulation results which are rel-evant for the signal integrity simulation calculated in CST MICROWAVE STUDIO® (CST MWS) using the time domain solver. A PCB layout with nine metal layers is used as an example.

In order to characterize the channel performance, the differential nets DPO_RXN1 and DPO_RXP1 are selected. To reduce the computa-tional effort, the import simplification “Restriction to the selected nets and area” has been applied, with the selected area extending seven millimeters around the selected nets. Each end of the line is terminated with a 50 ohm single-ended discrete port using the au-tomatic port definition option within the PCB Import interface. A 1.4 mm mesh step width in the x and y directions has been chosen in order to achieve a good trade-off between the simulation time, the memory consumption and the accuracy of the results.

S-Parameter

The scattering parameter, or S-parameter, is mostly used in signal integrity analysis for characterizing the channel performance. The S-parameters can be written in the form of a matrix, known as the scattering matrix. The size of the scattering matrix de-pends on the number of the ports defined in the structure. In this example, four single-ended ports are defined, which will lead to a 4x4 scattering matrix. To characterize the high-speed channel response, the spectrum of the scattering matrix has been de-fined between 0-20 GHz (the results are calculated up to 20 GHz),

which corresponds to a 40 Gb/s data rate.

The corresponding port configuration for the two single-ended lines defined for the simulation is illustrated in Figure 12.

Figure 12: Port configuration for two single-ended lines

Figure 13a, 13b: 4x4 S-Parameter results.

The corresponding insertion and return loss of the channel can be found in Figure 13a, and the near end cross talk (NEXT) and the far end cross talk (FEXT) are depicted in Figure 13b.

At higher frequencies the channel response consists of a lot of reso-nances, which are mostly caused by the broken return current path. Similarly, the insertion loss also shows poor performance at fairly low frequency, at 4.5 GHz. As well as showing the return and in-sertion loss, the S-parameters also show a higher level of crosstalk between the nets. Figure 13b shows that the maximum of X-talk is about 5 dB, which is generally unacceptable for high-speed circuit.

The above results relate to the single-ended configuration, where each net is excited individually. However, in practical applications differential signaling is often required, since it shows better noise immunity. In order to calculate the differential results from the single-ended results, we will use the circuit simulator, CST DS. The schematic and workflow for applying circuit simulation within the CST DS are shown in Figure 14.

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Figure 14: CST DESIGN STUDIO schematic for single-ended to mixed mode convertion

Since the circuit co-simulation requires an S-matrix from the CST MICROWAVE STUDIO block, the full port simulation in CST MWS has to be carried out first. To convert the single-ended results into the mixed mode results we can use, for instance, the ideal mode converter. The pins “D” and “C” are related to the dif-ferential and common mode respectively, whereas the pins “P” and “N” are both related to the single-ended mode, so these pins are connected with the CST MWS block. Once the circuit simula-tion is complete, the mixed mode results (consisting of the dif-ferential and the common mode results) are accessible through the navigation tree, as shown in Figure 15.

Figure 15: Mixed Mode S-Parameter results from CST DESIGN STUDIO schematic

using ideal mode converter

Based on the above schematic configuration, ports one and three are related to the differential mode while ports two and four are related to the common mode. Therefore, the S1,1 and S2,2 param-eter correspond to the return loss of the differential and common modes respectively, whereas the S1,3 and S2,4 parameters describe the insertion loss of the two modes. In this example, a 100 ohm impedance is set for the differential mode and a 25 ohm imped-ance is set for the common mode.

Time Domain Reflectometry (TDR)

Alongside the scattering parameter, time domain reflectometry or TDR is also commonly used to review the impedance value along the transmission line, such as a microstrip line, coplanar wave-guide or stripline. The TDR result lets us easily locate any disconti-nuities in the impedance.

Figure 16: Time Domain Reflectometry (TDR) results for a single-ended line

In CST STUDIO SUITE, the TDR calculation is part of the post-processing, which means it doesn’t require a recalculation of the full-wave simulator. Choosing the time domain solver means that the time signal responses will be used for the TDR calculation. Alternatively, since the scattering parameters describe the trans-fer function of the system, the TDR can be also obtained from the scattering matrix. A typical TDR result based on the time signal response for a single-ended line is illustrated in Figure 16.

The TDR results from Figure 16 show that the impedance at the beginning and end points is 50 ohm. This indicates that a 50 ohm impedance was used to terminate single-ended line. The TDR curves includes a number of jumps caused by the signal passing through several discontinuities, including a via transition and points where the line’s cross-section changed. From this infor-mation, the location of the discontinuities can be found out by using the velocity of the signal propagating inside the substrate medium to convert the time information into spatial information.

As mentioned previously, the TDR can be also calculated from the scattering parameter information. This means the differential and common mode TDR can be directly obtained from the result from the CST DESIGN STUDIO circuit simulator, as shown in Figure 17.

Figure 17: Time Domain Reflectometry (TDR) results for the differential and common

mode signal

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Eye Diagrams

In high-speed digital communication, eye diagrams, or eye pat-terns, are used to measure the performance of channels. A series of random digital signals are sent from the transmitter through the channel, and the receiver observes a distortion of the signal as a result of poor channel performance.

Figure 18 shows the PRBS (pseudo-random bit signal) excitation used to generate the eye pattern, together with the response sig-nal. The digital pulses used in this example have a rise and fall time of 50 ps and a pulse length of 200 ps, which corresponds to a 5 Gb/s data rate. By wrapping the response signal around the after every two unit intervals or every two bits, the response signals become overlaid, producing the eye diagram shown in Figure 19. In addition this, the software can also automatically provide the information generated from the eye diagram, such as eye height and eye width. This information helps to interpret the eye diagram.

Figure 18: The excitation and response of the digital signal sequences

Figure 19: The eye diagram results and the corresponding parameters

As the eye height becomes smaller, the probability of having a false triggering between “0” and “1” is higher. Hence, the bit error rate (BER) becomes higher as the noise rises. The eye width provides information about the jitter, important for timing measurement.

Field Distribution

The previous sections have explained the scattering parameter, TDR and eye diagram and shown how these are often used to esti-mate the channel performance. There is a trend in PCB layout de-sign towards greater complexity and higher clock frequencies to meet the demands of high-speed communication. On high-speed boards, interference is a major issue, as interference can degrade the channel performance of the channel.

Channel performance also suffers when there is a discontinuity in the reference plane. The discontinuity will result in an incorrect return current path and this will degrade the received signal qual-ity. Moreover, the presence of cross talk will cause the response signal to deteriorate as well.

To avoid these issues, the PCB layout design needs to be changed in order to improve the channel response.

The ability to visualize the field distribution is one of the major advantages of a full 3D simulation, since it helps to quickly iden-tify problematic areas. Correcting or improving the layout is much easier with the aid of the field distribution than it is with just S-parameters or an eye diagram.

Figure 20 presents an example of field visualization, showing the surface current distribution for three different frequencies.

Figure 20: The surface current distribution, and the corresponding scattering param-

eter results

Since the current always finds the path with the lowest impedance, there is a good return current path at low frequencies. The short-est path for the return current runs underneath the trace. As the frequency increases, the inductance and impedance of the GND plane will rise. As a result, the entire GND plane becomes a possible return current path. In this case, the surface current is spread out across the entire reference plane, which in severe cases will lead to serious EMC issues.

Another use of field visualization is locating the poor insertion loss at certain frequency. The field visualization highlights the via reso-nances as the main cause of this. If the via is resonating, most of the energy will be radiated by the antenna effect instead of being transferred to the receiver. This will result in EMC issues and a poor signal quality.

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Figure 21 illustrates the two differences between the original via (top left) and a via modified by back-drilling (bottom left) and the field distributions of the two different via models can be seen in the Figure 22. Back-drilling the via helps to reduce its inductance, which can be critical at high frequencies.

Alternatively, using a micro via can be also a good choice since back drilling the via might be more expensive and difficult from a manu-facturing point of view.

Figure 21: S-Parameter results for two different via models

Figure 22: Comparison of field radiation for two different via modeling

Conclusions

This paper has presented a complete workflow for a signal integ-rity simulation of a high-speed differential channel from using CST STUDIO SUITE to import various layout formats and trans-late the PCB layout into a 3D mode to the full 3D simulation of a complex realistic multilayer PCB using the time domain solver of CST MICROWAVE STUDIO to calculate its properties efficiently.

Multiple useful quantities and figures have been presented: scat-tering parameters, TDR, and eye diagram, all of which are very important for channel performance analysis. Field monitors to visualize the surface current distribution for different frequency points have been demonstrated to show the advantages of 3D full wave simulation. Finally, few design ideas on how to improve the performance of the channel have been put forward.

[1] Marcus Clemens and Thomas Weiland, “Discrete electromagnetism with the Finite Integration

Technique”, Journ. of Electromagnetic Waves and Propagation/Progress in Electromagnetic

Research (PIER) Monograph Series, 2011.[2] B. Krietenstein, R. Schuhmann, P. Thoma, T. Weiland, „The Perfect Boundary Approximation

Technique Facing The Big Challenge Of High Precision Field Computation“, Proc. of the XIX

Internation Linear Accelerator Conference (LINAC 98), Chicago, USA 1998, pp.860-862.

AuthorRichard Sjiariel, CST AG – Support and Engineering

CST AGBad Nauheimer Str. 1964289 DarmstadtGermany

info@cst.comhttp://www.cst.com

CHANGING THE STANDARDS