custom processor design using vhdl

8/11/2019 CUSTOM PROCESSOR DESIGN USING VHDL

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Custom Processor design using VHDL

CHAPTER 1

INTRODUCTION

A microcontroller is a computer-on-a-chip, or, a single-chip computer. Micro suggests

that the device is small, and controller tells you that the device might be used to control

objects, processes, or events. Another term to describe a microcontroller is embedded

controller, because the microcontroller and its support circuits are often built into, or

embedded in, the devices they control. We can find microcontrollers in all kinds of things

these days. Any device that measures, stores, controls, calculates, or displays information is a

candidate for putting a microcontroller inside. The largest single use for microcontrollers is in

automobiles. Just about every car manufactured today includes at least one microcontroller

for engine control, and often more to control additional systems in the car. In desktop

computers, can find microcontrollers inside keyboards, modems, printers, and other

peripherals. In test equipment, microcontrollers make it easy to add features such as the

ability to store measurements, to create and store user routines, and to display messages and

waveforms. Consumer products that use microcontrollers include cameras, video recorders,

compact-disk players, and ovens are just a few examples.

A microcontroller is similar to the microprocessor inside a personal computer.

Examples of microprocessors include Intels 8086, Motorolas 68000, and Zilogs Z80. Both

microcontrollers and microprocessors contain a central processing unit, or CPU. The CPU

executes instructions that perform the basic logic, math, and data-moving functions of a

computer. To make a complete computer, a microprocessor requires memory for storing data

and programs, and input/output (I/O) interfaces for connecting external devices like

keyboards and displays. In contrast, a microcontroller is a single-chip computer because it

contains memory and I/O interfaces in addition to the CPU. Because the amount of memory

and interfaces that can fit on a single chip is limited, microcontrollers tend to be used in

smaller systems that require little more than the microcontroller and a few support

components. Examples of popular Microcontrollers are Intel 8051,PIC,Motorolas

68HC11and Zilogs Z8.

Increasing performance and gate capacity of recent FPGA devices permits complex

logic systems to be implemented on a single programmable device. Such a growingcomplexity demands design approaches, which can cope with designs containing hundreds of


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thousands of logic gates, memories, high-speed interfaces, and other high-performance

components.

One category of such design approaches are design methodologies based on languages

derived from traditional programming languages such as C, Pascal, Java or others. These

allow designers to use the familiar language syntax to develop hardware systems at high

level. In this report, the design of a RISC controller is presented. Hardware description

language is used for the proposed work and the work is targeted towards FPGA.


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CHAPTER 2

RISC ARCHITETURE

2.1 RISC Architecture

In the early 1980s, a number of computer designers were questioning the need for

complex instruction sets used in the computer of the time. In studies of popular computer

systems, almost 80% of the instructions are rarely being used. So they recommended that

computers should have fewer instructions and with simple constructs. This type of computer

is classified as reduced instruction set computer or RISC.

The first characteristic of RISC is the uniform series of single cycle, fetch-and-

execute operations for each instruction implemented on the computer system being

developed. A single-cycle fetch can be achieved by keeping all the instructions a standard

size. The standard instruction size should be equal to the number of data lines in the system

bus, connecting the memory where the program is stored to the CPU. At any fetch cycle, a

complete single instruction will be transferred to the CPU. For instance, if the basic word size

is 16 bits, and the data port of the data bus has 16 lines, the standard instruction length should

be 16-bits.

Achieving uniform execution of all instructions is much more difficult than achieving

a uniform fetch. Some instructions may involve simple logical operations on a CPU register

(such as clearing a register) and can be executed in a single CPU clock cycle without any

problem. Other instructions may involve memory access (load from or store to memory, fetch

data) or multi-cycle operations (multiply, divide, floating point), and may be impossible to be

executed in a single cycle. Ideally, we would like to see a streamlined and uniform handling

of all instructions, where the fetch and the execute stages take up the same time for any

instruction, desirably, a single cycle. This is basically one of the first and most important

principles inherent in the RISC design approach. All instructions go from the memory to the

CPU, where they get executed, in a constant stream. Each instruction is executed at the same

pace and no instruction is made to wait. The CPU is kept busy all the time.

Thus, some of the necessary conditions to achieve such a streamlined operation are:

Standard, fixed size of the instruction, equal to the computer word length and to the

width of the data bus.

Standard execution time of all instructions, desirably within a single CPU cycle.


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While it might not practical to hope that all instructions will execute in a single cycle, one

can hope that at least 75% should. Which instructions should be selected to be on the reduced

instruction list? The obvious answer is: the ones used most often. It has been established in a

number of earlier studies that a relatively small percentage of instructions (10 20%) take up

about 80% 90% of execution time in an extended selection of benchmark programs [3].

Among the most often executed instructions were data moves, arithmetic and logic

operations. As mentioned earlier, one of the reasons preventing an instruction from being

able to execute in a single cycle is the possible need to access memory to fetch operands

and/or store results. The conclusion is therefore obvious, we should minimize as much as

possible the number instructions that access memory during the execution stage. This

consideration brought forward the following RISC principles:

Memory access, during the execution stage, is done by load/store instructions only.

All operations, except load/store, are register-to-register, within the CPU.

Most of the CISC systems are micro programmed; because of the flexibility that

microprogramming offers the designer. Different instructions usually have micro routines of

different lengths. This means that each instruction will take a number of different cycles to

execute. This contradicts the principle of a uniform, streamlined handling of all instructions.

An exception to this rule can be made when each instruction has a one-to one correspondence

with a single micro instruction. That is, each micro routine consists of a single control word,

and still let the designer benefit from the advantages of micro programming. However,

contemporary CAD tools allow the designer of hardwired control units almost as easy as

micro programmed ones. This enables the single cycle rule to be enforced, while reducing

transistor count.

In order to facilitate the implementation of most instruction as register-to register

operations, a sufficient amount of CPU general purpose registers has to be provided. A

sufficiently large register set will permit temporary storage of intermediate results, needed as

operands in subsequent operations, in the CPU register file. This, in turn, will reduce the

number of memory accesses by reducing the number of load/store operations in the program,

speeding up its run time. A minimal number of 16 general purpose CPU registers has been

adopted, by most of the industrial RISC system designers.


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The characteristics of RISC architecture are summarized as follow:

Single-cycle instruction execution

Fixed-length, easily decoded instruction format

Relatively few instructions

Relatively few addressing modes

Memory access limited to load and store instructions

Hardwired rather than micro programmed control unit

Relatively large number of general purpose register file

2.2Benefits of RISC Architecture

1. RISC architecture makes the implementation of a processor on a single chip feasible. It is

more difficult to realize a complex architecture on a chip than a less complicated architecture.

So only a RISC processor can be implemented on an FPGA chip with a limited number of

logic cells.

2. RISC architecture helps in implementing more efficient pipelining. The length of the

pipeline is dependent on the length of the longest step. RISC instructions are all of the same

length and can be fetched in a single operation. Ideally, each of the stages in a RISC

processor pipeline takes 1 clock cycle so that the processor finishes an instruction during each

clock cycle and averages one cycle per instruction. All RISCs use pipelined execution where

pipelining involves finding a balance between the four parts of a RISC instruction execution:

instruction fetch, register read, arithmetic/ logic operation and register write.

3. The difficulty in system design is less for RISC processors. The design time and the time

required for testing and debugging is thus reduced leading to an edge in the industry. This

also assists in implementing the project within the time frame. Documentation and

maintenance is also easier for RISC architecture.

4. RISC architecture saves chip area by getting rid of the more complicated hardware

necessary in CISC processors. The space on a chip spared by implementing only hardware

for a reduced instruction set can be used to promote pipelining and a larger cache, thus

improving the performance of the system.


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5. A RISC processor is capable of executing commonly used algorithms at a high speed with

a simple architecture. Better use of chip area, use of newer technologies facilitated by

reduced design time, simpler control structures and the presence of fewer gates in the critical

path in the machine could give RISC processors an edge in algorithm execution speed

2.3Common RISC Traits

The operations and addressing modes are reduced. Operations between registers complete in

one cycle, permitting a simpler, hardwired control for RISC, instead of microcode. Only one

or a very few simple addressing modes are provided. More complicated addressing modes

can be synthesized from the simple ones.

2. Operations are register-to-register, with only load and store operations accessing memory.

Operands are not discarded after being fetched, as in the memory-to- memory architecture.

This allows compilers to reuse operands stored in registers. As a result cycle time is

shortened.

3. Instruction formats are simple and are usually of uniform length. This restriction allows

RISCs to remove instruction decoding time from the critical execution path. So register

access can take place simultaneously with op-code decoding. This removes the instruction

decoding stage from the pipelined execution, making it more effective by shortening the

pipeline. Single-sized instructions also simplify virtual memory, since they cannot be broken

into parts that might wind up on different pages. Since the instructions are simple their

execution time is very low and so the processor cycle time was reduced. Due to the uniform

length and execution time of RISC instructions this architectural approach is highly

supportive of pipelined and superscalar processors.

4. RISC architecture usually supports only one or two data types in a bid to simplify the

instruction set and associated hardware. These two data types are the integer and floating

point data types.

5. RISC branches avoid pipeline penalties. A branch instruction in a pipelined computer will

normally delay the pipeline until the instruction at the branch address is fetched The RISC

solution, commonly used is to redefine jumps so that they do not take effect until after the

following instruction; this is called the delayed branch. The delayed branch allows RISCs to

always fetch the next instruction during the execution of the current instruction.


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CHAPTER 3

CONTROLLER SPECIFICATIONS

The specifications are:-

8-bit RISC microcontroller

13-bit program counter

16-bit instruction register

Uses Harvard architecture

Program memory 8k x16

o

Address Bus - 13 bito Data Bus - 16 bit

Data memory 256 x 8

o Address Bus - 8 bit

o Data Bus - 8 bit

Data memory 256 x 8

Memory access is only through LOAD and STORE instructions

16 instructions of fixed length op-code

Sixteen 8-bit general purpose registers

Four 8-bit special purpose registers

Four ports for Input/Output Communication

All ports are bidirectional

Supports 2 flags:- Carry and Zero

The top level entity of the controller is shown in fig 63.

Fig63:-Top Level Entity:-Microcontroller


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CHAPTER 4

INSTRUCTION SET ARCHITECTURE

The Instruction Set Architecture (ISA) is the part of the processor that is visible to the

programmer or compiler writer. The ISA serves as the boundary between software and

hardware. The operation of the CPU is determined by the instruction it executes, referred to

as machine instructions or computer instructions. The collection of different instructions that

the CPU can execute is referred to as the CPUs instruction set.

4.1 Register Files

The proposed microcontroller consists of both 16 general purpose registers and 4 special

purpose registers. All the register can hold an 8 bit data. The structure of register file is

shown below.

R0

R1

R2

R3

R8

R9

R10

R11

R4R5

R6

R7

R12

R13

R14

R15

PORTA

PORTB

PORTC

PORTD

Table12: General Purpose Register

Table13: Special Purpose Register


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4.2 Instruction Formats

RISC instructions have a fix length and are easily decoded. For this microcontroller, all

instructions have a fixed-length of 16-bits. The instruction format is simple in order to be

decoded easily. The instructions are of fixed length opcode. The proposed controller supports

four different types of instruction formats are as follows.

A. Immediate type (I-type)

In immediate type instruction format, an 8-bit data is used as an immediate value.

B. Register type (R-type)

In register type instruction format, both the source and destination be register. The format is

shown below.

C. Jump type (J-type)

In jump type instruction format, it contains only the opcode and address. The address is

specified as part of instruction. The jump type instruction format is shown below.

OP Rd4 Immediate_value

OP Rd4 Rs

4

OP Address_12


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4.2 Instruction Set

The proposed microcontroller is designed to execute 16 instructions of fixed length op-code.

The instructions set for our design is shown below.

OP-CODE INSTRUCTION EXAMPLE

0000 NOP NOP

0001 MOV MOV Rd, Rs

0010 MVI MVI Rd, Immediate_value

0011 LD LD address_12

0100 ST ST sddress_12

0101 ADD ADD Rd, Rs

0110 SUB SUB Rd, Rs

0111 XOR XOR Rd, Rs

1000 CMP CMP Rd, Rs

1001 JMP JMP address_12

1010 JNZ JNZ address_12

1011 JEQ JEQ address-12

1100 IN IN port_num

1101 OUT OUT port_num

1110 BS BS bit_pos

1111 BC BC bit_pos

Table14: Instruction set

Our controller design is carry out to perform above instructions. In this MOV, ADD, SUB,

XOR, CMP instructions are register type. MVI is of immediate type; in this an 8-bit

immediate value is used as a source. LD, ST, JMP, JNZ, JEQ, IN, OUT, BS, BC is of jump

type; in this only opcode and address is present.


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CHAPTER 5

INTERNAL ARCHITECTURE

Fig64: Internal Architecture of custom controller

The figure 64 repents the internal architecture of our proposed custom controller. Mainly it is

having 4 units

1. FETCH UNIT

2. DECODE UNIT

3.

EXECUTE UNIT

4. CONTROL UNIT

The Fetch unit fetches the instructions from the program memory. After the execution of

fetch operation, it generates s completion signal to control unit. The control unit enables the

decode module, and decode the instruction according to the decoding algorithm. After the

completion of decode module, it provides a decode completion signal. Then control unit

enables the execution unit and after the completion of execution, the fetch module will be

enabled.


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CHAPTER 6

STAGE CONTROL UNIT

The proposed microcontroller follows a non-pipelined architecture. So the stage control unit

controls the flow for executing an instruction. This control unit monitors the completion

signal of each unit and once the completion signal is available, then it enables the other unit

for subsequent operation. The top level entity is shown in figure65.

Fig65: Top Level Entity:-Stage Control Unit

The flow of executing an instruction in our microcontroller is FETCH, DECODE then

Execute. The stage control unit controls this flow by checking the completion signal from

each unit and enables the next unit to continue the execution. The stage control unit accepts

the completion signal as inputs and enable signal as output. It has a reset signal to reset the

entire unit.

The flow chart for the stage control unit is shown in figure 66. It has 5 states, RESET,

FETCH_aft_rst, Fetch, Decode, and Execute. In RESET state all the units are in reset state.In

this state no unit is in enabled. After the removal of reset it comes to the FETCH_aft_rst. In

this state it enables the fetch unit and waits for the completion signal from fetch unit. If

fetch_comp signal is HIGH then it goes to DECODE state and enables the decode unit and

wait in the same state for the completion signal. If the Dco_comp signal is HIGH then it

moves to the Execute state and enables the execute state and waits for the completion signal

from execute unit. If Exe_comp signal is HIGH then it goes to the FETCH unit enables the

fetch units and continous with decode ste and so on.

Exe_comp

Dco_comp

Fetch_com

STAGE

CONTROL


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Fig66: Flow Chart-Stage Control Unit


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The fetch unit fetches the in

Program counter (PC), whicInstruction Register (IR) whi

entity of a fetch unit is shown

The fetch unit have an enab

completion of fetch operatio

diagram for the fetch unit is s

Custom Processor

CHAPTER 7

FETCH UNIT

structions from program memory. The fetc

holds the address of next instruction to bch holds the current instruction to be exec

in figure 67

ig67: Top level Entity-Fetch Unit

le signal (FETCH_EN) for enabling the fe

it produces a completion signal (FETCH

own in figure 68

ig68: State Diagram-Fetch Unit

esign using VHDL

h unit consist of a

e executed and anted. The top level

tch unit. After the

COMP). The state


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When a reset is applied, the Program counter and instruction register are set to be zero. After

the removal of reset it comes to the work state and checks for the fetch enable signal, if it is

enabled it places the program counter value on to the address bus of program memory and

provides a read signal to the program memory. Within the one clock cycle duration the

program memory will performs the read operation.

In update state the value on to the data bus of the program memory is copied to the

instruction register and program counter is incremented by one. After this operation a fetch

completion signal is given to the stage control unit and state changed to work state.


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CHAPTER 8

DECODE UNIT

The decode unit in the processor performs the decoding of the instruction register obtained

from the fetch unit. The top level entity of the fetch module is shown in figure 69.

Fig69: Top Level Entity:-decode Unit

The input to the decode module is Inst_reg, a 16 bit register from the fetch unit. It has output

of destination register (4-bit), source register (4-bit), immediate bus (8-bit), Branch address

(12-bit), and a bit position (3 bit). The source and destination register is used to identify the

source and destination registers used. The immediate bus is used to hold an 8-bit immediate

value for immediate data transfers. The branch address bus is a 12-bit bus used to hold the

addresses for jump operations. The Bit_pos bus is a 8-bit used for holding the bit position for

the bit set and clear operations. The figure 70 shows the state diagram used for the decode

operations.

Fig70: State machine:-Decode unit


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The state machine of the decode unit contains 4 states; RESET, IDLE, DECODE,

DECODE_COMP. The RESET state is for reset operations. The IDLE state is the default

state in decode unit. It checks for the enable signal of the decode unit. If it is enabled then it

moves to the DECODE state otherwise it stays in IDLE state. In DECODE state it performs

the decode operation and moves to the DECODE_COMP state and produces a decode

completion signal. The operations done at DECODE state is shown in figure 71.

Fig71: Working of DECODE state

In decode state first it checks for the first 4 bit to identify the opcode, based on that it

performs the appropriate information extraction. The above figure shows the some of the

information extraction done during the decode operation.


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CHAPTER 9

EXECUTION UNIT

The execution unit performs the execution of the instructions that is already decoded. Theexecution unit is divided into several subunits to perform operations. The structure of an

execution unit is shown in figure72.

Fig72: Structure:-Execution Unit

The Execution unit performs the proposed instruction set (16 instructions). The 16

instructions are grouped into 7 sub units which are described below.

A) MOVE unit

The MOVE unit is designed to perform MVI and MOV instructions. The MVI is move

immediate. It performs the immediate movement of an 8-bit data to destination register. The

example is shown below

MVI R0, 00010010

The above instruction performs the movement of immediate value 00010010 to the

destination register r0. The MOV instruction performs the movement of data between source

and destination registers. The example is shown below

MOV R1, R2

The above instruction performs the movement of the content of R2 into R1.

MOVE

ARITHMETIC

JUMP

NOP

LOAD

STORE

IN and

OUT

SET and

CLEAR

PORT1

PORT2

PORT3

PORT4LOGIC


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The flow chart for the MOVE unit is shown in figure 73.

Fig73: Flow Chart-- MOVE unit

The default state is RESET state. After the reset release it moves to the MOV_STATE, and

checks for the enable signal. If it is enabled then it checks the instructions to be executed. If

the instruction is MVI then it performs the immediate data movement or if the instruction is

MOV then it performs data movement between the source and destination registers. After the

execution of the instruction it moves to the completion state and provides an execution

completion signal.

B) ARITHMETIC unit

The ARITHMETIC unit is designed to perform ADD and SUB instructions. The ADD

instruction performs the addition of content in registers. The example is shown below.

ADD R0, R1

The above instruction performs the addition of contents in register R0 and R1. After the

addition the result of operation is stored in destination register (R0). If any carry occur during

the addition operation a carry flag is set. The content of register R1 is not altered.


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The SUB instruction performs the subtraction of contents in register. The example is shown

below.

SUB R0, R1

The above instruction performs the subtraction of contents in register R0 and R1. After the

subtraction the result of operation is stored in destination register (R0). If any borrow occur

during the subtraction operation a carry flag is set. The content of register R1 is not altered.

The flowchart is used is shown in figure 74.

Fig74: Flow Chart-- ARITMETIC unit

The default state is RESET state. After the reset release it moves to the ARITH_STATE, and

checks for the enable signal. If it is enabled then it checks the instructions to be executed. If

the instruction is ADD then it performs the addition or if the instruction is SUB then it

performs the subtraction between the source and destination registers. After the execution of

the instruction it moves to the completion state and provides an execution completion signal.


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C) LOGIC unit

The ARITHMETIC unit is designed to perform XOR and CMP instructions. The XOR

instruction is used performs the Exclusive-OR operation between the source and destination

registers. The example is shown below.

XOR R2, R3

The above instruction performs the Exclusive-OR operation between registers R2 and

R3.After the execution of operation the result is stored on to the register R2. The content of

register R3 is not altered. If the result of operation is zero then a zero flag is set.

The CMP instruction is used to perform comparison between source and destination registers.

The example is shown below.

CMP R2, R3

The above instruction performs the comparison operation between registers R2 and R3. After

the execution of operation the result is stored on to the register R2. If the contents of registers

are same the zero flag is set or otherwise it is reset. The content of registers is not altered after

the execution.

D) LOAD_STORE unit

The LOAD_STORE unit is designed to perform LD and ST instructions. The base register

used for load and store operation is R0.The LD instruction is used to perform the LOAD

operation. As a part of instruction an 8-bit data memory address is specified. The example is

shown below.

LD 00100000

The above instruction loads the content of memory location 00100000 (0x20H) in the base

register R0.

The ST instruction is used to perform the STORE operation. The memory address is specified

as a part of the instruction. The example is shown below.

ST 00100000

The above instruction stores the contents of base register on to the memory location

00100000 (0x20H).


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E) JUMP unit

The JUMP unit is designed to perform JMP, JNZ, and JEQ instructions. It performs the jump

in program memory. The jump address is specified as a part of instruction. The JMP is an

unconditional jump instruction and JNZ and JEQ are conditional jump instruction. The

maximum supported jump in program memory is 212

. This unit works on the content of status

of flag registers. The example is shown below

JMP 0x020

JNZ 0x1FF

JEQ 0X2FF

In the above instruction JMP 0x020 it jumps to the program memory location 0x020.For this

instruction only the program counter (PC) value is substituted with jump address, and normal

instruction fetch continuous. In the instruction JNZ0x1FF it jumps to the program memory

location 0x1FF only the zero flag is in reset condition (active LOW). If the zero flag set then

this instruction is not been executed. The instruction JEQ 0x2FF it jumps to the program

memory location 0x2FF, only the zero flag is set. If the zero flag is low then this instruction

is not been executed.

F) IN_OUT unit

The IN and OUT instructions used for transferring data to and from the Input/output ports.

The IN instruction stores the data from port to the base register R0. The OUT instruction

stores the data on to the I/O port from base register R0. The address of the port is shown in

table 15.

PORT NAME PORT ADDRESS

PORT1 00000001

PORT2 00000010

PORT3 00000011

PORT4 00000100

Table15: Port Address


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The example is shown below

IN 00000001

OUT 00000001

The above IN instructions stores the status of the port 00000001 to the base register R0. The

OUT instructions load the base register on to the port 00000001. All the ports are directly

mapped to the first four locations in the data memory.

G) SET_CLEAR unit

The SET_CLEAR unit is used to perform bit setting and resetting of the specified register.

This operation is done by specifying the bit position as a part of the instruction. The example

is shown below.

BS R0, 00000001

The above instruction sets (high) the first position in the R0 register.

BC RO, 00000000

The above instruction resets (zero) the zeroth

bit position in R0 register.

H) NOP unit

The NOP unit is used to perform the no operation. This operation used to wait the operation

of the controller to 3 clock cycle. It doesnt alter the content of any register. The example is

shown below.

NOP

The above instruction is used to perform the no operation.


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Custom Processor

CHAPTER 10

SIMULATION RESULT

MOV R1, 00000100

esign using VHDL


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Custom Processor

MOV R2, R1

esign using VHDL


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CHAPTER 11

SYNTHESIS REPORT

The proposed microcontroller is designed by using VHDL and synthesised by using

ALTERA QUARTUS II for ALTERA STRATIX II EP2S60F672C3N FPGA. The

synthesised report is shown in figure 75.

Fig 75: Synthesis Report-Custom Controller

The Register Transfer level representation of the custom controller is shown in figure 76.

Fig76: RTL view:-Custom Controller


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If you have any quries please feel free to contact

aneesh [email protected]

custom processor design using vhdl

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