13 February 2010 2nd Workshop Trasgo project 1

The Front-End Electronics of the The Front-End Electronics of the HADES timing RPCs wall.HADES timing RPCs wall.

Daniel Belver Fernández LabCAF-University of Santiago de Compostela

13 February 2010 2nd Workshop Trasgo project 2

OUTLINE

• The HADES tRPC TOF wall.

• The Front-End Electronics (FEE) developed for the RPCs.

• FEE performances.

– Time resolution.

– Calibration of the ‘Charge to Width’ algorithm.

– In beam results.

• Summary of the main FEE performances.

• Adaptation of the FEE to TRASGO detector.

13 February 2010 2nd Workshop Trasgo project 3

HADES tRPC TOF wall

13 February 2010 2nd Workshop Trasgo project 4

t1

t2

FEE-DBOs (108 DBOs/sector x6)

FEE-MBOs (16 MBOs/sector x6)

Mechanical support board, providing power supply, test signal and threshold DAQs.

Amplifying and timing discrimination board (QtoW algorithm).

The RPC Front-End Electronics (FEE)

13 February 2010 2nd Workshop Trasgo project 5

FEE and DAQ system

4 MBOs/TRB 8 DBOs/MBO 4 cells/DBO

Trigger ∑

Front-EndMBO DBO

RPC signals

RPC signals

RPC cells

DC-DCconverter

Commercial power supply

Low voltage system

5

3.3

-5

5V,-5V,3.3V48V

Ethernet

TRB

Data acquisition system

4 TRB/sector 2 LV/sector

See M. Traxler talk

13 February 2010 2nd Workshop Trasgo project 6

• 4-channel & 6-layer board connected to 4 RPC cells.

• 1 amplifier (G=35.5 dB, BW=2 GHz, NF=4.5 dB).

• Generates timing and trigger signals.

• Time & charge encoded in a single LVDS digital output (low power consumption and high noise immunity).

- Leading edge Arrival time (ToF measure).

- Pulse width Charge (QtoW algorithm).

DaughterBOard (DBO)

1 32 4

Width~charge (QtoW)

Arrival time

LVDS

All SMT available components (R & C 0402 size)

SAMTEC connector (40 pins, 0.8 mm

pitch)

Area=5x4.5 cm2

13 February 2010 2nd Workshop Trasgo project 7

TI OPA690 amp integrates the amplified signal (QtoW algorithm)

PHILIPS BGM1013 amp (35.5 dB at 1 GHz) Protected by PHILIPS BAV199 2-diodes

RPC cell

One DBO channel: analog stage

Amplified RPC signal

Integrated signal

C

QtoW integrator

Amplifier

ToF Thresholds

In

OPA690

BGM1013

PECL-LVDS converter

Trigger

In/Out Connector

Discriminator

QQ/

LE/LE

R

MAX9601

SN65LVDSHSEC8

MBO-DB0

BFT92

4ch

4ch

PECL-LVDS

Test Pulse

Baseline level

4ch x Baseline levels4ch x ToF Thresholds

2x2ch Test Pulse

R

C

QtoW integrator

Amplifier

ToF Thresholds

In

OPA690

BGM1013

PECL-LVDS converter

Trigger

In/Out Connector

Discriminator

QQ/

LE/LE

R

MAX9601

SN65LVDSHSEC8

MBO-DB0

BFT92

4ch

4ch

PECL-LVDS

Test Pulse

Baseline level

4ch x Baseline levels4ch x ToF Thresholds

2x2ch Test Pulse

R

Analog stage

Digital stage

13 February 2010 2nd Workshop Trasgo project 8

MAX9601 dual PECL discriminator: LE used for cut/shape the output pulse

TI SN65LVDS100 PECL-LVDS converter

PHILIPS BFT92 PNP wideband (5 GHz) transistor for multiplicity trigger sum

One DBO channel: digital stage

Discriminator output

Latch Enable (LE)

Latch Enable/ (LE/)

C

QtoW integrator

Amplifier

ToF Thresholds

In

OPA690

BGM1013

PECL-LVDS converter

Trigger

In/Out Connector

Discriminator

QQ/

LE/LE

R

MAX9601

SN65LVDSHSEC8

MBO-DB0

BFT92

4ch

4ch

PECL-LVDS

Test Pulse

Baseline level

4ch x Baseline levels4ch x ToF Thresholds

2x2ch Test Pulse

R

C

QtoW integrator

Amplifier

ToF Thresholds

In

OPA690

BGM1013

PECL-LVDS converter

Trigger

In/Out Connector

Discriminator

QQ/

LE/LE

R

MAX9601

SN65LVDSHSEC8

MBO-DB0

BFT92

4ch

4ch

PECL-LVDS

Test Pulse

Baseline level

4ch x Baseline levels4ch x ToF Thresholds

2x2ch Test Pulse

R

Analog stage

Digital stage

13 February 2010 2nd Workshop Trasgo project 9

MotherBOard (MBO)

• Interfaces board between DBO and DAQ system (TRB).

• 8-layer board providing mechanical support to 32 channels (8 DBOs) or 12 channels (3 DBOs).

Area 16.5x6.5 cm2

Area 40x6 cm2

13 February 2010 2nd Workshop Trasgo project 10

– Delivers the timing signals from 8 DBOs to the TRB.

– DBO supply voltages (+5V,-5V,+3.3V) Low-Dropout Regulators (ripple filtering).

– DACs for the thresholds of the discriminator (DAC program interface).

– Test signals distribution.

– Combines the 32 multiplicity DBOS signals low level trigger signal.

MBO schematic

13 February 2010 2nd Workshop Trasgo project 11

FEE performances: time resolution

Q=Vmax x e-t/RinC

RinC>>tr

Q=C x V

σt(FEE+TRB) <40 ps/ch

ToF threshold=-20mVσt(FEE) <17 ps/ch

(Q>90 fC)

13 February 2010 2nd Workshop Trasgo project 12

FEE performances: QtoW calibration

• Charge measurements through QtoW algorithm, using pulser signals and RPC signals measurements.

Streamer region

Avalanche region

13 February 2010 2nd Workshop Trasgo project 13

In-beam results

QtoW spectrums for one cell

σt=76 ps 3σ tails=2.2%

ToF threshold=-50 mV

13 February 2010 2nd Workshop Trasgo project 14

Summary of the FEE performances

13 February 2010 2nd Workshop Trasgo project 15

FEE adaptation to TRASGO

• Immediately application of the FEE to the TRASGO project.

Possible FEE positions

Cut view of the TRASGO

DBOs placed over one MBO

TRB between RPC planes

13 February 2010 2nd Workshop Trasgo project 16

• Power consumption for 128 channels:

• 1 TRB 10-20 W.• 4 MBOs+32 DBOs 90-100 W.

• Possible solutions (new FEE approach):

– Adapt other RPC-FEE as NINO (CERN) or PADI (GSI).

– Integrate the FEE in an integrated circuit (ASIC).

Power consumption ≈120 W per TRB

FEE improvements for TRASGO

Easy for the power supply but not for solar panels.

13 February 2010 2nd Workshop Trasgo project 17

Thanks for your attention!