Design for Testability Theory and Practice

Lecture 6: Combinational ATPGATPG problemExampleAlgorithmsMulti-valued algebraD-algorithmPodemOther algorithmsATPG systemSummaryCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*

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ATPG ProblemATPG: Automatic test pattern generationGivenA circuit (usually at gate-level)A fault model (usually stuck-at type)FindA set of input vectors to detect all modeled faults.Core solution: Find a test vector for a given fault.Combine the core solution with a fault simulator into an ATPG system.Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*

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What is a Test?Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*X100101XXStuck-at-0 fault1/0Fault activationPath sensitizationPrimary inputs(PI)Primary outputs(PO)Combinational circuit1/0Fault effect

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Multiple-Valued AlgebrasSymbol

DD01XG0G1F0F1Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*AlternativeRepresentation

1/00/10/01/1X/X0/X1/XX/0X/1FaultyCircuit

0101XXX01Fault-freecircuit

1001X01XXRothsAlgebra

MuthsAdditions

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An ATPG ExampleFault activationPath sensitizationLine justificationCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*1D

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ATPG Example (Cont.)Fault activationPath sensitizationLine justificationCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*1DDDD101

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ATPG Example (Cont.)Fault activationPath sensitizationLine justificationCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*1DDDD10111Conflict1

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ATPG Example (Cont.)Fault activationPath sensitizationLine justificationCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*1DDDD011BacktrackD

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ATPG Example (Cont.)Fault activationPath sensitizationLine justificationCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*1DDDD011DTest found01

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D-Algorithm (Roth 1967)Use D-algebraActivate faultPlace a D or D at fault siteJustify all signalsRepeatedly propagate D-chain toward POs through a gateJustify all signalsBacktrack ifA conflict occurs, orAll D-chains dieStop whenD or D at a PO, i.e., test found, orSearch exhausted, no test possibleCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*

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Example: Fault A sa0Step 1 Fault activation Set A = 1Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*D1DD-frontier = {e, h}

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Example ContinuedStep 2 D-Drive Set f = 0Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*D10DD

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Example ContinuedStep 3 D-Drive Set k = 1Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*D10DD1D

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Example ContinuedStep 4 Consistency Set g = 1Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*D10DD1D1

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Example ContinuedStep 5 Consistency f = 0 Already setCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*D10DD1D1

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Example ContinuedStep 6 Consistency Set c = 0, Set e = 0Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*D10DD1D100

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Example: Test FoundStep 7 Consistency Set B = 0Test: A = 1, B = 0, C = 0, D = XCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*D10XDD1D1000

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Podem (Goel, 1981)Podem: Path oriented decision makingStep 1: Define an objective (fault activation, D-drive, or line justification)Step 2: Backtrace from site of objective to PIs (use testability measures guidance) to determine a value for a PIStep 3: Simulate logic with new PI valueIf objective not accomplished but is possible, then continue backtrace to another PI (step 2)If objective accomplished and test not found, then define new objective (step 1)If objective becomes impossible, try alternative backtrace (step 2)Use X-PATH-CHECK to test whether D-frontier still there a path of Xs from a D-frontier to a PO must exist.Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*

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Podem ExampleCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*(9, 2)S-a-11. Objective 002. Backtrace A=03. Logic simulation for A=04. Objective possible but not accomplished

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Podem Example (Cont.)Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*(9, 2)S-a-11. Objective 005. Backtrace B=06. Logic simulation for A=0, B=07. Objective possible but not accomplished000

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Podem Example (Cont.)Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*(9, 2)S-a-11. Objective 008. Backtrace E=09. Logic simulation for E=010. Objective possible but not accomplished00000

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Podem Example (Cont.)Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*(9, 2)S-a-11. Objective 0011. Backtrace D=012. Logic simulation for D=013. Objective accomplished0000000

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An ATPG SystemCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*Random pattern generatorFault simulatorFault coverage improved?Random patterns effective?Save patternsDeterministicATPG (D-alg. or Podem)yesnoyesnoStop if fault coverage goal achieved

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SummaryMost combinational ATPG algorithms use D-algebra.D-Algorithm is a complete algorithm:Finds a test, orDetermines the fault to be redundantComplexity is exponential in circuit sizePodem is also a complete algorithm:Works on primary inputs search space is smaller than that of D-algorithmExponential complexity, but several orders faster than D-algorithmMore efficient algorithms available FAN, Socrates, etc.See, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 7.

Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*

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Exercise 2: Lectures 4-6For the circuit shown aboveDetermine SCOAP testability measures.Derive a test for the stuck-at-1 fault at the output of the AND gate.Using the parallel fault simulation algorithm, determine which of the four primary input faults are detectable by the test derived above.Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*

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Exercise 2: AnswersCopyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*(1,1) 4(1,1) 3(1,1) 4(1,1) 3(2,3) 2(4,2) 0 SCOAP testability measures, (CC0, CC1) CO, are shown below:

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Exercise 2: Answers Cont.Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6* s-a-1000 A test for the stuck-at-1 fault shown in the diagram is 00.

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Exercise 2: Answers Cont.Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 6*PI1=0PI2=00 0 1 0 00 0 0 0 10 0 0 0 10 0 0 0 00 0 0 0 10 0 0 0 1No faultPI1 s-a-0PI1 s-a-1PI2 s-a-0PI2 s-a-1PI2 s-a-1 detected Parallel fault simulation of four PI faults is illustrated below.Fault PI2 s-a-1 is detected by the 00 test input.

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