dasia smcs spw - kosrad.ru astrium_uod_aae... · wp 1.1 prelim. router req. -wp 1.2 test bed...

SpW Router Final Presentation

24/25.09.2008 at ESTEC

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Astrium ASE2

p2

Outline

General Project PresentationAstrium GmbH

Design, architecture and features of the SpW-10X and thedeveloped Test Equipment University of Dundee

ASIC Features, test approach and characterisation resultsAustrian Aerospace

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Astrium ASE2

p3

Project Organization and ObjectivesETD-031 High Speed Interconnect NetworkSpW Router: Development Coordination & ValidationAstrium GmbH with University of Dundee • Coordinate SpW Router development• Validate the design of the SpW Router• Set a complete test bed with SpW nodes, PC SW and a Logic Analyzer

ESM-006 SpaceWire Router DevelopmentAustrian Aerospace with University of Dundee• develop a VHDL model for a SpW Coder/Decoder Core• develop a VHDL model for a SpW Router• manufacture FPGA and ASIC of the SpW Router

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Astrium ASE2

p4

Project - Flow

Group 0: Selection of Sub contractor- WP 0.2 Preparation ITT for ESM-006- WP 0.3 Evaluation of proposals (TEB)- Negotiation

Group 1: Preparatory Developments- WP 1.1 Prelim. Router Req. - WP 1.2 Test bed Definition- WP 1.2 Router Detailed Validation Plan - WP 1.3 New Com. Ctrl SMCS332-FPGA- WP 1.3 SpaceWire-PCI Board - WP 1.4 Break-out box - WP 2.3 PCBs equipped with Routers

ETD-031

Group 3: Reduced Validation of Router- ASIC- WP 3.1 Router ASIC Test PCB- WP 3.3 Router ASIC Validation

Group C: SpaceWire Router ASIC- WP 3.0 Design Update - RTR&CODEC - WP 3.3 Router ASIC Implementation

Group 2: Validation of the Router-FPGA- WP 2.1 Validation of the Router FPGA- WP 2.5 Reduced Valid. Plan for Router ASIC- Group2 Review

ESM-006Group A: SpaceWire CODEC VHDL Core- WP 1.3 CODEC VHDL + test benches - Group A Review - Validated CODEC VHDL Core

Group B: SpaceWire Router – FPGA- WP 2.1 Router ASIC Req.&Func. Spec.- WP 2.3 Router ASIC&T.Bench VHDL- Router ADR - WP 2.4 Router FPGA + Data Sheet

- Phase 1 Review + WG Meeting

- Final Presentation + WG Meeting

- WG Meeting

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Astrium ASE2

p5

Project History

• First Discussions: 2001

• Signature ETD-031 contract: June 2002

• Signature ESM-006 contract: February 2003

• Delivery ASIC prototype: May 2008

• Final presentation September 2008

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Astrium ASE2

p6

Project ChangesCCN1: January 2003• Update project schedule • Support improvement of the RTL model of the CODEC : independent transmit clock and variable transmit rates ; independent receive buffer clock rates.

CCN2: June 2005• Change of router configuration protocol to RMAP as in ECSS-E-50-12 Part 2 Draft C• Change in target FPGA and Test board complexity• 8 SpW ports instead of 7 • 2 parallel external ports instead of 1 • added PLL to Rx Clock

CCN3: February 2007• Upgrade of RMAP protocol to draft F• Modification of SpW Router design; validation at FPGA

• CRC computation, alignment with other designs• Input port timeout settings

• Extension of ASIC validation

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Astrium ASE2

p7

Project – HW-Deliverables

- CODEC VHDL (license available for ESA members)

- SMCS332SpW FPGA

- Break Out Box -> SpW Monitor (for use with a logic analyzer)

- SpW Router FPGA

- Test board with SpW Router FPGA

- SpaceWire-PCI card (with SMCS332SpW FPGA)

- Router ASIC (ATMEL MH1RT, Rad-Hard, 0.35um)

- Test board with SpW Router ASIC

8

SpaceWire Router ASICSteve Parkes, Chris McClements, Stuart Mills,Iain Martin, Ray Manston, Peter Mendham,Jon Bowyer, Martin Dunstan, David Dillon

Space Technology Centre, University of Dundee

All the SpaceWire you need

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Astrium ASE2

p9

OverviewSpaceWire CODECLink MonitorSpaceWire PCIRouter FPGARouter ASICRouter ASIC capabilities

9

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Astrium ASE2

p10

SpaceWire CODECESA SpW(b)

VHDL IP core for SpaceWire CODEC

Widely used ESA projectsCommercial projectsInternational agencies and industry

Extensively configurable using generics

10

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Astrium ASE2

p11

Link MonitorBreak-out box for SpaceWireEnables SpaceWire traffic to be captured on standard logic analyserOperates at up to 200 Mbits/sIncorporates LEDS for immediate link status indication

11

SpW Unit SpW Unit

SpaceWireMonitor

SpaceWireMonitor

Logic Analyser

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Astrium ASE2

p12

Link Monitor

12

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Astrium ASE2

p13

SpaceWire PCISpaceWire interface boardPCI board with 3 SpW interfacesUses FPGA version of SMCS 332 SpWLinks run at 200 Mbits/sExtensive software support

Windows and Linux driversQuick start applicationSystem test support applicationSource code application example

13

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Astrium ASE2

p14

SpaceWire PCI

14

SMCSFPGA

DUALPORTRAM

PCI

SPW

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Astrium ASE2

p15

Router FPGARouter FPGA designed by UoD

Same VHDL code as final routerExcept

BuffersPLL for clock

VHDL simulation of PLL clock to give same functionalityAimed to test as much of the final router code as possible

Router FPGA unit designed by AstriumIncorporating

Router FPGASpaceWire connectorsParallel/time-code port connectorsPower suppliesReset

15

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Astrium ASE2

p16

Router FPGA

16

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Astrium ASE2

p17p17

FPGA / ASIC Validation

Validation Testbed- Two PCs with SMCS332SpW PCI cards- Up to 4 router boards- SpW Monitor boxes- Validation SW on PC

Validation of 1 router with PCI cardOr4 router with 2 PCI cards

SpaceWire-PCI Node with SMCS332 FPGA Cascaded routers

PCPC

SpaceWire-PCI Node with SMCS332 FPGA

Monitorbox

Software applications in PCs provide packet source,packet sink and network configuration functions.

LogicAnalyser

Monitorbox

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Astrium ASE2

p18

Router FPGA

p18

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Astrium ASE2

p1919

SpW-10X

SpW-10X Architecture

RoutingSwitch

SpW Port 1

SpW Port 2

SpW Port 3

SpW Port 4

SpW Port 5

SpW Port 6

SpW Port 7

SpW Port 8

Time-CodeInterface

ConfigurationPort 0

RoutingTable

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Astrium ASE2

p2020

SpaceWire Ports

SpaceWire compliantData Signalling Rate

200 Mbits/s maximumSelectable 2 – 200 Mbits/s

Each SpaceWire port can run at a different speedLVDS drivers and receivers on chip

Avoids size, mass, cost of external LVDS chipsReceiver auto-start modePower control

Each SpaceWire port can be completely disabledincluding clock tree

LVDS can be “tri-stated” with auto-enableLinks can be held disconnected until there is data to send

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Astrium ASE2

p2121

Parallel Ports

Parallel ports to support connection to ProcessorsSimple logic

8-bit data + control/data flagFIFO type interfaceOperate at speed of SpaceWire links

i.e. 200 Mbits/s

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Astrium ASE2

p2222

Routing Switch

Switches packet being received to Appropriate output portSpaceWire and Parallel ports treated the sameNon-blocking

If the required output port is not being used already Guaranteed to be able to forward packetRapid packet switching timesLow latency

Wormhole routing

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Astrium ASE2

p2323

Configuration Port

Used to configure router deviceRouting tablesLink speedsPower statesEtc

Used to read router statusRMAP Remote Memory Access ProtocolUsed for reading and writing configuration port registersRouter can be configured over

Any SpaceWire portAny Parallel port

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Astrium ASE2

p2424

Time-Code Port

Sends and receives time-codes

Tick-inInternal time-counter incremented and time-code sentOrValue on the time-code input port is sent as a time-code

Tick-outIndicates valid time-code receivedValue of time-code on time-code output port

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Astrium ASE2

p2525

Status/Configuration InterfaceOn power up holds some configuration informationThereafter provides status according to four address lines0-10: Port status

0: Configuration port1-8: SpaceWire port9-10: Parallel port

11: Network discoveryReturn portThis is a router

12: Router controlEnables and timeouts

13: Error active14: Time-code15: General purpose

Contents of general purpose registerSettable by configuration command

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Astrium ASE2

p26

Router Features

Path and logical addressingGroup adaptive routingPriority arbitrationStart on RequestDisable on SilenceWatchdog timers

p26

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Astrium ASE2

p27

Start on Request

p27

R1 R21 2 1 2

Auto-Start default mode and Start on Request enabled in both routersConnection

Attempt

2

Data TransferPacket with address 2

22Link Started

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Astrium ASE2

p28

Disable on Silence

p28

R1 R21 2 1 2

Auto-Start default mode, Start on Request, and Disable on Silence enabled in both routers

Packet with address 2Connection Attempt

Data transferLink disabled after timeout periodLink StartedData transfer completed

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Astrium ASE2

p29

Watchdog Timers

p29

R1

1

2

3

4

5

645

R2

1 4

2

3

5

6

44

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Astrium ASE2

p30

Watchdog Timers

p30

R1

1

2

3

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6

R2

1 4

2

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5

6

44Blocked !

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Astrium ASE2

p31

Watchdog Timers

p31

R1

1

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3

4

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R2

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44

Time Out

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Astrium ASE2

p32

Watchdog Timers

p32

1

2

3

4

5

6

1 4

2

3

5

6

44

EEP

R1 R2

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Astrium ASE2

p33

Watchdog Timers

p33

1

2

3

4

5

6

1 4

2

3

5

6

R1 R2

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Astrium ASE2

p3434

Router Prototype Implementations

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Astrium ASE2

p3535


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Astrium ASE2

p3636


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Astrium ASE2

p3737


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Astrium ASE2

p38

SpW-10X Development System

38

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Astrium ASE2

p3939


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Astrium ASE2

p40p40

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Astrium ASE2

p4141

Applications – Stand Alone Router

SpW-10XRouter

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Astrium ASE2

p4242

Applications – Instrument Interface

High RateInstrument

InstrumentControlFPGA

SpW-10XRouter

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Astrium ASE2

p4343

Applications – Memory Interface

MemoryBanks

MemoryControlFPGA

SpW-10XRouter

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Astrium ASE2

p4444

Applications – Processor Interface

Processor

I/OControlFPGA

SpW-10XRouter

Memory

SpW Router Verification and ASIC implementation

Christian Gleiss, Gerald Kempf, Manfred Knobl, Roman ZanglAustrian Aerospace24/25.09.2008 at ESTEC

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Astrium ASE2

p46

Outline ASIC Test, Implementation and Characteristics

SpW-10X Verification

SpW-10X ASIC Implementation

SpW-10X ASIC Production Tests

SpW-10X ASIC Performance and Characteristics

SpW-10X ASIC Commercialisation

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Astrium ASE2

p47

SpW-10X (SPROUT) Verification

VHDL Testbench with self-checking scenarios

RTL and Netlist (FPGA and ASIC) verified with TB

Code coverage checked for RTL simulations

Analysis of requirements not possible to simulate

Timing of ASIC verified with static timing analysis

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Astrium ASE2

p48

SpW-10X (SPROUT) Testbench Environment

*.log

P:\ESMS\ENG\SPROUT\VERIF\POWERPOINT\VISIO\SPROUT_VERIFICATION_ENVIRONMENT.VSDRevision: V1.0, 11.02.2003 by tocLast change: 02.07.2003 by toc

Unit UnderTest (UUT)

SPROUTinputs

SPROUTenvironment

(ENV)

*.cmd

SPROUToutputsparser

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Astrium ASE2

p49

*.log



SPROUTinputs

SPROUTenvironment

(ENV)

*.cmd

SPROUToutputsparser


VHDL model of SPROUT

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Astrium ASE2

p50


*.log



SPROUTinputs

SPROUTenvironment

(ENV)

*.cmd

SPROUToutputsparser

Supply UUT with all input signals and check output signals

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Astrium ASE2

p51


*.log



SPROUTinputs

SPROUTenvironment

(ENV)

*.cmd

SPROUToutputsparser

*.cmd Simulation flow defined by command script; read and processed by parser

Notes, errors, success messages and other useful information recorded in simulator logging file.

*.log

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Astrium ASE2

•

•

•

•

p52

Command:

Parser assigns commands to other units by command bus.

Acknowledge:

Via acknowledge bus units tell the parser

completion of command,

command completed, but no logging information shall be recorded,

unknown command or

syntax error.

TB Spwr IF

TB Spwr Unit 7DOUT(6)

DIN(6)

SIN(6)

SOUT(6)

*.log

Revision: V1.0, 27.06.2003 by tocLast change: 19.03.2004 by toc

*.cmd

Com

man

d

Ack

now

ledg

e

TB Spwr IF

TB Spwr Unit 1Active

Switc

h O

ff TB

TB Spwr IF

TB Spwr Unit 8DOUT(7)

DIN(7)

SIN(7)

SOUT(7)

SYSCLK

RST_N

POR_TX_RATE_N

POR_ADDR_SELF_N

POR_TIMEOUT_EN_N

POR_SEL_TIMEOUT0_N

POR_START_ON_REQ_N

POR_DISABLE_ON_SILENCE_N

CommandScripts

LoggingFiles

SpwrCheck

SpwrCtrl

SpwrCheck

SpwrCtrl

SpwrCheck

Parser

CommonCtrl Unit

SpwrCtrl

DOUT(0)

DIN(0)

SIN(0)

SOUT(0)

EXT_TICK_IN

EXT_TIME_IN

SEL_EXT_TIME

TIME_CTR_RST

EXT_TICK_OUT

EXT_TIME_OUT

ExternalTime Ctrl

EXT_CLK

STAT_MUX_OUT

STAT_MUX_ADDR

EXT_IN_DATA1

EXT_IN_FULL_N1

EXT_IN_WRITE_N1

EXT_OUT_DATA1

EXT_OUT_EMPTY_N1

EXT_OUT_READ_N1

External PortCtrl 2

External PortCheck 2

EXT_IN_DATA0

EXT_IN_FULL_N0

EXT_IN_WRITE_N0

EXT_OUT_DATA0

EXT_OUT_EMPTY_N0

EXT_OUT_READ_N0

External PortCtrl 1

External PortCheck 1

ExternalTime Check

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Astrium ASE2

p53

verifies the packet switching of the SpaceWire routerPacketSim

verifies the time code distribution of the SpaceWire routerTimecodeSim

verifies the link error recovery of the SpaceWire routerLinkerrorSim

verifies in conjunction with the “Performance (Timing)”analysis the performance (timing) of the SpaceWire router

PerformanceSim

verifies the ports (SpaceWire input/output ports, configuration port and external input/output port) of the SpaceWire router and their elementary functions; verifies the PLL function for all PLL configurations as well as ASIC test functions

PortSim

Verification Scripts

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Astrium ASE2

p54

Verification Analysis

Static Timing Analysis:

ASIC netlist (pre- and post-place&route) analysed

Checks all timing requirements (interfaces and internal)

Synopsys Design Compiler and partly postprocessing with Excel

Functional analysis:

Synchronisation of asynchronous signals

Some performance parameters (e.g. router latency)

Analysis of requirements not possible to simulate:

Usage of ESA SpW Codec, LVDS Buffers, … checked by inspection

Physical parameters checked by inspection of technology data sheets

RTL code line coverage checked and uncovered lines explained

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Astrium ASE2

p55

SpW-10X ASIC Implementation

Standard flow for MH1RT Gate Array implementation

Migration from FPGA to ASIC

Test and PLL functions

Memory for GAR LUT

IO buffer implementation

All memory cells except in SpW frontends SEU free cells

Due to timing reasons a few FFs (2x8 in Tx and 4 in Rx) in the 200MHz SpW frontends needs to be without special SEU protection

All other memory cells are SEU free cells from the MH1RT library

Place & Route, Timing closure

High degree of connections most critical (GAR LUT)

Timing balancing of SpW frontends

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Astrium ASE2

p56

SpW-10X Production Tests

Modified scenarios derived from the verification are used as functional test vectors

Dedicated test vectors for PLL test, memory test and scan tests have been made

Timing measurements on the SpW links are included in the functional TV

All tests have been run on the prototypes and will be used for all production components

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Astrium ASE2

p57

SpW-10X ASIC Performance and Characteristics (1)

SpW data rate configurable up to 200Mbps

Single supply voltage of 3.3V (3.0 to 3.6V)

Temperature:

Operational ambient temperature -55°C to +125°C

Maximum junction temperature +175°C

Maximum lead temperature (soldering 10 sec) +300°C

Storage temperature -65°C to +150°C

Radiation

Total dose 300Krad(Si)

No latchup up to 70 MeV/mg/cm2

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Astrium ASE2

p58

SpW-10X ASIC Performance and Characteristics (2)

Package MQFP 196 with 25 mil pin spacing

Power consumption (max):

Static Pst: 1W

OFF condition Poff: 1.6W

Total operational all SpW IF active Pop: 3.7W @ 200Mbps, 3.0W @ 100Mbps, 2.4W @ 10Mbps

Deactivated (Clk and LVDS buffer) SpW link: reduction of power by (Pop - Poff) x 0.1 + 0.06; E.g. 2 SpW deactivated @ 200Mbps -> 3.16W

Data flow has very little influence on power consumption

For lower supply voltage (<3.6V):resistive model can be used, e.g. 69.4% of power at 3.0V

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Astrium ASE2

p59

SpW-10X Commercialisation

SpW-10X ASIC is commercialised as an Atmel Application Specific Standard Component with the name AT7910E

Information (Data sheet and Users Manual) is available via the Atmel Space homepage (www.atmel.com/products/radhard/default.asp)

Atmel is the point of contact for buying the component

Star Dundee (www.star-dundee.com) gives additional technical support

Components in the following quality levels are available:

Engineering Samples: from stock

QML-Q: Q2 2009

QML-V: Q2 2009

SpW Router Validation

Stephan Fischer, Uwe Liebstückel, Paul RastetterEADS Astrium24/25.09.2008 at ESTEC

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Astrium ASE2

p61

FPGA / ASIC Validation

- FPGA validation was performed 3 times due to VHDL code modifications like RMAP implementation or check-sum modification

- Validation includes all requirements of the SpW Router Specification

- All Validations were successfully performed. Only in the first one two clarifications for the Router Specification were addressed

- Path addressing with different priority levels not implemented

- Exact value for the Output Port Timeout Interval

- ASIC Validation was performed successfully

- Atmel LVDS I/O cells disable rather than tristate.

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Astrium ASE2

p62

Lessons Learned

- Check concepts in FPGA prototypes

- Focus on design for ASIC rather design for FPGA

- FPGA validation before ASIC run reduces risk significantly

- Automated FPGA/ASIC tests are important, as the repetition of tests should always be possible

- Good teamwork was key for success

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Astrium ASE2

p6363

Conclusions

SpW-10X router has extensive capabilitiesSuitable for a wide range of applicationsDesign independently verifiedFPGA and ASIC extensively validatedASIC available now as standard product from AtmelFull range of support services available

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Astrium ASE2

p6464

dasia smcs spw - kosrad.ru astrium_uod_aae... · wp 1.1 prelim. router req. -wp 1.2 test bed...

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