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FEATURES DESCRIPTION

APPLICATIONS

0

10

20

30

40

50

60

70

80

1 10 100 1 k 10 k 100 k 1 M 10 M

Rip

ple

Re

jec

tio

n−

dB

TPS79530

RIPPLE REJECTION

vs

FREQUENCY

VIN = 4 V

COUT = 10 mF

CNR = 0.01 mFIOUT = 1 mA

IOUT = 500 mA

Frequency (Hz) Frequency (Hz)

0

0.1

0.2

0.3

0.4

0.5

100 1 k 10 k 100 k

IOUT = 1 mA

VIN = 5.5 V

COUT = 2.2 mF

CNR = 0.1 mF

IOUT = 0.5 A

TPS79530

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

Ou

tpu

t S

pe

ctr

al

No

ise

De

ns

ity

−mV

/ÖH

z

1

2

3

4

5

DCQ PACKAGE

SOT223-6

(TOP VIEW)

NR/FB

OUT

GND

IN

EN

6

GND

EN

NC

GND

NR/FB

8

7

6

5

IN

IN

OUT

OUT

1

2

3

4

DRB PACKAGE3mm x 3mm SON

(TOP VIEW)

TPS795xx

SLVS350G–OCTOBER 2002–REVISED JULY 2006

ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 500-mALOW-DROPOUT LINEAR REGULATORS

• 500-mA Low-Dropout Regulator With Enable The TPS795xx family of low-dropout (LDO),low-power linear voltage regulators features high• Available in Fixed and Adjustable (1.2-V topower-supply rejection ratio (PSRR), ultralow noise,5.5-V) Versionsfast start-up, and excellent line and load transient• High PSRR (50 dB at 10 kHz)responses in small outline, SOT223-6 and 3 x 3 SON

• Ultralow Noise (33 µVRMS, TPS79530) packages. Each device in the family is stable with asmall 1-µF ceramic capacitor on the output. The• Fast Start-Up Time (50 µs)family uses an advanced, proprietary BiCMOS• Stable With a 1-µF Ceramic Capacitorfabrication process to yield extremely low dropout

• Excellent Load/Line Transient Response voltages (for example, 110 mV at 500 mA). Eachdevice achieves fast start-up times (approximately 50• Very Low Dropout Voltage (110 mV at Fullµs with a 0.001-µF bypass capacitor) whileLoad, TPS79530)consuming very low quiescent current (265 µA,• 6-Pin SOT223 and 3 × 3 SON Packagestypical). Moreover, when the device is placed instandby mode, the supply current is reduced to lessthan 1 µA. The TPS79530 exhibits approximately 33

• RF: VCOs, Receivers, ADCs µVRMS of output voltage noise at 3.0 V output with a0.1-µF bypass capacitor. Applications with analog• Audiocomponents that are noise-sensitive, such as• Bluetooth®, Wireless LANportable RF electronics, benefit from the high-PSRR• Cellular and Cordless Telephonesand low-noise features, as well as from the fast

• Handheld Organizers, PDAs response time.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2002–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATING TABLE

TPS795xx


This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

ORDERING INFORMATION (1)

PRODUCT VOUT(2)

TPS795xxyyyz XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).YYY is package designator.Z is package quantity.

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.

(2) Output voltages from 1.3 V to 5.0 V in 100 mV increments are available; minimum order quantities may apply. Contact factory for detailsand availability.

over operating temperature (unless otherwise noted) (1)

VALUE

VIN range – 0.3 V to 6 V

VEN range –0.3 V to VIN + 0.3 V

VOUT range 6 V

Peak output current Internally limited

ESD rating, HBM 2 kV

ESD rating, CDM 500 V

Continuous total power dissipation See Dissipation Rating Table

Junction temperature range, TJ –40°C to +150°C

Storage temperature range, Tstg –65°C to +150°C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.

PACKAGE BOARD RθJC RθJA

SOT223 Low K (1) 15°C/W 53°C/W

3 x 3 SON High-K (2) 1.2°C/W 40°C/W

(1) The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3-inch (7.5 cm × 7.5cm), two-layer board with 2-ouncecopper traces on top of the board.

(2) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch × 3-inch (7,5-cm × 7,5-cm), multilayer board with 1-ounceinternal power and ground planes and 2-ounce copper traces on top and bottom of the board.

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ELECTRICAL CHARACTERISTICS

TPS795xx


Over recommended operating temperature range (TJ = –40°C to +125°C), VEN = VIN, VIN = VOUT(nom) + 1 V (1), IOUT = 1 mA,COUT = 10 µF, CNR = 0.01 µF, unless otherwise noted. Typical values are at +25°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input voltage, VIN(1) 2.7 5.5 V

Internal reference, VFB (TPS79501) 1.200 1.225 1.250 V

Continuous output current, IOUT 0 500 mA

Output voltage range TPS79501 1.225 5.5 – VDO VOutput TPS79501 (2) 0 µA ≤ IOUT ≤ 500 mA, VOUT + 1 V ≤ VIN ≤ 5.5 V (1) 0.98(VOUT) VOUT 1.02(VOUT) Vvoltage Accuracy

Fixed VOUT 0 µA ≤ IOUT ≤ 500 mA, VOUT + 1 V ≤ VIN ≤ 5.5 V (1) –2.0 +2.0 %

Output voltage line regulation (∆VOUT%/∆VIN) (1) VOUT + 1 V ≤ VIN ≤ 5.5 V 0.05 0.12 %/V

Load regulation (∆VOUT%/∆IOUT) 0 µA ≤ IOUT ≤ 500 mA, 3 mV

TPS79530 IOUT = 500 mA 110 170Dropout voltage (3)mVVIN = VOUT(nom) - 0.1 V TPS79533 IOUT = 500 mA 105 160

Output current limit VOUT = 0 V 2.4 2.8 4.2 A

Ground pin current 0 µA ≤ IOUT ≤ 500 mA 265 385 µA

Shutdown current (4) VEN = 0 V, 2.7 V ≤ VIN ≤ 5.5 V 0.07 1 µA

FB pin current VFB = 1.225 V 1 µA

f = 100 Hz, IOUT = 10 mA 59

f = 100 Hz, IOUT = 500 mA 58Power-supply ripple rejection TPS79530 dB

f = 10 kHz, IOUT = 500 mA 50

f = 100 kHz, IOUT = 500 mA 39

CNR = 0.001 µF 46

CNR = 0.0047 µF 41BW = 100 Hz to 100 kHz,Output noise voltage (TPS79530) µVRMSIOUT = 500 mA CNR = 0.01 µF 35

CNR = 0.1 µF 33

CNR = 0.001 µF 50

Time, start-up (TPS79530) RL = 6 Ω, COUT = 1 µF CNR = 0.0047 µF 75 µs

CNR = 0.01 µF 110

High-level enable input voltage 2.7 V ≤ VIN ≤ 5.5 V 1.7 VIN V

Low-level enable input voltage 2.7 V ≤ VIN ≤ 5.5 V 0.7 V

EN pin current VEN = 0 V 1 1 µA

UVLO threshold VCC rising 2.25 2.65 V

UVLO hysteresis 100 mV

(1) Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.(2) Tolerance of external resistors not included in this specification.(3) Dropout is not measured for the TPS79501 and TPS79525 since minimum VIN = 2.7 V.(4) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.

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CurrentSense

ThermalShutdown

UVLO

UVLO

R1

FB

R2

External tothe Device

OvershootDetect

250 kΩ

Quickstart

BandgapReference

1.225 V

IN

VIN

EN

GND

OUT

300Ω

VREF

ILIM SHUTDOWN

CurrentSense

ThermalShutdown

UVLO

UVLO

R1

R2

R2 = 40 kΩ

OvershootDetect

250 kΩ

Quickstart

BandgapReference

1.225 V

IN

VIN

EN

GND

NR

OUT

300Ω

VREF

ILIM SHUTDOWN

TPS795xx


FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION

FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION

Table 1. Terminal FunctionsSOT223 (DCQ) 3x3 SON (DRB)

NAME PIN NO. PIN NO. DESCRIPTION

IN 2 1, 2 Unregulated input to the device

GND 3, 6 6 Regulator ground

EN 1 8 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator intoshutdown mode. EN can be connected to IN if not used.

NR 5 5 Noise-reduction pin for fixed versions only. Connecting an external capacitor to this pin bypassesnoise generated by the internal bandgap, which improves power-supply rejection and reducesoutput noise. (Not available on adjustable versions.)

FB 5 5 Feedback input voltage for the adjustable device. (Not available on fixed voltage versions.)

OUT 4 3, 4 Regulator output.

NC – 7 Not connected




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TYPICAL CHARACTERISTICS

2.98

2.99

3

3.01

3.02

0 0.1 0.2 0.3 0.4 0.5IOUT (mA)

VO

UT (

V)

−40 −25−10 5 20 35 50 65 80 95 110 125

TJ (°C)

IOUT = 1 mA

VIN = 4 VCOUT = 10 µF

IOUT = 0.5 A

260

262

264

266

268

270

272

274

276

I GN

D (

µA)

−40 −25 −10 5 20 35 50 65 80 95 110 125

TJ (°C)

IOUT = 0.5 A

IOUT = 1 mA

VIN = 4 VCOUT = 10 µF

2.97

2.975

2.98

2.985

2.99

2.995

3

3.005

VO

UT (

V)

0

0.1

0.2

0.3

0.4

0.5

100 1 k 10 k 100 kFrequency (Hz)

IOUT = 1 mA

VIN = 5.5 VCOUT = 2.2 µFCNR = 0.1 µF

IOUT = 0.5 A

Out

put S

pect

ral N

oise

Den

sity

−

µV/

Hz

100 1 k 10 k 100 k

Frequency (Hz)

VIN = 5.5 VIOUT = 500 mACOUT= 10 µF

CNR = 0.1 µF

CNR = 0.001 µF

CNR = 0.0047 µF

CNR = 0.01 µF

0

0.5

1

1.5

2

2.5

Out

put

Spe

ctra

l Noi

se D

ensi

ty −

µV

/H

z

0

0.1

0.2

0.3

0.4

0.5

0.6

100 1 k 10 k 100 k

Frequency (Hz)

IOUT = 1 mA

IOUT = 0.5 A

VIN = 5.5 VCOUT = 10 µFCNR = 0.1 µF

Out

put S

pect

ral N

oise

Den

sity

−

µV/

Hz

−40 −25−10 5 20 35 50 65 80 95 110 125

VIN = 2.9 VCOUT = 10 µFIOUT = 500 mA

TJ (°C)

25

50

75

100

125

150

175

0

VD

O (

mV

)

0

10

20

30

40

50

0.001 0.0047 0.01 0.1CNR (µF)

IOUT = 500 mACOUT= 10 µF

BW = 100 Hz to 100 kHz

RM

S −

Roo

t Mea

n S

quar

ed O

utpu

t Noi

se −

µV

RM

S

0

10

20

30

40

50

60

70

80

1 10 100 1 k 10 k 100 k 1 M 10 M

Rip

ple

Rej

ectio

n −

dB

IOUT = 1 mA

VIN = 4 VCOUT = 10 µFCNR = 0.1 µF

IOUT = 500 mA

Frequency (Hz)

TPS795xx


TPS79530 TPS79530 TPS79530OUTPUT VOLTAGE OUTPUT VOLTAGE GROUND CURRENT

vs OUTPUT CURRENT vs JUNCTION TEMPERATURE vs JUNCTION TEMPERATURE

Figure 1. Figure 2. Figure 3.

TPS79530 TPS79530 TPS79530OUTPUT SPECTRAL OUTPUT SPECTRAL OUTPUT SPECTRAL

NOISE DENSITY NOISE DENSITY NOISE DENSITYvs FREQUENCY vs FREQUENCY vs FREQUENCY


TPS79530 TPS79530 TPS79530ROOT MEAN SQUARED DROPOUT VOLTAGE RIPPLE REJECTIONOUTPUT NOISE vs CNR vs JUNCTION TEMPERATURE vs FREQUENCY





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0

10

20

30

40

50

60

70

80

1 10 100 1 k 10 k 100 k 1 M 10 M

Rip

ple

Rej

ectio

n −

dB

VIN = 4 VCOUT = 2.2 µFCNR = 0.01 µF

IOUT = 1 mA

IOUT = 500 mA

Frequency (Hz)

Rip

ple

Rej

ectio

n −

dB

0

10

20

30

40

50

60

70

80

1 10 100 1 k 10 k 100 k 1 M 10 M

IOUT = 500 mA

IOUT = 1 mA

VIN = 4 VCOUT = 2.2 µFCNR = 0.1 µF

Frequency (Hz)

0

10

20

30

40

50

60

70

80

1 10 100 1 k 10 k 100 k 1 M 10 M

Rip

ple

Rej

ectio

n −

dB

VIN = 4 VCOUT = 10 µFCNR = 0.01 µF IOUT = 1 mA

IOUT = 500 mA

Frequency (Hz)

3

4

5

0 50 100 150 200

−10

0

10

20

30

t (µs)

COUT = 10 µF, CNR = 0.01 µF,IOUT = 0.5 A, dv/dt = 1 V/µs

−20V

OU

T (

mV

)V

IN (

V)

0

0.25

0.50

0.75

1

1.25

1.50

1.75

2

2.75

3

0 100 200 300 400 600

Enable

t (µs)

VIN = 4 VCOUT = 10 µFIOUT = 0.5 A

CNR = 0.01 µF

CNR = 0.001 µF

CNR = 0.0047 µF

500

VIN

(V

)

2.25

2.50

2

3

4

0 50 100 150 200

−20

−10

0

10

20

t (µs)

COUT = 10 µF, CNR = 0.01 µF,IOUT = 0.5 A, dv/dt = 1 V/µs

VIN

(V

)V

OU

T (

mV

)

−0.5

0

0.5

0 200 400 600 800 1000

−40

−20

0

40

t (µs)

COUT = 10 µF, CNR = 0.01 µF,VL = 3.8 V, dv/dt = 0.5 A/µs

20

−60

60

V

OU

T (

mV

)I O

UT (

A)

Time (µs)

−0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

VIN

VOUT

VOUT = 2.5 V,RL = 10 Ω

VO

UT (

V)

4000 800 1200 1600 20000

20

40

60

80

100

120

140

160

180

0 100 200 300 400 500

TJ = 125°C

TJ = 25°C

TJ = −40°C

IOUT (mA)

VD

O (

mV

)

TPS795xx


TYPICAL CHARACTERISTICS (continued)

TPS79530 TPS79530 TPS79530RIPPLE REJECTION RIPPLE REJECTION RIPPLE REJECTION

vs FREQUENCY vs FREQUENCY vs FREQUENCY


TPS79530 TPS79518 TPS79530START-UP TIME LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE


TPS79530TPS79530 TPS79525 DROPOUT VOLTAGE

LOAD TRANSIENT RESPONSE POWER UP/POWER DOWN vs OUTPUT CURRENT





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0.01

0.1

1

10

100

0 100 200 300 400 500IOUT (mA)

COUT = 1 µF

ES

R (

)Region of Stability

Region ofInstability

0

50

100

150

200

2.5 3 3.5 4 4.5 5VIN (V)

TJ = 25°C

TJ = −40°C

TJ = 125°C

COUT = 10 µF,CNR = 0.01 µF,IOUT = 50 mA

VD

O (

mV

)

0.01

0.1

1

10

100

1 10 100 1000IOUT (mA)

COUT = 2.2 µF

ES

R (

)

Region of Stability


0.01

0.1

1

10

100

0 100 200 300 400 500

IOUT (A)

COUT = 10 µF

ES

R (

)

Region of Stability


TPS795xx


TYPICAL CHARACTERISTICS (continued)

TPS79530 TPS79530TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY

TPS79501 EQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCEDROPOUT VOLTAGE (ESR) (ESR)vs INPUT VOLTAGE vs OUTPUT CURRENT vs OUTPUT CURRENT


TPS79530TYPICAL REGIONS OF STABILITY

EQUIVALENT SERIES RESISTANCE(ESR)

vs OUTPUT CURRENT

Figure 22.




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APPLICATION INFORMATION

TPS795xx

GNDEN NR

IN OUTVIN VOUT

1 Fm

0.01 Fm

1 Fm

BOARD LAYOUT RECOMMENDATION TO

EXTERNAL CAPACITOR REQUIREMENTS

REGULATOR MOUNTING

TPS795xx


because any leakage current creates an IR dropThe TPS795xx family of low-dropout (LDO) across the internal resistor, thus creating an outputregulators has been optimized for use in error. Therefore, the bypass capacitor must havenoise-sensitive equipment. The device features minimal leakage current. The bypass capacitorextremely low dropout voltages, high PSRR, ultralow should be no more than 0.1-µF in order to ensureoutput noise, low quiescent current (265 µA that it is fully charged during the quickstart timetypically), and an enable input to reduce supply provided by the internal switch shown in thecurrents to less than 1 µA when the regulator is Functional Block Diagram.turned off.

For example, the TPS79530 exhibits only 33 µVRMSA typical application circuit is shown in Figure 23. of output voltage noise using a 0.1-µF ceramicbypass capacitor and a 10-µF ceramic outputcapacitor. Note that the output starts up slower asthe bypass capacitance increases because of the RCtime constant at the bypass pin that is created by theinternal 250-kΩ resistor and external capacitor.

IMPROVE PSRR AND NOISEFigure 23. Typical Application CircuitPERFORMANCE

To improve ac measurements such as PSRR, outputnoise, and transient response, it is recommendedthat the board be designed with separate groundAlthough not required, it is good analog designplanes for VIN and VOUT, with each ground planepractice to place a 0.1µF — 2.2µF capacitor near theconnected only at the ground pin of the device. Ininput of the regulator to counteract reactive inputaddition, the ground connection for the bypasssources. A higher-value input capacitor may becapacitor should connect directly to the ground pin ofnecessary if large, fast-rise-time load transients arethe device.anticipated and the device is located several inches

from the power source.

Like most low-dropout regulators, the TPS795xxThe tab of the SOT223-6 package is electricallyrequires an output capacitor connected betweenconnected to ground. For best thermal performance,OUT and GND to stabilize the internal control loop.the tab of the surface-mount version should beThe minimum recommended capacitor is 1 µF. Any 1soldered directly to a circuit-board copper area.µF or larger ceramic capacitor is suitable.Increasing the copper area improves heat

The internal voltage reference is a key source of dissipation.noise in an LDO regulator. The TPS795xx has an

Solder pad footprint recommendations for theNR pin which is connected to the voltage referencedevices are presented in Application Reportthrough a 250-kΩ internal resistor. The 250-kΩSBFA015, Solder Pad Recommendations forinternal resistor, in conjunction with an externalSurface-Mount Devices, available from the TI webbypass capacitor connected to the NR pin, creates asite (www.ti.com).low-pass filter to reduce the voltage reference noise

and, therefore, the noise at the regulator output. Inorder for the regulator to operate properly, thecurrent flow out of the NR pin must be at a minimum,



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PROGRAMMING THE TPS79501

C1 (3 107) (R1 R2)

(R1 R2) (3)

VOUT VREF 1 R1

R2

(1)

REGULATOR PROTECTION

R1 VOUT

VREF 1 R2

(2)

TPS79501

GND FB

IN OUT

EN

VIN VOUT

R1 C1

R2

1 Fm1 Fm

OUTPUT VOLTAGE

PROGRAMMING GUIDE

1.8 V

3.6 V

14.0 kW

57.9 kW 30.1 kW

30.1 kW 33 pF

15 pF

OUTPUT

VOLTAGE R1 R2 C1

TPS795xx


The approximate value of this capacitor can beADJUSTABLE LDO REGULATOR calculated as Equation 3:

The output voltage of the TPS79501 adjustableregulator is programmed using an external resistordivider as shown in Figure 24. The output voltage is

The suggested value of this capacitor for severalcalculated using Equation 1:resistor ratios is shown in the table within Figure 24.If this capacitor is not used (such as in a unity-gainconfiguration), then the minimum recommendedoutput capacitor is 2.2 µF instead of 1 µF.

where:• VREF = 1.2246 V typ (the internal reference

voltage) The TPS795xx PMOS-pass transistor has a built-inback diode that conducts reverse current when theResistors R1 and R2 should be chosen forinput voltage drops below the output voltage (forapproximately 40-µA divider current. Lower valueexample, during power down). Current is conductedresistors can be used for improved noisefrom the output to the input and is not internallyperformance, but the device wastes more power.limited. If extended reverse voltage operation isHigher values should be avoided, as leakage currentanticipated, external limiting might be appropriate.at FB increases the output voltage error.

The TPS795xx features internal current limiting andThe recommended design procedure is to choosethermal protection. During normal operation, theR2 = 30.1 kΩ to set the divider current at 40 µA,TPS795xx limits output current to approximately 2.8C1 = 15 pF for stability, and then calculate R1 usingA. When current limiting engages, the output voltageEquation 2:scales back linearly until the overcurrent conditionends. While current limiting is designed to preventgross device failure, care should be taken not toexceed the power dissipation ratings of the package.

In order to improve the stability of the adjustable If the temperature of the device exceedsversion, it is suggested that a small compensation approximately 165°C, thermal-protection circuitrycapacitor be placed between OUT and FB. shuts it down. Once the device has cooled down to

below approximately 140°C, regulator operationresumes.

Figure 24. TPS79501 Adjustable LDO Regulator Programming




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THERMAL INFORMATION

TJA

RθJC

TCB

RθCS

TA

C

RθSA

SOT223 Package

CIRCUIT BOARD COPPER AREA

B

A

C

PD max VIN(avg) VOUT(avg) IOUT(avg) V I(avg) IQ

TJ TA PD max RθJC RθCS RθSA (5)

TPS795xx


The amount of heat that an LDO linear regulatorgenerates is directly proportional to the amount ofpower it dissipates during operation. All integratedcircuits have a maximum allowable junctiontemperature (TJmax) above which normal operationis not assured. A system designer must design theoperating environment so that the operating junctiontemperature (TJ) does not exceed the maximumjunction temperature (TJmax). The two mainenvironmental variables that a designer can use toimprove thermal performance are air flow andexternal heatsinks. The purpose of this information isto aid the designer in determining the properoperating environment for a linear regulator that isoperating at a specific power level.

In general, the maximum expected power (PDmax)Figure 25. Thermal Resistancesconsumed by a linear regulator is computed as

shown in Equation 4:Equation 5 summarizes the computation:

(4)

where: The RΘJC is specific to each regulator as determinedby its package, lead frame, and die size provided in• VIN(avg) is the average input voltagethe regulator's data sheet. The RΘSA is a function of• VOUT(avg) is the average output voltagethe type and size of heatsink. For example, black

• IOUT(avg) is the average output current body radiator type heatsinks can have RΘCS values• IQ is the quiescent current ranging from 5°C/W for very large heatsinks to

50°C/W for very small heatsinks. The RΘCS is aFor most TI LDO regulators, the quiescent current isfunction of how the package is attached to theinsignificant compared to the average output current;heatsink. For example, if a thermal compound istherefore, the term VIN(avg) x IQ can be neglected. Theused to attach a heatsink to a SOT223 package,operating junction temperature is computed byRΘCS of 1°C/W is reasonable.adding the ambient temperature (TA) and the

increase in temperature due to the regulator's power Even if no external black body radiator type heatsinkdissipation. The temperature rise is computed by is attached to the package, the board on which themultiplying the maximum expected power dissipation regulator is mounted provides some heatsinkingby the sum of the thermal resistances between the through the pin solder connections. Some packages,junction and the case (RΘJC), the case to heatsink like the DDPAK and SOT223 packages, use a(RΘCS), and the heatsink to ambient (RΘSA). Thermal copper plane underneath the package or the circuitresistances are measures of how effectively an board ground plane for additional heatsinking toobject dissipates heat. Typically, the larger the improve their thermal performance. Computer-aideddevice, the more surface area available for power thermal modeling can be used to compute verydissipation and the lower the object's thermal accurate approximations of an integrated circuit'sresistance. thermal performance in different operating

environments (for example, different types of circuitFigure 25 illustrates these thermal resistances for aboards, different types and sizes of heatsinks,SOT223 package mounted in a JEDEC low-K board.different air flows, etc.). Using these models, thethree thermal resistances can be combined into onethermal resistance between junction and ambient(RΘJA). This RΘJA is valid only for the specificoperating environment used in the computer model.




www.ti.com

TJ TA PD max RθJA (6)

RθJA TJ TA

PD max (7)

PD max (3.3 2.5)V 1A 800mW (8)

RθJA max (125 55)°C800mW 87.5°CW

0

100

120

140

160

180No Air Flow

80

60

40

20

0.1 1 10PCB Copper Area (in 2)

Rθ J

A −

The

rmal

Res

ista

nce

(°C

/W)

SOT223 POWER DISSIPATION

0

1

2

3

6

0 25 50 75 100 150125

TA = 25°C

TA − Ambient T emperature ( °C)

4

5

4 in2 PCB Area

0.5 in2 PCB Area

PD

− M

axim

um P

ower

Dis

sipa

tion

(W)

TPS795xx


Equation 5 simplifies into Equation 6: To illustrate, the TPS79525 in a SOT223 packagewas chosen. For this example, the average inputvoltage is 3.3 V, the output voltage is 2.5 V, the

Rearranging Equation 6 gives Equation 7: average output current is 1 A, the ambienttemperature 55°C, no air flow is present, and theoperating environment is the same as documentedbelow. Neglecting the quiescent current, themaximum average power is Equation 8:Using Equation 6 and the computer model generated

curves shown in Figure 26, a designer can quicklycompute the required heatsink thermal

Substituting TJmax for TJ into Equation 4 givesresistance/board area for a given ambientEquation 9:temperature, power dissipation, and operating

environment.(9)

From Figure 26, RθJA vs PCB Copper Area, theground plane needs to be 0.55 in2 for the part todissipate 800 mW. The operating environment usedto construct Figure 26 consisted of a board with 1 oz.copper planes. The package is soldered to a 1 oz.copper pad on the top of the board. The pad is tiedthrough thermal vias to the 1 oz. ground plane.

From the data in Figure 26 and rearranging equation6, the maximum power dissipation for a differentground plane area and a specific ambienttemperature can be computed, as shown inFigure 27.

Figure 26. SOT223 Thermal Resistance vs PCBCopper Area

The SOT223 package provides an effective meansof managing power dissipation in surface-mountapplications. The SOT223 package dimensions areprovided in the Mechanical Data section at the endof the data sheet. The addition of a copper planedirectly underneath the SOT223 package enhancesthe thermal performance of the package.

Figure 27. SOT223 Maximum Power Dissipationvs Ambient Temperature




PACKAGING INFORMATION

Orderable Device Status (1) PackageType

PackageDrawing

Pins PackageQty

Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TPS79501DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TPS79501DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &no Sb/Br)


TPS79501DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &no Sb/Br)


TPS79501DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &no Sb/Br)


TPS79501DRBR ACTIVE SON DRB 8 3000 Green (RoHS &no Sb/Br)


TPS79501DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS &no Sb/Br)


TPS79501DRBT ACTIVE SON DRB 8 250 Green (RoHS &no Sb/Br)


TPS79501DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS &no Sb/Br)




































PACKAGE OPTION ADDENDUM

www.ti.com 8-Oct-2007

Addendum-Page 1

Orderable Device Status (1) PackageType

PackageDrawing

Pins PackageQty

Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)







(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 8-Oct-2007

Addendum-Page 2

http://www.ti.com/productcontent

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1(mm)

W(mm)

Pin1Quadrant

TPS79501DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3

TPS79501DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS79501DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS79516DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3

TPS79518DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3

TPS79525DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3

TPS79530DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3

TPS79533DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Apr-2009

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS79501DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0

TPS79501DRBR SON DRB 8 3000 346.0 346.0 29.0

TPS79501DRBT SON DRB 8 250 190.5 212.7 31.8

TPS79516DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0

TPS79518DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0

TPS79525DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0

TPS79530DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0

TPS79533DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Apr-2009

Pack Materials-Page 2

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.

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