david lucas clarendon laboratory & balliol college oxford...
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Quantum logic with trapped-ion qubits
David Lucas
Clarendon Laboratory & Balliol College
Oxford University
www.physics.ox.ac.uk/users/iontrap
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A quantum bit (“qubit”)
• single 40Ca+ ion
• confined in an
ion trap
• laser-cooled
to <0.001K
40Ca+ ground state:
1s2 2s2 2p6 3s2 3p6 4s1
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A quantum bit (“qubit”)
• single 40Ca+ ion
• confined in an
ion trap
• laser-cooled
to <0.001K
40Ca+ ground state:
1s2 2s2 2p6 3s2 3p6 4s1
Qubit states
|0> = |↑>
|1> = |↓>
4s1 S1/2
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A quantum bit (“qubit”)
• single 40Ca+ ion
• confined in an
ion trap
• laser-cooled
to <0.001K
40Ca+ ground state:
1s2 2s2 2p6 3s2 3p6 4s1
Qubit states
|0> = |↑>
|1> = |↓>
4s1 S1/2 “Blu-ray”
DVD laser
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ion-electrode distance = 1.2 mm
motional frequencies ~ 1 MHz
10mm
7 mm
10mm
Ion trap “quantum abacus”
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Real atoms!
~2
50m
m
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Quantum logic gate
“Controlled-NOT” gate:
flip ion B between states |↑> ↔ |↓>
if and only if ion A is in state |↑>
|↑>
|↓> ion
A s
tate
s
w0
A B
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Quantum logic gate
“Controlled-NOT” gate:
flip ion B between states |↑> ↔ |↓>
if and only if ion A is in state |↑>
|↑>
|↓> 0 1
vibrational quanta
wz
|↑>
|↓>
0 1 vibrational quanta
w0
ion
A s
tate
s
ion
B s
tate
s
A B
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Quantum logic gate
“Controlled-NOT” gate:
flip ion B between states |↑> ↔ |↓>
if and only if ion A is in state |↑>
|↑>
|↓> 0 1
vibrational quanta
wz
|↑>
|↓>
0 1 vibrational quanta
w0
ion
A s
tate
s
ion
B s
tate
s
STEP (i): w0-wz
A B
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Quantum logic gate
“Controlled-NOT” gate:
flip ion B between states |↑> ↔ |↓>
if and only if ion A is in state |↑>
|↑>
|↓> 0 1
vibrational quanta
wz
|↑>
|↓>
0 1 vibrational quanta
w0
ion
A s
tate
s
ion
B s
tate
s
STEP (i): w0-wz STEP (ii): w0
A B
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BBC microcomputer 1984 32 kbytes RAM 2 MHz clock speed
1985 Idea of quantum computer (Deutsch, Oxford; Feynman, Cal.Tech.)
A bit of history
1995 Quantum error-correction invented (Shor, IBM; Steane, Oxford) 1998 First quantum logic gate demonstrated (Wineland group, NIST)
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NIST
Innsbruck
Oxford
NIST NIST
NIST
History of 2-qubit logic gates
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NIST
Innsbruck
Oxford
UCSB
UCSB
Yale
IBM
NIST NIST
NIST
History of 2-qubit logic gates
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silicon
History of 2-qubit logic gates
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log
10(n
o.o
pera
tions)
Overhead and noise threshold of fault-tolerant quantum error correction,
A.M.Steane, PRA 2003
The challenge: quantum error correction
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superconducting circuits
ion traps
impurity spins in solids
(e.g. NV centres)
electronic semiconductor qubits
linear optics
blue: usually cryogenic red: usually room temp.
Example qubit hardware platforms
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log
10
(no.o
pera
tions)
superconducting circuits (cryo.) semiconductor qubits (cryo.) trapped ions (room temp.)
Some examples of state-of-the-art
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log
10
(no.o
pera
tions)
superconducting circuits (cryo.) semiconductor qubits (cryo.) trapped ions (room temp.)
1-qubit gate
initialisation, readout
memory
1-qubit gate
initialisation
1-qubit gate
Some examples of state-of-the-art
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log
10
(no.o
pera
tions)
superconducting circuits (cryo.) semiconductor qubits (cryo.) trapped ions (room temp.)
1-qubit gate
2-qubit gate
initialisation, readout
memory
5 q
ub
its,
arb
. co
ntr
ol
20
qu
bits,
limited c
ontr
ol 2-qubit gate
(in 5-qubit device)
1-qubit gate
initialisation
1-qubit gate
Some examples of state-of-the-art
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laser subsystem
NEW: rackmount laser system OLD: “traditional” optical table laser setup
AOM subsystem
Meanwhile, in the basement…
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Node #1 “Alice” Node #2 “Bob”
HOA-2 surface trap
(Sandia National Labs, USA)
Optically-linked ion traps
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