dct700 ph0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1

DCT.SCH. Top level connections

6

DCT700 Phase 0 Main Board Schematic

POR.SCH Power On Reset

Ref

2

APVD

DIGITAL.SCH Hierarchical Grouping

3

QUAKE_RP_DIGITAL.SCH QUAKE_RP Digital I/O

AFE.SCH. Analog front end.

PLATFORM_FLASH & SRAM.SCH

Rev. .00

100

THIS DOCUMENT CONTAINS PROPRIETARY DATA AND

IS INTENDED ONLY TO CONVEY INFORMATION TO

CUSTOMERS, PROSPRECTIVE CUSMERS, AND

VENDORS. IT SHALL NOT BE COPIED, REPRODUCED,

COMMUNICATED TO OTHERS, OR USED AS A BASIS

FOR THE MANUFACTURE OR SALE OF APPARATUS

WITHOUT THE WRITTEN PERMISSION OF GENERAL

INSTRUMENT CORPORATION.

REVISION

14

2

2. Each page in the schematics is assigned a set of reference designators (Ref)

11

INCORP

200

DDR_SDRAM.SCH

1100

Revision History

A

SECURITY.SCH MC1.7, Battery, and TVPC

700/800

Initial Proto Rev.

1

NUMBER

.00

900

QUAKE_RP_ANALOG.SCH 7114 Analog I/O

REVISION

.00

.00

DCT700 Phase 0 Title Sheet

B

SheetSchematic

8

ECO

1

.00

.00

.002

1. These schematics are grouped heirachically by function

A

Notes :

D

.00

.00

Rev. Description

PCB Requirements

12

Place all terminating resistors as close to source as possible. The series terminating resistors willhave a value of 0, 33, or 51 Ohms.

C

DESCRIPTION

.00

This reference is the starting designator for all parts on the page

MODIFICATION RECORDS

328-039-001

4 1

1

13

9

4

.00

C

400

7

Table of Contents

VIDEO_AUDIO.SCH Baseband / Remod Output

200/400

300

.00

4

3

D

1

1

10 .00

B

5

.00

REV

.00

3

ANALOG.SCH Hierarchical Analog Grouping

TUNER_UPSTREAM.SCH Tuner, Upstream Amp & Diplexer 500/600

PWR.SCH Power Distribution

REV.1DMR SD_284 , DMR SD_286 , DMR SD_287, DMR SD_288, DMR SD_289, DMR SD_290, DMR SD_291, DMR SD_292, DMRSD_293, DMR SD_294, DMR BCST_1, DMR BCST_2, DMR SD_295, DMR SD_297

REV.2 DMR SD_299, DMR SD_301, DMR SD_303, DMR SD_304

REV.3 DMR SD_307-1, DMR SD_311-1, DMR SD_309, DMR SD_312, DMR BCST_3, DMR BCST_4

10V

-65%

YES

YES<1%

10V

YES

NO

-2%-2%

Applied

Voltage

-2%

YES

10V

Y5V 0805

-3%

X5R 1206

X5R 1206

1.2V

NO

-10%

YES

10VX6S 1206

X5R 1206

-10%X7R 1206

-15%

5V

NO

Y5V 0805

Y5V 0805

For power supply bypass applications (not AC signals).

10VX6S 1206

YES

X5R 1206

-15%

YES

3.3VX7R 1206

6.3VX6S 0805

YES

-28%

Y5V 0805

X7R 1206

6.3VX6S 0805

6.3V YES

NO

-2%

10V

YES

Cap change at

applied

voltage.

YES

6.3V

Voltage

Rating

Acceptable

for use?

X7R 1206-20%

2.5V

10V

6.3V

10V

-85%

Dielectric

Material &

Size

Acceptable Dielectric Material for 10 uF Multilayer Chip Capacitors.

10V

-75%

YES

6.3V <1%10V

REV.4DMR SD_317,DS_321,BCST_021,SD_326,SD_330,SD_332,SD_335,SD_341,SD_342,BCST_022

REV.A Release for mass production(REV.A=REV.4)

AC031282

Rele

ase

for m

ass

prod

uctio

n of

Phas

e 1

Matt

Chiang

9-24-03'

Raph Chang

9-24-03'

A

A

SCHEMATIC,MAIN,DCT700 P0

Atlanta, Georgia, U.S.A. Taipei, Taiwan R.O.C.

1 14Friday, September 26, 2003

864684-049

Title

Document Number Rev

Date: Sheet of

File Name

DCT_2

Sheet_02

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

YELLOW - POWER

RED - MESSAGE

D4 R15 R16 R17 R18

MIM-5383H4

SFH5110-38

INSTALL INSTALL

INSTALL

DNI

INSTALLDNI

DNI

DNI

See optionTable 3 Table 3

A

DCT.SCH

Atlanta, Georgia, U.S.A. Taipei, Taiwan R.O.C.


<Variant Name>

864684-049

Title

Document Number Rev

Date: Sheet of

File Name

POWER

Sheet_05

VDC_IN

ANALOG

Sheet_04

LINE_OUT_RIGHT

LINE_OUT_LEFT

COMP_OUT

REMOD_OUT

CH3/4_SEL

DIGITAL

Sheet_03

WRPROT_1

WRPROT_3

CH3/4_SEL

IR_IN

MANF_RXD

MANF_TXD

MSG_LED

PWR_LED

HARD_RESETB

MSG_LED

MSG_LEDB

PWR_LED

PWR_LEDB

DIAG_TXD

DIAG_RXD

MANF_RXD

MANF_TXD

HARD_RESETB

COMP_OUT

LINE_OUT_LEFT

LINE_OUT_RIGHT CH3/4_SEL

WRPROT_GND

IR_IN

WRPROT_1

WRPROT_3

D

A

D

D

D

+3.3V

+5V

D

D

D

D

D

D

D

+5V

+3.3V

D

R12

330_s

J4conn_f_female_007185243-007-99

1

32

TP4TESTPIN

TP10

R18 0_s

Q42sc2712

1

32

TP3TESTPIN

TP5TESTPIN

R63.3K_s

S1QUAKE_SHIELD

123456

GN

DG

ND

GN

DG

ND

GN

DG

ND

R11

4.7K_s

D4gp1um281yk

21

3

4

5

VCC

(GN

D)

VOU

T

GND(VCC)

MTG1

MTG2

TP6TESTPIN

D2hlmp_1401

21

R17 0_s

S

T

J6

hsp_241v1y

1

32

D3led

21

R15 0_s

TP7TESTPIN

TP1TESTPIN

R3100_s

TP9

Q1

2sc27121

32

Q3

2sc27121

32

TP2TESTPIN

R710K_s

R16

0_s

R10

330_s

TP8

J3

conn_power_jack1

123

C10.1U_s

R81K_s

R51K_s

2T

1TS

J5

hsp_242v2

23

1

Q2

2sc27121

32

R23.3K_s

R13

4.7K_s

R14

4.7K_s

D1mmbd4148

13

J1

header_3_pins

123R4

1K_s

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

A

DIGITAL.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.


C 864684-049

Title

Document Number Rev

Date: Sheet of

File NameSize

POR

Sheet_06

POR_IRQBPOR_RESETB

HARD_RESETB

EJTAG_RESETB

DDR_SDRAM_1

Sheet_09

SD_DATA_[15:0]

SD_ADDR_[12:0]

SD_UDMSD_LDM

SD_UDQS_1SD_LDQS_0

SD_WEBSD_RASBSD_CASB

SD_CSB_0

SD_CLKSD_CLKB

SD_BA_0SD_BA_1

SD_CLKE

SECURITY_1

Sheet_10

PKT_DATAPKT_SYNC

PKT_CLK

POR_RAM_ENB

SYS_RESETB

MC_SPI_CSB

WRPROT_1WRPROT_3

INFO_DATAINFO_SYNC

INFO_CLK

SRAM_VBATTMC_IRQB

SPI_MISOSPI_MOSI

MC_CLK27MC_CLK40

SPI_CLK

POR_RESETB

PLATFORM_FLASH & SRAM_1

Sheet_08

EBI_DATA_[15:0]EBI_ADDR_[24:0]

EBI_RDB

SRAM_VBATTPOR_RAM_ENB

SYS_RESETB

FLASH1_CSBROM_CSB

SRAMLB_CSBSRAMUB_CSB

EBI_R/WB

SEL_FLASH1/ROMB

QUAKE_RP_ DIGITAL_1

Sheet_07

EBI_DATA_[15:0]EBI_ADDR_[24:0]

EBI_RDB

SD_ADDR_[12:0]

SD_DATA_[15:0]

SD_UDMSD_LDMSD_UDQS_1SD_LDQS_0SD_WEBSD_RASBSD_CASB

SD_CSB_0

SD_CLKSD_CLKB

SPI_MOSI

SPI_CLKMC_SPI_CSB

SPI_MISO

EJTAG_RESETB

POR_RESETBPOR_IRQB

ROM_CSBFLASH1_CSB

SRAMLB_CSBSRAMUB_CSB

MANF_RXDMANF_TXD

INFO_CLKINFO_DATAINFO_SYNC

EBI_R/WB

SD_BA_0SD_BA_1

MC_IRQB

IR_IN

PKT_CLKPKT_DATAPKT_SYNC

MC_CLK27MC_CLK40

SYS_RESETBCH3/4_SEL

MSG_LEDPWR_LED

SD_CLKE

SEL_FLASH1/ROMB

POR_RESETB

SYS_RESETB

SRAM_VBATTPOR_RAM_ENB

WRPROT_3WRPROT_1

HARD_RESETB

SYS_RESETB

SD_CSB_0

EBI_ADDR_[24:0]

SPI_MISO

SPI_CLK

SD_CASB

SD_LDM

SD_BA_0 SRAMUB_CSB

SD_DATA_[15:0]

EBI_RDB

IR_IN

SPI_MOSI

CH3/4_SEL

EBI_R/WB

INFO_SYNC

ROM_CSB

SD_CLK

PWR_LED

SYS_RESETB

MC_IRQB

SD_CLKB

EBI_DATA_[15:0]

SD_RASB

SD_ADDR_[12:0]

MC_SPI_CSB

SD_CLKEFLASH1_CSB

POR_IRQB

INFO_CLK

SRAMLB_CSB

SD_UDM

MC_CLK40MC_CLK27

POR_RESETB

MSG_LED

SD_BA_1

INFO_DATA

EJTAG_RESETB

SD_WEBSD_LDQS_0SD_UDQS_1

SEL_FLASH1/ROMB

WRPROT_3

IR_IN

WRPROT_1

CH3/4_SEL

PWR_LEDMSG_LED

MANF_RXDMANF_TXD

HARD_RESETB

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

A

ANALOG.SCH



C 864684-049

Title

Document Number Rev

Date: Sheet of

File NameSize

TUNER_UPSTREAM.SCH

Sheet_14

TX_DAC+TX_DAC-

TX_OEN

US_CTL_DATAUS_CTL_CLKUS_CTL_CSB

TUNER_SDATUNER_SCLK

QAM_IF-

OOB_TAPQAM_IF+

QAM_AGCT

QUAKE_RP_ANALOG

Sheet_11

DIG_COMPOSITE

AUDIO_LEFT_POSAUDIO_LEFT_NEG

AUDIO_RIGHT_POSAUDIO_RIGHT_NEG

OOB_AGC

OOB_VCO_POSOOB_VCO_NEG

IB_IF_NEGIB_IF_POS

OOB_IF_NEGOOB_IF_POS

QAM_AGCI

TX_DAC+

TX_OEN

TX_DAC-

US_CTL_DATAUS_CTL_CLKUS_CTL_CSB

TUNER_SDATUNER_SCLK

QAM_AGCT

AFE

Sheet_13

OOB_AGC

QAM_AGCI

IB_IF_POSIB_IF_NEG

OOB_IF_NEG

OOB_VCO_POSOOB_VCO_NEG

OOB_IF_POS

QAM_IF-

OOB_TAP

QAM_IF+

VIDEO_AUDIO.SCH

Sheet_12

DIG_COMPOSITE

COMP_OUT

AUDIO_RIGHT_POS

LINE_OUT_RIGHT

AUDIO_RIGHT_NEG

REMOD_OUTAUDIO_LEFT_NEG

LINE_OUT_LEFTAUDIO_LEFT_POS

CH3/4_SEL

OOB_TAP

REMOD_OUT

COMP_OUT

CH3/4_SEL

LINE_OUT_LEFTLINE_OUT_RIGHT

QAM_IF+

AUDIO_LEFT_POS

OOB_IF_NEG

DIG_COMPOSITE

IB_IF_POS

AUDIO_RIGHT_POS

AUDIO_LEFT_NEG

AUDIO_RIGHT_NEG

OOB_AGC

OOB_IF_POS

OOB_VCO_POS

IB_IF_NEG

OOB_VCO_NEG

TX_DAC-TX_DAC+

US_CTL_CSB

TX_OEN

QAM_IF-

OOB_TAP

TUNER_SDA

US_CTL_DATAUS_CTL_CLK

TUNER_SCLK

QAM_AGCI

QAM_AGCT

COMP_OUT

LINE_OUT_RIGHTLINE_OUT_LEFT

REMOD_OUT

CH3/4_SEL

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

112004-014

+2.5V Voltage Regulator (50 mA nominal)

-5V Charge Pump (20 mA max)

488524-001

+3.4V LDO Voltage Regulator

506626-001

138194-000

Reverse voltageprotection

138194-000

+1.25V DC-DC Converter

1%

Low ESR

502130-001

Overcurrentprotection

Low ESR

Input DC Power Filter andProtection

501238-001

Low ESR

503458-001

Collector tab of 2SD2118 must be heat sinked tocopper on PCB.

VOUT = VFB*(1+R1/R2)VFB = 1.242V nominalVOUT = 1.242V*(1 +1K/47K) = 1.268V

VOUT = VFB*(1+R1/R2)VFB = 2.5V nominalVOUT = 2.5V*(1 +1K/2.8K) = 3.393V

EMI Filter

1%

SurgeProtection

See table page 1.6.3V X5R 1206467639-001

See table 1

467639-0016.3V X5R 1206See table page 1.

467639-0016.3V X5R 1206See table page 1.

See table 1 See table 1

506626-001

1%

1%

See table 1

+5V DC-DC Converter

138194-000

Low ESR Low ESR

501238-001

See table 1

VOUT = VFB*(1+R1/R2)VFB = 1.242V nominalVOUT = 1.242V*(1 +10K/3.24K) = 5.075V

C113

C101, C102

C105, C106

United Chemi-Con

KMF25VB471M10X16 507629-001 0.19 ohms

KZE16VB471M10X12 496616-001 0.053 ohms C121 = 1000pF

KZE25VB471M10X16 496616-002 0.038 ohmsKMF25VB471M10X16 507629-001 0.19 ohms

United Chemi-ConKMF16VB471M10X12 507630-001 0.25 ohms

KZE series Do not use. Do not use.United Chemi-ConKMF16VB471M10X12 507630-001 0.25 ohms C121 = 1000pFKMF25VB471M10X16 507629-001 0.19 ohms C121 = 1000pF

Reference

Designator

Vendor and PN Motorola MCN ESR max. at 20 deg C

and 100 kHz

NotesTable 1

A

PWR.SCH



C 864684-049

Title

Document Number Rev

Date: Sheet of

File NameSize

D

+5V

+5V

D

D

+12V_UNREG

D

D

D

DD

D

+12V_UNREG

+5V+12V_UNREG

D

+1.2V

+12V_UNREG

D

-5V

+2.5V+2.5VREF

+3.3V

+3.3V

D

D

D

+12V_UNREG

+5V

D

D

+12V_UNREG

D

U103F74vhc14dt

13 12

F100fuse2a

D100mbrs340

21

C1031000P_s

C104100P_s

R1101K_s

C109

10U_c C108

10U_c

R106100K_s

R10517.4K_s1%

C1111000P_s

R11420_s

C110100P_s

Q1022SD2118

1

43

C1180.1U_s

12

D1041smb20a

21

L10122uh_1_9a

+C105470uf_21

12

R1112.8K_s

U103D74vhc14dt

9 8

R1001K_s

Q101FDC640P

123 4

56DRAIN

DRAINGATE SOURCE

DRAINDRAIN

R1081K_s

C1211000P_s

Q1042sa1162

1

23

C1170.1U_s

12

C116

10U_c

+C106470uf_21

12

R10310K_s

U103B74vhc14dt

3 4

+C115

100uf_07

12

+ C113470uf_22

12

Q103mmbt2222a

1

32

R10920_s

R112100_s

R1130_s

C1071000P_s

C122180P_s

L10232uh_2a

D102mbr0520lt

21

U100LM3485

495633-001-26

1234 5

678ISENSE

GNDNCFB ADJ

PWRGNDPGATE

VIN

R10147K_s

D105mbrs340

2 1

U103E74vhc14dt

11 10

D103mbr0520lt

21

+ C102

470uf_21

12

C1140.1U_s

R1043.24K_s

U103C74vhc14dt

5 6

C100100P_s

U101LM3485

495633-001-26

1234 5

678ISENSE

GNDNCFB ADJ

PWRGNDPGATE

VIN

D101mbrs340

21

R1071K_s

+C101470uf_21

12

L10022uh_1_9a

C1120.1U_s

R10217.4K_s1%

U104TL431CD

61

832

7

C1201000P_s

Q100FDC640P

123 4

56DRAIN

DRAINGATE SOURCE

DRAINDRAIN

U103A74vhc14dt14

71 2

VDC_IN

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

128008-010

1%

3.3V Voltage Monitor

1.2V Voltage Monitor

128008-010

Power UP threshold = 1.125 V nom.Power DOWN threshold = 1.113 Vnom.

Power UP threshold = 8.536V nom.Power DOWN threshold = 6.889V nom.

Power UP threshold = 2.989 V nom.Power DOWN threshold = 2.894 Vnom.

128008-010

1%

1%

DC Input Power Supply Voltage Monitor

128008-010

A

POR.SCH



C 864684-049

Title

Document Number Rev

Date: Sheet of

File NameSize

PG1

+2.5VREF

+2.5VREF

PG2

+2.5VREF

+2.5VREF

+12V_UNREG

+12V_UNREG

D

+12V_UNREG

+3.3V

+1.2V

D

D

+3.3VD

+3.3V

+2.5VREF

D

+3.3V

D

+12V_UNREG

-

+

U150CLM339AD

9

814

312

R16120K_s

R1658.06K_s1%

R153100K_s

-

+

U150DLM339AD

11

1013

312

R15447.5K_s

-

+

U150BLM339AD

5

42

312

C1504700P_s

12

D151bat54alt1

3

2

1

R1573.3K_s

-

+

U150ALM339AD

7

61

312

C1510.1U_s

R162100K_s

R1593.3K_s

U151TL431CD 6

1

832

7 R1513.3K_s

R16410K_s1%

R160

3.3K_s

R15610K_s

R158100K_s

R15520K_s

D150bat54alt1

3

2

1

R15210K_sR166

3.3K_s

R1631K_s

R15010K_s

HARD_RESETB

EJTAG_RESETB

POR_IRQB

POR_RESETB

EBI_CSB_6

EBI_CSB_8EBI_CSB_7

27MHz

QUAKE has internal PU

for EXTI[4:0]. QUAKE has internal

PD for

GPIO[23:00].

LK_SEL[3:0] are outputs.

LK_SEL4 has internal PD.

QUAKE has internal

PD for LK_LD[7:0]

QUAKE has internal

PD for LK_KD[3:0]


for SCI_RXD[3:0]


for USB inputs.

QUAKE has internal PD

for GPT_INCAP[2:0],

GPT_PWMA & GPT_PWMB.


for SPI_PCS[3:0].

QUAKE has internal PD/PU for TDI,

TCK, TMS & TRST_N. TDO is output

Ground guard these components and all associated traces, including traces to Quake and

connect ground guard to digital ground. Place ground vias every 0.25 inches.

Ground guard these components and all associated traces, including

traces to QUAKE and connect ground guard to analog ground. Place

ground vias every 0.25 inches.

35.84 MHz XO27 MHz VCXO

DNI

BER Test Header

GPIO_11 is dedicated for F/W to determine the number of DRAM chips installed

on a QUAKE platform.

Default is 1 chip = pull down, for 2 chips a pullup is required

A

QUAKE_DIGITAL.SCH



C 864684-049

Title

Document Number Rev

Date: Sheet of

File NameSize

EJTAG_TDO

MC_CLK27

EBI_DATA_14

EBI_DATA_8

EBI_DATA_5

EJTAG_TDI

EBI_ADDR_22

EJTAG_TMS

SD_DATA_2

EBI_ADDR_23

EBI_ADDR_9

EBI_DATA_9

EBI_DATA_2

SD_DATA_12

SD_ADDR_11

EBI_ADDR_1

EBI_DATA_6

SD_DATA_15

EBI_ADDR_21

EBI_ADDR_15

EBI_ADDR_10

EBI_DATA_12

CLK27_O

SD_ADDR_10

SD_ADDR_3

EBI_ADDR_14

EBI_DATA_4

EBI_DATA_1

SD_DATA_11

SD_ADDR_8

EBI_ADDR_18

EBI_ADDR_2

EBI_DATA_13

SD_ADDR_12

SD_DATA_8SD_DATA_7SD_DATA_6

EBI_ADDR_7

CLK27_OUT

SD_ADDR_9

EBI_ADDR_24

EBI_ADDR_17

EBI_ADDR_8

EBI_ADDR_4

EBI_ADDR_0

SD_DATA_5

SD_DATA_1SD_DATA_0

EBI_DATA_7

CLK27_I

SD_ADDR_7

EJTAG_TCK

EBI_DATA_15

SD_DATA_14

SD_DATA_3

SD_ADDR_2

SD_ADDR_0

EBI_DATA_10

CLK27_PCR_DAC

SD_ADDR_6

EBI_ADDR_5

SD_DATA_9

SD_ADDR_4

EBI_ADDR_16

EBI_ADDR_6

SD_DATA_10

SD_ADDR_1

EBI_ADDR_13

EBI_DATA_11

EBI_DATA_0

SD_ADDR_5

EBI_ADDR_11

EBI_ADDR_3

EBI_DATA_3

SD_DATA_13

SD_DATA_4

EBI_ADDR_12

EBI_ADDR_20EBI_ADDR_19

CLK27_PCR_DAC

PHY_XTALOPHY_XTALI

EJTAG_TRSTB

SEL_FLASH1/ROMB

PHY_XTALOPHY_XTALI

CLK27_I

CLK27_O

INFO_CLK

INFO_DATA

MC_CLK40

INFO_SYNC

INFO_SYNCINFO_CLK

INFO_DATA

MC_CLK40CLK40_OUT

D

+3.3V

D

+3.3V

DD

D

D

DD

A

A

A

+3.3V

D

R221100_s

C22247P_s

12

J201

header_6_pins

123456

R220100K_s

TP203

R202 33_s

Y21035_84mhz_sm

R2274.7K_s

L2102.7uH_c_1210

R2254.7K_s

C2231000P_s

12

R204 33_s

R201 33_s

D2201sv322

21

TP206

C21068P_s

R21047K_s

Y22027mhz

1 2

C2210.01U_s

12

TP207

R203 33_s

R2244.7K_s

C21215P_s

RP200

33_4_s

1234 5

678

C22022P_s

12

R223100K_s

TP204

R2264.7K_s

R200 33_s

C2250.1U_s

12

TP230

TP205

C21115P_s

R22251_s

J200header_7pins_2rows

2468

10

135791113

1214

C2240.1U_s

12

QUAKE Digital I/O

U200D Quake

T4U1

U3

B13A13C11B11

D13C13A12D11

AB2AB4AC2AD1AE1AE2AD3AF3AC4AE3AF2AF1AD2AC3AC1AB3

AB1AA4AA3AA2AA1Y4

W4W5

C15

AE21

AC20

B10

D15

AF21

AD20

A10

AD23D10

AD15

AE20AF20AD19AE19AC18

AF18AC17AD17AE17AF17AF16AE16AD16

AF19AD18AE18AC19

W1W2W3

L4L3L2

A15

A19

C19

B15

B19AF23AE23

V2

V4V3

D23C25

AC16A11

D12

B12

AD26AD4

M1R2U5T5R5P5

V25V24V23

W26W25W24W23

AC21AC15

C10V26U23B22R3

A22D21

Y1Y3Y2

M2M3M4

R1P4P3P2P1N4N3N2N1

AD21

U2AC23

AF4

AE15

C26A26B24B25

AE4

C12

E12

AF24AE24

AA25

Y25Y24

AA24

AA26

Y26

Y23

AA22

Y22

AC26AB23

AC25AC24

AB26

AB24

AA23

AB25

B21D20A21

C21E20

SPI_MISOSPI_MOSI

SPI_SCK

USB_A_DATAPUSB_A_DATANUSB_A_PWR_ON_NUSB_A_PWR_ERR_N

USB_B_DATAPUSB_B_DATANUSB_B_PWR_ON_NUSB_B_PWR_ERR_N

ATA_DATA00ATA_DATA01ATA_DATA02ATA_DATA03ATA_DATA04ATA_DATA05ATA_DATA06ATA_DATA07ATA_DATA08ATA_DATA09ATA_DATA10ATA_DATA11ATA_DATA12ATA_DATA13ATA_DATA14ATA_DATA15

ATA_DRQATA_IOWATA_IOR

ATA_IOCHRDYATA_DACK

ATA_INTRQ

ATA_CS0ATA_CS1

SCI_RXD0

SCI_RXD1

SCI_RXD2

SCI_RXD3

SCI_TXD0

SCI_TXD1

SCI_TXD2

SCI_TXD3

GPT_INCAP0GPT_INCAP1GPT_INCAP2

LK_SEL0LK_SEL1LK_SEL2LK_SEL3LK_SEL4 (656_IN_CLK)

LK_LD0 (656IN_D0)LK_LD1 (656IN_D1)LK_LD2 (656IN_D2)LK_LD3 (656IN_D3)LK_LD4 (656IN_D4)LK_LD5 (656IN_D5)LK_LD6 (656IN_D6)LK_LD7 (656IN_D7)

LK_KD0LK_KD1LK_KD2LK_KD3

MCI_PKTCLKMCI_PKTSYNMCI_PKTDAT

MENC_PKTCLKMENC_PKTSYNMENC_PKTDAT

HSI_DATA0

HSI_PKTDAT

HSI_PKTCLK

HSI_DATA1

HSI_PKTSYNI2C_SCLI2C_SDA

MCO_PKTCLK

MCO_PKTDATMCO_PKTSYN

DO_POD_CLK (CRX)DO_POD_DATA (DRX)

IR_INIR_OUT

SFTM_PWRCLKP

SFTM_DIB_DATAP

GPIO00GPIO01GPIO02GPIO03GPIO04GPIO05GPIO06GPIO07GPIO08GPIO09GPIO10GPIO11GPIO12GPIO13GPIO14GPIO15GPIO16GPIO17GPIO18GPIO19GPIO20GPIO21GPIO22GPIO23

ATA_DA0ATA_DA1ATA_DA2

AUD_I2SO_DATAAUD_I2SO_LRCLK

AUD_I2SO_CLK

CCIR656_B00CCIR656_B01CCIR656_B02CCIR656_B03CCIR656_B04CCIR656_B05CCIR656_B06CCIR656_B07

CCIR656_BCLK

GPT_PWMA

SPI_PCS0SPI_PCS1SPI_PCS2

GPT_PWMB

UO_POD_Q (QTX)UO_POD_I (ITX)

UO_POD_C (CTX)UO_POD_E (ETX)

SPI_PCS3

SFTM_DIB_DATAN

SFTM_PWRCLKN

DMX_DBG_TXDDMX_DBG_RXD

CCIR656_A06

CCIR656_A01CCIR656_A02

CCIR656_A07

CCIR656_A05

CCIR656_A00

CCIR656_A03

CCIR656_A08

CCIR656_A04



CCIR656_A09

CCIR656_A11

CCIR656_ACLK

CCIR656_A10

AUD_COMP_CLKAUD_COMP_LRCLK

AUD_COMP_DATA

AUD_MCLKAUD_REQ_N

R205 33_s

QUAKE Digital CP

U200B Quake

A9

C4C3C2C1D4D3D2D1E4E3A8B8A7B7C7A6B6C6A5B5A4B4A3B9B3D9

A2A1C5B2B1K1K2H5D8

E1E2D6

T2

R4

T3K3K4J5C9

D5

E5F5

C8G5D7

T1

AD8AE8

AF6AE6AD6AF5AE5AC5AD5AC6AB7AC7AD7AB8

AF7AE7

AE14AF14AE13AF13AF12AE12AF11AE11AC11AD11AC12AD12AD13AC13AD14AC14

AF8AE9AF9

AD10AB10AF10AC10

AD25AE25AF26AD24AE26

AF15AC22

L26K22

A20B20D19

U4

V1

AC8

F4F3F2F1G4G3G2G1H4H3H2H1J4J3J2J1

AE10AB11

L1

AB9AC9AD9

AF25

CP_BOOTSEL_CS0_N

CP_ADDR00CP_ADDR01CP_ADDR02CP_ADDR03CP_ADDR04CP_ADDR05CP_ADDR06CP_ADDR07CP_ADDR08CP_ADDR09CP_ADDR10CP_ADDR11CP_ADDR12CP_ADDR13CP_ADDR14CP_ADDR15CP_ADDR16CP_ADDR17CP_ADDR18CP_ADDR19CP_ADDR20CP_ADDR21CP_ADDR22CP_ADDR23CP_ADDR24CP_ADDR25

CP_CS_N0CP_CS_N1CP_CS_N2CP_CS_N3CP_CS_N4CP_CS_N5CP_CS_N6CP_CS_N7CP_CS_N8

CP_R_WNCP_RD_NCP_DSACK_N

SYS_RSTI_N

NMI_N

EXTI0EXTI1EXTI2EXTI3EXTI4

CP_CLK27_OUT

CP_SIZE0CP_SIZE1

CP_ADDR_STRB_NCP_BERR_NCP_DATA_STRB_N

SYS_RSTO_N

MI_CS_N0MI_CS_N1

MI_MADDR00MI_MADDR01MI_MADDR02MI_MADDR03MI_MADDR04MI_MADDR05MI_MADDR06MI_MADDR07MI_MADDR08MI_MADDR09MI_MADDR10MI_MADDR11

MI_BANK_O0MI_BANK_O1

MI_MDBUS00MI_MDBUS01MI_MDBUS02MI_MDBUS03MI_MDBUS04MI_MDBUS05MI_MDBUS06MI_MDBUS07MI_MDBUS08MI_MDBUS09MI_MDBUS10MI_MDBUS11MI_MDBUS12MI_MDBUS13MI_MDBUS14MI_MDBUS15

MI_RAS_NMI_CAS_NMI_WE_N

MI_WMASK0MI_WMASK1

MI_DQS0MI_DQS1

TRST_NTMSTCKTDI

TDO

OUTENB_NTCC

QFE_XTIQFE_XTO

CLK27_VCXO_ICLK27_VCXO_O

PCRDAC

CLK27_OUT

CLK54_OUT

MI_MADDR12

CP_DATA00CP_DATA01CP_DATA02CP_DATA03CP_DATA04CP_DATA05CP_DATA06CP_DATA07CP_DATA08CP_DATA09CP_DATA10CP_DATA11CP_DATA12CP_DATA13CP_DATA14CP_DATA15

MI_DQS2MI_DQS3

CP_CLK40_OUT

MI_CKEMI_CLK

MI_CLK_N

EJTAG_SEL_N

EBI_R/WBEBI_RDB

SD_BA_1

SD_RASBSD_CASB

SD_BA_0

SD_WEB

SD_CSB_0

POR_RESETB

MANF_RXDMANF_TXD

FLASH1_CSBROM_CSB

IR_IN

EBI_ADDR_[24:0]

SRAMLB_CSB

EBI_DATA_[15:0]

SRAMUB_CSB

PKT_SYNCPKT_CLK

PKT_DATA

SPI_CLK

SPI_MOSISPI_MISO

MC_SPI_CSB

EJTAG_RESETB

MC_CLK27

MC_IRQB

SD_DATA_[15:0]

SD_ADDR_[12:0]

CH3/4_SEL

SD_UDQS_1

SD_UDM

SD_CLK

POR_IRQB

SD_CLKB

SD_LDQS_0

SD_CLKE

SYS_RESETB

SD_LDM

MSG_LEDPWR_LED

SEL_FLASH1/ROMB

INFO_CLKINFO_SYNCINFO_DATA

MC_CLK40

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RESET CONFIGURATION:cp_data00 RC: ebi_config Bitcp_data01 RC: boot_config Bitcp_data02 RC: Memory Clock Speed Select Bus Bit 0cp_data03 RC: Memory Clock Speed Select Bus Bit 1cp_data04 RC: MIPS Clock Speed Select Bus Bit 0cp_data05 RC: MIPS Clock Speed Select Bus Bit 1cp_data06 RC: MIPS Clock Speed Select Bus Bit 2cp_data07 RC: USB Normal Clock Source Selectcp_data08 RC: Internal clk27 Alternate Source Selectcp_data09 RC: MIPS After Reset Delay Enablecp_data10 RC: Staggered Reset Off Selectcp_data11 RC: Slip ckt controlcp_data12 RC: PLL By-Pass Select

DNI

DNI

DNI

SRAM

EBI_DATA_[15..13] to be used by

F/W to detect HW configurations.

EBI_DATA_[15..13] 111 = Quake Installed

EBI_DATA_[15..13] 000 = Quake RP Installed

TYPE/VENDOR

BOOT BLOCK FLASH

SIZE

Intel_ GE28F320C3BD70ST_M28W320ECB70_ZB1

BOOT BLOCK(U300)uBGA packageonly

TABLE 1: MEMORY OPTIONS

32 MBIT

DDR SDRAM SPEED SETTING

121.5MHz => EBI_DATA_[3:2] = 10

162MHz => EBI_DATA_[6..4] = 010

MIPS SPEED SETTINGDNI

DNI

DNI

DNI

DNI

Theplacement ofC302 shouldbe near theE1 and F5 ofU300.

Theplacementof C303should benear theD6 and E1of U301.

FLE-121-01-G-DV-A (SAMTEC)

ROM Socket Daughter cardinterface

DNI: (Install only for the Proto,EPR and PPR)

Layout Note: Remapping connectorsignals is allowed for layoutoptimization if necessary.

NOTE: All test padsshould be placed at thebottom layer

A

PLATFORM_FLASH & SRAM.SCH



C 864684-049

Title

Document Number Rev

Date: Sheet of

File NameSize

EBI_DATA_5

EBI_DATA_7

EBI_DATA_6

EBI_DATA_0

EBI_DATA_8

EBI_DATA_14EBI_DATA_13

EBI_DATA_15


SRAM_VBATT

EBI_ADDR_5

EBI_ADDR_15

POR_RAM_ENB

EBI_ADDR_4

EBI_ADDR_14

EBI_ADDR_17

SRAMUB_CSB


EBI_ADDR_16

EBI_ADDR_3


EBI_ADDR_9

EBI_ADDR_11

EBI_R/WB

EBI_RDB

SRAMLB_CSB

EBI_ADDR_8

EBI_ADDR_10

EBI_DATA_1

EBI_DATA_2

EBI_DATA_3

EBI_DATA_4

EBI_DATA_10EBI_DATA_11EBI_DATA_12

EBI_DATA_9

EBI_DATA_0EBI_DATA_1EBI_DATA_2EBI_DATA_3EBI_DATA_4EBI_DATA_5EBI_DATA_6EBI_DATA_7EBI_DATA_8EBI_DATA_9EBI_DATA_10EBI_DATA_11EBI_DATA_12EBI_DATA_13EBI_DATA_14EBI_DATA_15

EBI_R/WB

SYS_RESETBFLASH1_CSBEBI_RDB

SRAM_CSB

EBI_DATA_14

EBI_DATA_12

EBI_ADDR_3

EBI_ADDR_11

EBI_DATA_7

EBI_DATA_8

EBI_DATA_15

EBI_ADDR_9




EBI_ADDR_1

EBI_DATA_2

SEL_FLASH1/ROMB

EBI_DATA_3

EBI_ADDR_14

EBI_ADDR_5


EBI_DATA_1

EBI_ADDR_6


EBI_ADDR_10

EBI_DATA_6

EBI_ADDR_16

EBI_RDB

EBI_DATA_11

EBI_DATA_13

EBI_DATA_5


EBI_DATA_4

EBI_ADDR_20ROM_CSB

EBI_ADDR_9

EBI_ADDR_2



EBI_ADDR_3

EBI_ADDR_16

EBI_ADDR_13


EBI_ADDR_17

EBI_ADDR_24

EBI_ADDR_10

EBI_ADDR_14

EBI_ADDR_11

EBI_ADDR_4

EBI_ADDR_21

EBI_ADDR_12


EBI_ADDR_15

EBI_ADDR_18

EBI_ADDR_1

EBI_DATA_1

EBI_DATA_13

EBI_DATA_6

EBI_DATA_0

EBI_DATA_14

EBI_DATA_12

EBI_DATA_2

EBI_DATA_4

EBI_DATA_8

EBI_DATA_5

EBI_DATA_11

EBI_DATA_3

EBI_DATA_15


EBI_DATA_7

EBI_DATA_0

D

+3.3V

D

D

D

+3.3V

D

+3.3V

DD

TP303

TP3451U300

Intel_GE28F320C3BD70xxxxxx-xxx-xx

D8C8B8C7A8B7C6A7A3C3B2A2C2A1B1C1D1B6B5A6C5

E7F7D5E5F4D3E3F2D6E6F6D4E4F3D2E2

D7F8

B4

B3

A5

A4

F5E1

E8F1

C4

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20

D0D1D2D3D4D5D6D7D8D9

D10D11D12D13D14D15

CE/OE/

RP/

WE/

WP/

VPP

VCCVCCQ

GNDGND

A21

TP3021

RP301

10000_4

1234 5

678

R314 10K_s

TP3321

TP3351

R30010K_s

TP317 1

TP3381

C3020.01U_s

12

TP306 1

C3030.01U_s

12

TP313 1 TP3411

TP310 1

TP304 TP3301

TP316 1

TP3331

R317 10K_s

TP301

TP3361

TP3391

R315 10K_s

R307 10K_s

R308 10K_s

TP3421

TP351

1

TP352

R306 10K_s

R319 10K_s

TP307 1

TP3431TP315 1

TP3501

TP312 1

TP3441

RP300

10000_4

1234 5

678

R303 10K_sU301

CY62137VLL481396-001-69

B4B3A5A4A3

E1 D6

G4F3F4E4D3

C3C4D4H2H3H4H5G3

D1E6

C5C6D5E5F5F6G6B1C1C2D2E2F2F1G1

A2

G5

A1B2

A6B5

B6

H1H6G2 E3

A4A3A2A1A0

VCC

1VC

C2

A13A14A15A16nc17

A5A6A7A8A9A10A11A12

GND1GND2

I/O1I/O2I/O3I/O4I/O5I/O6I/O7I/O8I/O9

I/O10I/O11I/O12I/O13I/O14I/O15

/OE

/WE

/LB/UB

ncCS2/CS1

I/O0

nc1nc2nc3 nc4

Q3002sc2712

1

32

TP308 1

C3000.1U_s

12

TP3311

R311 10K_s

C3010.1U_s

12

TP319 1

R313 10K_s

R312 10K_s

R318 10K_s

TP3341

TP311 1

TP3371

R302 10K_s

R310 10K_s

R304 10K_s

R301

1K_s

R309 10K_s

TP3401

TP305 1

TP318 1

R305 10K_s

R316 10K_s

TP320 1

TP309 1

TP314 1

J300

hdr42_21x2_50_sm

1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 42

SRAMLB_CSB

SRAM_VBATT

SRAMUB_CSB

POR_RAM_ENB

FLASH1_CSBEBI_RDB

SYS_RESETB

EBI_R/WB

EBI_DATA_[15:0]

SEL_FLASH1/ROMB

ROM_CSB

EBI_ADDR_[24:1]

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

16 MBYTES UNIFIED DDR_SDRAM

Place caps near

U202

(DDR_SDRAM)

1%

1%

MICRON - MT46V8M16TG-6T

1. DDR_DATA[15:0] lines and strobes should be the shortest (and most direct) trace lengths as possible. 2. CK & CKB traces again should be the shortest possible lengths, with CK & CKB being adjacent to each other on ALL layers.3. DDR_ADDR[15:0], & control signals are not as critical as layout items 1 and 2.4. NO data or data strobe traces should exceed 2 inches in length. (The 2 inches includes traces to and from series terminationresistors) Less critical signals should be less than 3 inches. Clock traces can be up to 3 inches, but should be as short as possible.Route DQS and clock pair signal traces FIRST when laying out the board.5. Trace length variations are as follows:Data, DQS signal traces have no more than 0.5 inch variationAddress, DQM, control signal traces have no more than 1.0 inch variationClock traces should be as closely matched as possible.6. Clock traces should be on same layer(s) and should be spaced 5 mils from each other, with other signal traces spaced 10 mils away.7. Number of vias for data and DQS lines should be restricted to maximum of 2 per signal trace. Other signals should be restricted tono more than 3 vias per signal trace. Micro-vias (14 mil through hole) can be used for signals, with larger (20 mil minimum throughhole) used for power and grounds.8. Trace widths for signals should be 5-6 mils. Power and ground signals should have minimum 10 mil traces from pins to vias (that dropdown to power/ground planes)8a. DDR_VREF signal should be 20mil trace.9. DDR section of board should keep all signals that are NOT part of the DDR interface outside of defined area on ALL layers.10. Decoupling capacitors should be used in accordance with the DDR manufacturer's recommendations. Bulk bypass capacitors should belocated nearby DDR memory.11. Power and ground pins should have dedicated traces to VIA, with adjacent power and ground pins using common trace only whendistance to via is less than .2 inch from any one pin/ball. In this case a more robust trace should be used to connect more than onepin to the via. (15 mil trace minimum)

Place this capclose to theU202

LAYOUT NOTES:

467639-001

6.3V X5R

1206 See

table page 1

Place this capclose to the U200(QUAKE)

10% 50V X7R

10% 50V X7R

A

DDR_SDRAM.SCH



C 864684-049

Title

Document Number Rev

Date: Sheet of

File NameSize

DDR_ADDR_3DDR_DATA_6

DDR_UDM

DDR_ADDR_6

DDR_DATA_14

DDR_DATA_11

DDR_DATA_4

DDR_DATA_2DDR_DATA_1

DDR_LDM

DDR_ADDR_9

DDR_DATA_0

DDR_ADDR_7

DDR_DATA_7

DDR_DATA_3

DDR_ADDR_4

DDR_DATA_10

DDR_ADDR_1

DDR_DATA_15

DDR_DATA_13

DDR_RASB

DDR_WEB

DDR_ADDR_11

DDR_ADDR_0

DDR_DATA_9

DDR_DATA_5

DDR_BA_1

DDR_ADDR_5

DDR_CASB

DDR_CSB_0

DDR_ADDR_8

DDR_DATA_8

DDR_ADDR_2

DDR_ADDR_12

DDR_ADDR_10

DDR_BA_0

DDR_DATA_12

SD_VREF

DDR_LDQS_0DDR_UDQS_1

DDR_CKDDR_CLKE

DDR_CKB

DDR_BA_1

SD_DATA_8

DDR_DATA_10

DDR_ADDR_2

SD_LDQS_0

DDR_WEB

SD_CLK

SD_ADDR_10

SD_DATA_6

SD_DATA_0

SD_UDQS_1

DDR_DATA_3

SD_CSB_0

SD_ADDR_12

DDR_DATA_11

DDR_DATA_14DDR_DATA_13

DDR_ADDR_9

DDR_ADDR_6

DDR_LDQS_0

SD_DATA_3

DDR_UDQS_1

DDR_CK

DDR_ADDR_12

DDR_DATA_4

DDR_CKB

SD_CASB

DDR_ADDR_4

SD_ADDR_11

DDR_ADDR_0

SD_LDM

SD_DATA_7

DDR_DATA_5

DDR_DATA_0

DDR_RASB

SD_BA_0

SD_ADDR_6

SD_UDM

DDR_ADDR_10

SD_DATA_10SD_DATA_9

DDR_DATA_12

DDR_ADDR_11

DDR_ADDR_5

SD_CLKB

DDR_ADDR_1

SD_BA_1

DDR_CASB

SD_DATA_4

SD_DATA_1

DDR_DATA_6

DDR_DATA_1

DDR_DATA_7

SD_WEB

DDR_UDM

SD_ADDR_9

SD_RASB

DDR_LDM

SD_DATA_11

SD_DATA_14SD_DATA_13

DDR_BA_0

DDR_DATA_9

DDR_CSB_0

DDR_ADDR_3

SD_DATA_5

SD_DATA_2 DDR_DATA_2

SD_CLKE

DDR_ADDR_7SD_ADDR_7

SD_DATA_12

SD_ADDR_8

SD_ADDR_2SD_ADDR_3

SD_ADDR_5

DDR_ADDR_8

SD_ADDR_1

SD_ADDR_4

SD_ADDR_0

DDR_DATA_8

DDR_CLKE

DDR_DATA_15SD_DATA_15

D

D

D

+2.5V

+2.5V

D

D

+2.5V

D

D

D

R419 33_s

R424 33_s

RP402

33_8

12345678 9

10111213141516

R410 33_s

R416 33_sR40210K_s

R420 33_s

C40810P_s

R407121_s

R404121_s

R409 33_s

C4111U_s

RP401

33_8

12345678 9

10111213141516

C40110U_c

12

R412 33_s

R423 33_s

R417 33_s

C4000.01U_s

12

R4011K_s

R405121_s

R411 33_s

R413 33_s

C4031000P_s

12

R406121_sR428 20_s

R4001K_s

R414 20_s

C4060.01U_s

C4101000P_s

12

C4050.1U_s

12

R421 33_s

R418 33_sR40310K_s

C4040.01U_s

12

R408 33_s

RP400

33_8

12345678 9

10111213141516

C4090.01U_s

12

C40710P_s

R422 33_s

R415 33_s

8M x16

U400 1

24578

1011135456575960626365

2930313235363738394028414217

36

14

15

16

18

19

21222324

25

2627

3334

43

44454647

48

49

50

51

52

53

5558 64

61

669

12

20

VDD

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15

A0A1A2A3A4A5A6A7A8A9

A10/APA11A12

NC (A13)

VDD

QVS

SQ NC

VDD

Q

LDQS

VDD

DNU

WECASRASCS

NC

BA0BA1

VDD

VSS

NC

CKECKCKUDM

VSS

VREF

DNU

UDQS

VSSQ

NC

VDD

QVS

SQVS

SQVD

DQ

VSS

VDD

Q

VSSQ

LDM

SD_DATA_[7..0]

SD_WEB

SD_ADDR_11SD_ADDR_9

SD_LDQS_0SD_LDM

SD_BA_1

SD_CLK

SD_UDQS_1

SD_ADDR_12

SD_CASB

SD_BA_0

SD_ADDR_7

SD_CLKB

SD_UDM

SD_DATA_[15..8]

SD_RASB

SD_ADDR_10

SD_CSB_0

SD_ADDR_8

SD_ADDR_[6..0]

SD_CLKE

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Low Leakage Cap

TDO

Bypass

DNI

A

SECURITY.SCH



C 864684-049

Title

Document Number Rev

Date: Sheet of

File NameSize

SYS_RESETB

POR_RESETB

PKT_DATAPKT_SYNCPKT_CLK

VBATT

MC_CLK27

MC_IRQB

MC_RESETB

SPI_MISO

INFO_DATA

SRAM_VBATT

INFO_CLKMC_PKTDATA

MC_PKTSTART

SPI_CLK

MC_CLK40

MC_PKTCLK

SPI_MOSI

INFO_SYNC

MC_SPI_CSB

JETJET JET

BTV

BTV

JET

BTV BTV BTV

JET

D

+3.3V

+3.3V

+3.3V

D

DD

D

DD

DD

D

+3.3V

D

D

+3.3V

D

+3.3V

C9004700P_s

12

R903470K_s

R906

620_sVB903TESTPIN

BT9033_0V_BR2335T3L_B123002-020-99

213

C9020.1U_s

12

VB901TESTPIN

D9111n4148w

21

CLK27MTEST_PAD

D9011n5711

13

C9084700P_s

12

C9054700P_s

12

BT9053_0V_BR2032T3L_B

213

C9040.1U_s

12

+ C910100uf_07

12

C9034700P_s

12

C9090.1U_s

12

+C91410u_50v

12

R904470K_s

VB902

TESTPIN

BT9063_0V_BR2330A_GA

213

RP900

33_4_s

1234 5

678

TD900

R926 51_s

RP901

470_4

12345

678

C9110.1U_s

12

C9130.1U_s

12

R92210K_s

D9021n4148w

21

VB900TESTPIN

MC1.7

U900

MC1_7C

123 4

5

89 10

11

1213

1617

1819

22232425 26

28

32

333435

100

99

97

9492

89

8887868584838281

787776

7 15 20 27 29 42 48 53 59

6 14 21 30 46 47 54 6071 31 41

70 72 80 91 93 95

90

3637383940

434445

7574

6867666564636261

58

49 50

575655

5251

69

73

79 96

98

SCLKSPL_CSBMOSI MISO

UP_INTB

TVPC_CLOCKTVPC_DETECTB TVPC_SIO

TVPC_RESETB

TVPC_3V_SENSETVPC_5V_SENSE

VBATTGNDBATT

PDUNDERBVSUPPLY

TMROEBTMSTCKTDI TDO

PKTCLKOUT

PKTSTARTOUT/MOSTRT

PKTDATAOUT/MDO0MDO1MDO2

CLK_27

CTRL_CLK_27

RESETB

SYNC_CLKPKTCLKIN/BITCLK

PKTSTARTIN/MISTAT

PKTDATAIN/MDI0MDI1MDI2MDI3MDI4MDI5MDI6MDI7

MIVALMCLKIMIERROR

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

VDD

3VD

D3

VDD

3VD

D3

VDD

3VD

D3

VDD

3

VDD

3

VDD

3

VDD

3VD

D3

GN

DG

ND

GN

DG

ND

GN

DG

ND

VDD

3

MDO3MDO4MDO5MDO6MDO7

MOVALMCLKO

MOERROR

TESTSELTESTWRB

TAD0TAD1TAD2TAD3TAD4TAD5TAD6TAD7

TESTOUT0

FUSE1 FUSE1RTN

TESTOUT1TESTOUT2TESTOUT3

FUSE0RTNFUSE0

VDD

3

TESTCLK

VDD

3

VDD

3

VBATT_EN

C9060.1U_s

12

C9010.1U_s

12

C91547P_s

12

BT907106007-002

12

C90747P_s

12

D912bat54alt1

3

2

1

BT9043_0V_BR2450A_GB414816-003-99

213

R9144.7K_s

INFO_CLK

POR_RESETB

SRAM_VBATT

WRPROT_1

INFO_SYNCPKT_DATAPKT_SYNC

MC_SPI_CSB

POR_RAM_ENB

SYS_RESETB

MC_CLK40MC_CLK27

INFO_DATA

SPI_CLK

WRPROT_3

SPI_MOSI

PKT_CLK

MC_IRQB

SPI_MISO

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Place no traces or parts betweenAUDIO_LEFT_POS/AUDIO_LEFT_NEG andAUDIO_RIGHT_POS/AUDIO_RIGHT_NEG.Keep traces close in length androute traces next to one another.Surround each pair with DGND.

Surround video traceDIG_COMPOSITE with DGND.

Place bypass capacitors of +3.3v, +2.5v, and+1.2V near IC's pin on bottom side.QUAKE pin numbers for each cap areindicated.

AB5AB6

AB12AB13

A17(DAC B)

AB14AB15AB17AB18

AB21AB22W22

E8E9E10

E15E18

G22J22L22N22R22

K5L5

V5Y5

VIDEO DAC CALCULATIONSIoutfs = 17.4 mA with Rbias = 628 ohmsChoose Rbias = 562 ohmsRload = 75 ohms (see video page)Dwhite = 364 (9 bit value) NTSCDsync = 14 (9 bit value) NTSCVout p-p = Ioutfs * (628 ohms / Rbias) *Rload * ((Dwhite - Dsync)/511) = 1 Vp-p

E21E22

U22V22

AB16 E6E7

M5N5E11

AB19AB20AA5

Place these parts nearQUAKE.

DAC A, C & D not used.

DAC A, C & D not used.

Signal Opitimize

467639-001

6.3V X5R

1206 See

table page

1

467639-001

6.3V X5R

1206 See

table page

1

A

QUAKE_ANALOG.SCH



Custom 864684-049

Title

Document Number Rev

Date: Sheet of

File NameSize

+3.3VA0

+3.3VA5

+3.3VA2

SDC_AVDD

+1.2VA2

+3.3VA7

+3.3VA6

+3.3VA3

+1.2VA5

+3.3VA4

+1.2VA1

ANA_1.2V

+1.2VA3

+1.2VA4

+3.3VA8

+3.3VA9

+3.3VA1

ANA_3.3V

D

D

+1.2V

+3.3V

+2.5V

A

D

A

+3.3V

D

+1.2V

D

A

A

D

+3.3V

+3.3V

D

+3.3V

+3.3V

D

D

A

A

D

+3.3V

D

C4220.1U_s

L40110uH_c_1008

L423ferrite_0603

1 2

C4360.1U_s

R47330.1K_s1%

C471

1U_s

C4260.1U_s

L424ferrite_0603

1 2

C4370.1U_s

C4480.01U_s

L413ferrite_0603

1 2

L425ferrite_0603

1 2

C4550.1U_s

C4270.1U_s

C4721U_s

QUAKE Analog

(UO_IREFD)

U200A Quake

K25K26

A23A25

R25R26C23T25T24

F26E23

U26U25U24

D18

C14D14A14B14

AD22AE22AF22

B16E16B17E17

C18

M23M25

N26N25

J24J23

M24

D26C24A24B26

B23

J26H22

P24P23

H24

A18

H25

P25

H23

F23

C17

C16

DI_ADC1_VINDI_ADC1_VIP

DI_RFAGC_SDVDI_AGC_SDV

DO_ADC3_VIPDO_ADC3_VINDO_AAGC_SDDO_LO_BPDO_LO_BN

UO_IOUTPUO_IOUTN

TNR_RFTCKTNR_RFTD

TNR_RFTE0

AUD_DIGAUD

AUD_LEFT_POSAUD_LEFT_NEG

AUD_RIGHT_POSAUD_RIGHT_NEG

AUD_I2SI_DATAAUD_I2SI_LRCLKAUD_I2SI_CLK

QVD_DV_D_PQVD_DV_C_PQVD_DV_B_PQVD_DV_A_P

QVD_RBIAS

BTSC_ADC2_VREFPBTSC_ADC2_VCM

BTSC_ADC2_VINBTSC_ADC2_VIP

AVD_ADC1_VIPAVD_ADC1_VIN

BTSC_ADC2_VREFN

UO_PWR0_GATEBUO_PWR1_CLK

UO_PWR2_DATAUO_PWR3

UO_RF_SD_OUT

DI_ADC1_VREFNDI_ADC1_VREFP

DO_ADC3_VREFNDO_ADC3_VREFP

QFE_ADC_VBGOUT

QVD_VREF

QFE_EXT_IREF

DO_ADC3_VCM

DI_ADC1_VCM

UO_DAC_BG_PSUPA

QVD_AVSS_BIAS

QVD_AVSS_BIAS2C465

1U_s

C4870.1U_s

C466

1U_sC450

10U_c

L412ferrite_0603

1 2

RP4111000_4

1 2 3 45678

C4840.1U_s

C4750.1U_s

12

RP4101000_4

1 2 3 45678

C4400.1U_s

L421ferrite_0603

1 2

C463

1U_s

L410ferrite_0603

1 2

C4530.1U_s

L422ferrite_0603

1 2

C434

10U_c

C4410.01U_s

L418ferrite_0603

1 2

C4560.1U_s

12

C4190.1U_s

C4450.1U_s

C4350.1U_s

L420ferrite_0603

1 2

C4380.1U_s

C4740.1U_s

L411ferrite_0603

1 2

C4210.1U_s

C482

0.1U_s C4430.1U_s

C4420.1U_s

C4250.01U_s

C4850.1U_s

C467

1U_s

QUAKE Power

U200C Quake

AB12AB13

J22

K5 L22

L5 N22

AB6AB5 AB19

AB20

E11E21E22

E6

G23J25

L25L24

G25

N23P22

E24

G26

E26E25

M22L23

H26K24

K23

P26R24

G24

D25

D16

A17D17

B18

A16

M26N24

L11L12L13L14L15L16M11M12M13M14

M15

M16

N11

N12

N13

N14

N15

N16

P11

P12

P13

P14

P15

P16

R11

R12R13R14R15R16T11T12T13T14T15T16

T26

T23

R23

E14E13

D24F22E1

8G

22

E8 E15

E9

AA5

Y5

AB16

V5

R22

W22

AB22

E10

AB21AB18

AB15AB17

AB14

F24

T22

F25

C22D22

C20 E19

E7

M5N5U22V22

VDD25VDD25

VDD

12VD

D12

VDD

12VD

D12

VDD

12

VDD25VDD25 VDD33

VDD33

VDD33VDD33VDD33

VDD33

DI_ADC1_NSUPADI_ADC1_NSUPA_SHA

QFE_XTAL_NSUPAQFE_ADC_ASUB

VSS_PLL

DO_ADC3_NSUPADO_ADC3_NSUPA_SHA

UO_DAC_NSUPA

UO_DAC_NSUPD

UO_DAC_BG_NSUPAUO_DAC_ASUB

BTSC_ADC2_NSUPA_SHABTSC_ADC2_NSUPA

DI_ADC1_PSUPADI_ADC1_PSUPA_SHA

QFE_XTAL_PSUPA

DO_ADC3_PSUPADO_ADC3_PSUPA_SHA

VDD_PLL

UO_DAC_PSUPD

QVD_AVDD_C

QVD_AVDD_BQVD_AVDD_A

QVD_AVDD_BIAS

QVD_AVDD_D

BTSC_ADC2_PSUPABTSC_ADC2_PSUPA_SHA

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSS VS

SVS

SVS

SVS

SVS

SVS

SVS

SVS

SVS

SVS

SVS

SVS

SVS

SVS

SVS

S

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

DO_LO_VBB

DO_LO_VSSB

DO_LO_BGND

SDC_AGNDSDC_AVDD

UO_QUIET_NSUPDUO_QUIET_PSUPDVD

D12

VDD

12

VDD

12

VDD

12

VDD

12

VDD33

VDD12

VDD33

VDD12

VDD

12

VDD12

VDD

12

VDD

12VDD12VDD12

VDD12VDD12

VDD12

UO_DAC_PSUPA

DO_LO_VDDB

UO_VBIAS

QFE_PGNDQFE_VPP

XTAL_CLK27_PSUPA XTAL_CLK27_NSUPA

VDD33

VDD33VDD33VDD33VDD33

R475 470_s

C4460.01U_s

L415ferrite_0603

1 2

C4730.1U_s

C493

1U_s

C4280.1U_s

R4728.06K_s1%

C4390.1U_s

C4540.1U_s

L402

10uH_c_1008

L414ferrite_0603

1 2

C4470.1U_s

C492

1U_s

C4440.01U_s

C481

1U_s

R474562_s1%

L419ferrite_0603

1 2

C4570.1U_s

12

C4860.1U_s

C4240.01U_s

C4320.1U_s C420

0.01U_s

RP412470_4

1234 5

678

C4230.01U_s

C464

1U_s

TX_DAC-

OOB_IF_NEG

AUDIO_RIGHT_POS

OOB_IF_POS

IB_IF_NEG

AUDIO_RIGHT_NEG

AUDIO_LEFT_POS

TX_DAC+

OOB_VCO_POS

TX_OEN

IB_IF_POS

OOB_VCO_NEG

DIG_COMPOSITE

AUDIO_LEFT_NEG

US_CTL_CSBUS_CTL_CLKUS_CTL_DATA

TUNER_SDATUNER_SCLKOOB_AGC

QAM_AGCI

QAM_AGCT

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

2 Vrms at 0 dBFS.

1.132 Vrms at 0 dBFS2 Vrms at 0 dBFS.

MC44BC375U data sheet: 85% FM modulation at 1 kHz with 205 mVrms input at pin 7, with pre-emphasis.Pre-emphasis gain at 1 kHz = 0.87 dB. 100% modulation = +/- 25 kHz.To achieve +/- 50 kHz FM modulation (200%) without pre-emphasis, the nominal input level at pin 7 is:2*(205 mVrms)*(0.87 dB)/(85%) = 534 mVrms.The digital audio level at the top end of R853 must be greater than 534 mVrms in order to achieve alignment.Target value = 566 mVrms for analog channel and 1132 mVrms for digital channel.

Loop Filter mustbe as close aspossible to pins14&15

Lowpass filter, F3dB = 159 kHz

10%

Place no traces or parts betweenAUDIO_RIGHT_POS and AUDIO_RIGHT_NEG.Keep traces close in length and routetraces next to one another. Surroundthe pair of traces with digital groundplane.

2 Vrms at 0 dBFS.

Place no traces or parts betweenAUDIO_LEFT_POS and AUDIO_LEFT_NEG.Keep traces close in length and routetraces next to one another. Surroundthe pair of traces with digitalground plane.

2 Vrms at 0 dBFS.

Audio DAC Filter and Output Amp

Video DAC Filter and Output Amp

Video/Audio RF Modulator (Remod)

Change tosurface mount.TDK partNLFV25T-100K.

Must be X7R

X7R

A

AUDIO_VIDEO.SCH



C 864684-049

Title

Document Number Rev

Date: Sheet of

File NameSize

DAC_AUD_LEFT REMOD_AUDIO

DAC_AUD_RIGHT

REMOD_VIDEO

DAC_AUD_RIGHT

DAC_AUD_LEFT REMOD_VIDEO

D

A

A

A

A

A

A

A

A

A

AAA A

+5V

D

-5V

D

D

-5V

D

+5V

D

D

D

+5V

D

D

-5V

D

D

+5V

AA

R7041K_s1%

C820 0.1U_s

C723 22P_s1 2

C8070.01U_s

C822

0.1U_s

C70410P_s1 2

R7348.25K_s1%

C720270P_s

12

C7020.1U_s

12

R735 100K_s 1%

C817750P_s5%, NPO

C739100P_s

C721 22P_s1 2 C719

0.1U_s

12

R7278.25K_s1%

R7071K_s

R73747.5K_s 1%

R7431.3K_s1%

R806150_s

RES\1%\0603

R70220_s

C707100P_s

C725270P_s

12

C816 27P_s

R80710K_s

R8087.5K_s

C7180.1U_s

12

C803 7P_s

L111910uH_c_1008

R705510_s

R809

50K_POT

13

2

R803

2.2K_s

C745100P_s

C8150.1U_s

C813

0.01U_s

R732 100K_s 1%

C8100.01U_s

C80243P_s

C812

0.1U_s

L804

3.3uH_c_1210

R7143.3K_s

Q7022sc2712

1

32

R7412K_s 1%

C726 22P_s1 2

R8101K_s

D800smbj13

21

R700102_s1%

C808

0.047U_s

Y800 4MHz

C8190.022U_s

R7133.3K_s

L7006.8uH_c_0805

C8211000P_s

R7288.25K_s1%

Q7012sc2712

1

32

+

-

U700BNJM4580128006-129-265

67

84

U800

mc44bc375u

1234

5

6789

10

11

12

13

14

1516CHS

PSSLOPXTAL

GND

PREEMAUDIOSPLFLTPS/LO

VIDEO

VCCA

GND

TVOUT

TVOVCC

PLLFLTSFS

R805560_s

L801120nH_c_0603

1 2

C701150P_s

12

R7031.2K_s

R80127_s

R7338.25K_s1%

R800470_s

C80436P_s

C724 22P_s1 2

R738 100K_s 1%

R73647.5K_s1%

C805 9P_s

C8000.01U_s

R804

2K_POT118874-513-14

13

2

R73047.5K_s1%

R70875_s1%

R802470_s

C809 0.022U_s

R72947.5K_s1%

Q7002sc2712

1

32

C7030.1U_s

12

C8181U

C700270P_s

12 R706

887_s1%

L800150nH_c_06031 2

R701280_s1%

F800

tps4_5mb2

13

2

+C1142

10uf_01

12

+

-

U700ANJM4580128006-129-263

21

84

R7422K_s 1%

L8034.7uH_c_0805

1 2

C814

1000P_s

R731 100K_s 1%

CH3/4_SEL

AUDIO_LEFT_POSLINE_OUT_LEFT

LINE_OUT_RIGHT

AUDIO_RIGHT_NEG

AUDIO_LEFT_NEG

AUDIO_RIGHT_POS

DIG_COMPOSITECOMP_OUT

REMOD_OUT

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

3. Keep these 2 traces very close to each other. Don't route under bypass caps. Don't place any trace between them.

70 to 130 mhz LPF. Helps to

reduce LO leakage and also

reject signals above 130

MHz.

Note 3

1. Use 0603 chip caps and resistors.

2. LA7784 Batwings must be connected to ground.

Notes :

Keep the bypass capacitors very

close to the pins of the LA7784

See note 3See note 3

149188-018

180 MHz Lowpass Filter

Inductors are TDK MLG1608 series

OOB Tuner


10%

Inductors are TDK MLF1608 series

10%

QAM IF SAW Filter and AGC Amp

10%

10%

10%

10%

501442-002

See table page 1.10V Y5V 0805

L1110 should be

changed by new

part number

L1112 should be

changed by new

part number

C1100 C1101 Do not install

Table 1

C1102 C1103 Do not installL1100 L1101 0 ohm resistorL1102 L1103 0 ohm resistor

R1100 1000 ohms 1%R1101 R1102 499 ohms 1%

L1104 L1105 0 ohm resistor

A

AFE.SCH



C 864684-049

Title

Document Number Rev

Date: Sheet of

File NameSize

+5VA_OOB

SAW_IF_NEG

+5VA_IB

SAW_IF_POS

A

A

A

A

A

A

A

A

A

A

+5V

A

A

A

A

+5VA_OOB

+5VA_OOB

L11041.5uH_c_0603

C11241000P_s

12

TP1104

TUNER_IF

L111827nH_c_0603

R110749.9_s1%

R111023.7_s1%

TP1106OOB_IF_NEG

L1108100nH_c_0603

TP1105OOB_IF_POSC1130

6P_s

12

L11021.5uH_c_0603

C11250.1U_s1 2

C11200.01U_s

12

L111327nH_c_0603

R110923.7_s1%

F1100

x6964m

1

2 45

3IN

ING POUT1POUT2

CHIP

C114027P_s

TP1103QAM_AGCI

L11001.5uH_c_0603

L1111100nH_c_0603

R1102499_s 1%

R110351_s

L110610uH_c_1008

C11360.01U_s1 2

L1112220nH_c_0603

1 2

L111727nH_c_0603 TP1107

AGND

C11050.01U_s1 2

C11210.01U_s

12

C11350.01U_s1 2

C113212P_s

12

C11315P_s1 2

TP1108OOB_AGC

C11220.1U_s

12

F1101

saf49_10mc220z

1

245

3 IN

CHIPPOUT1POUT2

SOUT

C11410.1U_s

12

+C1109

10uf_01

12

U1101LA7784

471105-001-32

1 2 3

23

24

26

27

4 5

12

13

6 7 11 15 25 28

1419 20

9

10

16

17

18

21 228

NC

_GN

D

NC

_GN

D

GN

D

RF_IN1

RF_IN2

MIX_OUT1

MIX_OUT2

IF_I

N1

IF_I

N2

OUT1

OUT2

NC

_GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

VCC

_PO

ST_A

MP

VCC

_MIX

_LO

VCC

_DR

IVER

AGC_IN

NC

_GN

D

LO_IN1

LO_IN2

NC

_GN

D

VCC

_LN

A

VCC

_LN

A

VCC

_IF

C113411P_s

C11280.01U_s1 2

C11339P_s1 2

U1100

LA7783469774-001-28

1

16

2 7 15

3

4

5

9

8

10 1214

6

1311

IF_IN+

IF_IN-

GN

D

GN

D

GN

D

AGC_SW

DELAY_ADJ

VCC

IF_OUT-

IF_OUT+

DR

V_AM

P_VC

C

VCC

AGC

_VC

C

AGC_OUT2

AGC_OUT1AGC_IN

C11270.01U_s

12

C11070.1U_s

12

TP1101IB_IF_NEG

C11035P_s

12

L11031.5uH_c_0603

R1101499_s 1%

C113847P_s

C11230.1U_s

12

L111427nH_c_0603

C113947P_s

C11019P_s

12

R11001K_s1%

C11260.1U_s1 2

C113727P_s

C11100.1U_s

12

C11029P_s

12

L11011.5uH_c_0603

C11080.01U_s

12

C11040.01U_s1 2

C11290.01U_s

1 2

C11005P_s

12

L111527nH_c_0603

L1109100nH_c_0603

R110451_s

L1110120nH_c_0603

TP1102AGND

L11051.5uH_c_0603

TP1100IB_IF_POS

R110575_s

L111627nH_c_0603

OOB_IF_POS

OOB_AGC

OOB_IF_NEG

OOB_VCO_POS

OOB_VCO_NEG

OOB_TAP

IB_IF_NEG

QAM_AGCI

IB_IF_POSQAM_IF+

QAM_IF-

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Place these parts near tuner IC.Place these parts near QUAKE.

70 MHz Highpass Filter


Place close to

the ALPS TUNER

Inductors are TDK MLG1608 seriesSEE OPTION TABLE 1

R603R604

Option Table 1

L609L608

L607L606

L605L604 C614

MicrotuneMT1530

13.0,1%

SEE OPTION TABLE 1 463131-001

SEE OPTION TABLE 1

Upstream Amp56nH

15.8, 1%

C613 C612 C611 R600

56nH

100nH 82nH

0.1uF

SEE OPTION TABLE 1

467639-001

6.3V X5R

1206

DNI

C603 C604

AnadigicsARA2018SanyoLA7791T

35.7,1%

35.7,1%

15.8,1%

180nH

56nH

82nH

220nH 180nH 56pF

120pF

120pF

100pF

330pF

220pF

100pF

330pF

220pF

56pF

120pF

120pF

93.1,1%26.1,1%31.6,1%

15pF

DNI

6800pF

270pF

0.1uF

A

TUNER_UPSTREAM.SCH

San Diego, California, U.S.A. Taipei, Taiwan R.O.C.


864684-049

Title

Document Number Rev

Date: Sheet of

File Name

SCLKSDA

SCLK

UPSTREAM

SDA

UPSTREAM

JET

DA

+5V

A

+5V_TUNER

AD

A

A

A

A

+5V_TUNER

A

+5V_TUNER

AA

A

AA

+5V_US

+5V_US

A

A

+5V

A

A

A

A

A

A

A

A

+5V_US

A

A

A

A

+5V_US

A

+5V_US

A

A

A

R505 470_s

RP600

33_4_S

1234 5

678

C6160.01U_s

R5231M_2010

C53827P_s

C604 0.1U_s

C608 0.01U_s

C612330P_s

C613330P_s

Q5012sc5227_5

1

32

C524120P_s

C54018P_s

L52310uH_c_1008

C559

100P_s

C537100P_s

L60756nH_c_0603

R501 1K_s

C6010.1U_s

C6070.01U_s

12

L60656nH_c_0603

C526470P_s

L521270nH_c_1008

1 2

D500smbj13

21

R6010_s

C54239P_s

R6020_s

C5251000P_s

C539100P_s

L511150nH_c_0603

1 2

U600la7791t

1218

5

6

2

4

1131

20

19

17

16

15

1413

71098

/SHDNTXEN

VIN+

VIN-

VCC1

GND1

NCGNDGND

GND2

VCC2

NC

VOUT+

VOUT-

VCMNC

DGNDSCLK

SDA/CS

C614120P_s

+ C557470u_10v

12

R503 470_s

L60856nH_c_0603

R60413_s1%

L513120nH_c_0603

12

C6050.01U_s

12L610

10uH_c_1008

R5224.7_s

L60456nH_c_0603

R502 470_s

S501

Diplexer shield

234

5 6 7 8

9101112

13141516

1GNDGNDGND

GN

DG

ND

GN

DG

ND

GNDGNDGNDGND

GN

DG

ND

GN

DG

ND

GND

C5551000P_s

C5010.1U_s

R5260_s

T600

458pt_1087

1 6

2

3 4

C563

100P_s

C5000.1U_s

12

C6001000P_s

C611120P_s

C603 6800P_s

C53633P_s

C5531000P_s

C533150P_s

C602

0.1U_s

L60956nH_c_0603

R60313_s1%

R60026.1_s

R504 470_s

TUNER1TDEZ1X002A

7

2

1

5

11

8

6

12

4

93

1013141516

AS

GND

RF_IN

SCL

IF-

GN

D

SDA

IF+

+5V

OPENAGC

GNDGNDGNDGNDGND

L519390nH_c_1008

1 2

L512390nH_c_1008

12

C53222P_s

C5541000P_s

C535390P_s

L520270nH_c_1008

1 2

R521470_s

C5272P_s

C53422P_s

C609 0.01U_s

C55810U_c

C6100.1U_s

L60556nH_c_0603

C564

100P_s

+C617470u_10v

12

C54182P_s

C560

100P_s

L5001uH_c_1008

1 2

L522

27uH_r

12

R500

150_s

L517100nH_c_1008

12

L516120nH_c_1008

12

C5560.1U_s

12

C6060.01U_s

12

C6150.01U_s

R519120_s

R5201.2K_s

E500

RF_conn

L518390nH_c_1008

1 2

TUNER_SDATUNER_SCLK

QAM_IF+

QAM_IF-

QAM_AGCT

OOB_TAP

TX_DAC+

TX_DAC-

TX_OEN

US_CTL_CLK

US_CTL_CSBUS_CTL_DATA

dct700 ph0

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