ddr ecc to improve memory reliability in 66ak2g2x-based

DDREMIF

66AK2G

Control Address Data

Device_0

Device_ECC

Device_n

«�«

1TIDUBO4B–April 2016–Revised June 2018Submit Documentation Feedback

Copyright © 2016–2018, Texas Instruments Incorporated

DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx-Based Systems

TI Designs: TIDEP-0070DDR ECC Reference Design to Improve Memory Reliabilityin 66AK2Gx-Based Systems

TI DesignsThis reference design describes system considerationsfor the DDR-SDRAM memory interface with ErrorCorrecting Code (ECC) support in high-reliabilityapplications based on the 66AK2Gx Multicore DSP +ARM® System-on-Chip (SoC). System interfaces,board hardware, software, throughput performance,and diagnostic procedures, are discussed. Detaileddescription about the DDR interface is available in thedevice Technical Reference Manual (TRM).

Design Resources

TIDEP0070 Design Folder66AK2G02 Product Folder66AK2G12 Product FolderK2G General PurposeEVM EVM Tool Folder

Processor SDK for K2G Download Software

ASK Our E2E Experts

Features• 32-bit DDR3L Interface With Optional 4-bit ECC for

High-Reliability System Designs• Flexible System Configurations With DDR ECC• Built-In Read-Modify-Write (RMW) Hardware

Supporting ECC Operation With Non-AlignedAccess

• Minimum Performance Impact• Implemented and tested on EVMK2G Hardware

and Supported in Processor SDK for K2G

Applications• Automotive Audio Amplifiers• Home Audio• Professional Audio• Power Protection• Industrial Communications and Controls

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and otherimportant disclaimers and information.

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=TIDUBO4B

http://www.ti.com/tool/tidep0070

http://www.ti.com/product/66AK2G02

http://www.ti.com/product/66AK2G12

http://www.ti.com/tool/evmk2gx


http://www.ti.com/tool/Processor-SDK-K2G

http://e2e.ti.com

http://e2e.ti.com/support/applications/ti_designs/

1

DDR3

Connectivity

ARM®

Cortex-A15

-

Ethernet

Service Port

Optional Simple LCDDisplay

UART

Field- Level

100Mb

Industrial

Ethernet

Control - Level

100Mb

Industrial

Ethernet

or Custom

Backplane

SD Card

66AK2G02

Copyright © 2016, Texas Instruments Incorporated

C66x

DSP

USB Flash Drive

USB2/3

SD/MMC

Display

Subsystem2x

PRU ICSS

PCIe

GPMC

SPI

I2C

UART

CAN

GbE

IndustrialEPHY

IndustrialEPHY

IndustrialEPHY

IndustrialEPHY

GbEPHY

Introduction www.ti.com

2 TIDUBO4B–April 2016–Revised June 2018Submit Documentation Feedback



1 IntroductionThe 66AK2Gx SoC supports the following features:• Processor Cores and Memory

– Arm® Cortex-A15 up to 1000 MHz• 32 KB L1D, 32 KB L1P, 512 KB L2 cache

– C66x DSP up to 1000 MHz• 32 KB L1D, 32 KB L1P, 1 MB L2 cache or RAM

– 1MB of Shared L2 MSMC SRAM– ECC on all memory

• Industrial and Control Peripherals– 2 Industrial Communication Subsystems enable cut through, real-time and low-latency Industrial

Ethernet protocols– Programmable real-time I/O enables versatile field bus and control interfaces– PCIe for connection to an FPGA or ASIC that provides industrial network connections, backplane

communication or connection to another 66AK2Gx device• Security and Crypto

– Standard secure boot with customer programmable OTP keys– Crypto Engine hardware accelerator and TRNG– Package

• 21 x 21 mm, 0.8 mm pitch BGA 625 pins

The 66AK2Gx SoC is suited for applications such as Industrial PLC and Protection Relay as shown inFigure 1 and Figure 2. In these systems ECC on the memory is required for achieving reliabilityrequirements. Device reliability requires managing failures that can cause the device not to functioncorrectly at any point during its expected lifetime.

Figure 1. Industrial PLC System Block Diagram

http://www.ti.com


DDR3

Connectivity

ARM®

Cortex-A15(Control, Comms)

2x

PRU - ICSS

GbE

Ethernet

C66x

DSP

(Analytics,

Metering)

UART

Ethernet

Ethernet

Ethernet

Ethernet

IEC61850 or

66AK2G02


Display

Subsystem

SPI

I2C

UART

CAN

PCIe

GPMC

Simple LCD Display

Gb

EPHYIEC61850 to SCADA

Industrial

EPHY

Industrial

EPHY

Industrial

EPHY

Industrial

EPHY

Industrial

EPHY

USB2/3

SD/MMC

C66xDSP

(Analytics, Metering)

www.ti.com Introduction




Figure 2. Protection Relay System Block Diagram

Error Correcting Code (ECC) memory is commonly used in server and communications infrastructuresystems today and has significantly improved system reliability. In embedded systems, a similar trend isobserved, where ECC memory is required for a variety of applications, such as:• Safety-critical industrial and factory automation systems• Harsh operating environment such as extreme temperature, pressure or radiation environment• Always-on systems with extended duty hours

http://www.ti.com


Non-Ecc Failure Rates (Year)

Fai

lure

Rat

e

0

0.25%

0.5%

0.75%

1%

1.25%

1.5%

2011 2012 2013

1.16%

0.93%0.83%

0.53%

0.19%

0%

D001

Non-ECCECC

Introduction www.ti.com




Figure 3 shows the relative failure rate reduction when ECC is used.

Figure 3. Memory Failure Rate Reduction With ECC

The 66AK2Gx SoC supports various methods of ECC in its internal memory and external memoryinterfaces. Namely, ECC is supported on:• Processor core memory blocks• Internal Multicore Shared Memory Controller (MSMC) SRAM• Embedded SRAM memory blocks in other subsystems• DDR3L memory interface

Except for the L1P in the A15 processor core, all ECC functions listed above implement Single ErrorCorrection and Double Error Detection (SECDED) method using Hamming Code.

This design guide focuses on the DDR interface design with ECC in systems where high reliability isrequired. The DDR3L memory interface supports standard 32-bit DDR3L interface up to 800MT/s.Additional 4-bit data is available to support optional Error Correcting Code (ECC). ECC is performed on32-bit quanta based on the SECDED algorithm. When the DDREMIF is used as 16-bit interface, no ECCis supported.

http://www.ti.com


DDREMIF (only shown RMW ECC and FIFOs)

Command/Data

FIFOs

Read Modify Write

ECC

To DDR 3L

SDRAM

Command/Data

SchedulersTo MSMC


66AK2G

DDREMIF

MSMC

ARM

A15

DSP

C66

DDR3LPHY

to

CBASS

www.ti.com System Overview




2 System OverviewThe DDR3L interface consists of the following subsystems:• DDREMIF controller — digital interface, FIFOs, and ECC module• DDR3LPHY — consists of DDR3L PHY macros and system interface logic

Figure 4 shows the interconnect of the sub-modules in the 66AK2Gx SoC.

Figure 4. DDREMIF and DDR3L PHY Subsystems in 66AK2Gx Devices

The ECC block is connected in front of the data and command FIFOs within the DDREMIF controller, asshown in Figure 5. The ECC block enables the Read-Modify-Write (RMW) feature that is not available insome earlier KeyStone™ II devices. The RMW block allows data write that is not aligned to a 32-bitboundary, by first read, the full quanta data from the DDR device merges with the non-aligned data,recalculates ECC, and writes back to DDR. This procedure incurs extra write latency.

Figure 5. ECC Block With RMW in DDREMIF Controller

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System Specifications www.ti.com




3 System SpecificationsTable 1 lists different DDR configurations depending on the required DDR interface for the device.

NOTE: The 4-bit devices are not supported unless the device is used as an ECC device.

Table 1. DDR Configurations for 66AK2Gx-Based Systems

CONFIGURATION DDR WIDTH DDR DEVICES ECC1 16-bit DDR3L with no ECC 2 × 8b –2 16-bit DDR3L with no ECC 1 × 16b –3 32-bit DDR3L with no ECC 4 × 8b –4 32-bit DDR3L with no ECC 2 × 16b –5 32-bit DDR3L with 4-bit ECC 4 × 8b 1 × 4b6 32-bit DDR3L with 4-bit ECC 4 × 8b 1 ×8b (tie-off upper 4-bit)7 32-bit DDR3L with 4-bit ECC 2 × 16b 1 × 4b8 32-bit DDR3L with 4-bit ECC 2 × 16b 1x8b (tie-off upper 4-bit)9 No DDR – –

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DDR 3L Device 0

DDR 3DQS 0p/n

DDR 3D [7 :0 ]

DDR 3RESETz

DDR 3RASz

DDR 3CASz

DDR 3WEz

DDR 3CKE 0

DDR 3CE 0

DDR 3CLKOUT 0p/n

DDR 3A[15 :0 ]

DDR 3BA [2 :0 ]

DQSp /n

DQ [7 :0 ]

RESET

RAS

CAS

WE

CKE

CS

CK

DDR 3A[15 :0]

DDR 3BA [2 :0 ]

DDR 3CE 1

DDR 3CLKOUT 1p/n Device 1

DQSp/n

DQ [7 :0 ]

RESET

RAS

CAS

WE

CKE

CS

CK

DDR 3A[15 :0]

DDR 3BA [2 :0 ]

Device 2

DQSp /n

DQ [7 :0 ]

RESET

RAS

CAS

WE

CKE

CS

CK

DDR 3A[15 :0 ]

DDR 3BA [2 :0 ]

Device 3

DQSp /n

DQ [7 :0 ]

RESET

RAS

CAS

WE

CKE

CS

CK

DDR 3A[15 :0]

DDR 3BA [2 :0 ]

Device ECC

DQSp /n

DQ [3 :0 ]

RESET

RAS

CAS

WE

CKE

CS

CK

DDR 3A [15 :0 ]

DDR 3BA [2 :0 ]

DDR 3DQS 1p/n

DDR 3D [15 :8 ]

DDR 3DQS 1p/n

DDR 3D [23 :16 ]

DDR 3DQS 1p/n

DDR 3D [31 :24 ]

DDR 3CBDQSp/n

3CBDQSp

CBDQSp

DDR 3DQM [3:0 ]

www.ti.com System Specifications




Figure 6 shows an example system interconnection between 66AK2Gx and five 8-bit external devices.

Figure 6. Signal Interconnect of 4 × 8 + 1 × 8 32-bit DDR configuration with ECC

http://www.ti.com


DDR+

ECC

C777C269

R489R23

R24

R857

R890

R891

C236C240

C266 C778

C255R896

FB31

TP154

C202

TP153

TP

155

C598C203

TP126 C227

C557

C209

C208

TP140

TP139

TP136

TP133

TP123

U112

C71

0

TP115

R210

R216

R217

R208

FB27

R51

4R

511

R51

2

R51

3C

258C25

9

C18

7

C17

8

R37

8

R37

9

R37

7

R37

6R784

R38

5R

386

R36

5

R36

6

R814

R815

R498U67

C25

0C

261

U1

R73

7

C17

9

C18

5

C17

2C

182

C177

R36

9

R36

8

C11

3

R26

0

R27

1

R26

9

R28

1

U29

R25

8

R26

8

TP127

RA7

R46

7

R46

6

R46

5

R46

3

R38

8R

387

RA6

R37

3

R328

TP125

TP135

TP131TP143

TP141

C17

0

C17

1

TP

124

R28

6

R29

9

R29

2

C146

R28

7 R301

R856

C206

C21

3

C265

U50

TP159

TP132

R453

R449

R445

R46

4

C231

C224

C264

R427R452

R468

R454

R473

R447R418

R820

R401

R413

R398

R410

R394

R817

U59C784

R86

9

R912

R913

R49

0

R49

1

TP142

R265

C147

R318

R344

C271C278

R478

Y7

R80

4

R450

R80

3

TP145

U56

C225C229

R431

R446

R462R437

R424

R430

R419

R482

R460

R451

R477

R441R436

R421

R432

R823

R816

R422

C795

C794R415

R396

R423

R434

R439

R416

R425

R407

R812

U135

R87

0

U64

C785

U38

R339

U40

R333

U47C53

2

C786

R698R321

R315

R701

U127

C27

7

R48

7

R832

C756

C27

2

C27

3

C67

8

C67

7

R76

1

C66

8

C66

9

R295

R247

R305

R308

R233

R261

R279

R309

R237

R230

R285

R241

C129

R483

R479

R485

U60

C268

R833

U12

2C

274

R47

4C

757

U123C758

C75

9C

610

R21

4

R30

7

R21

2

R25

6

R21

3

C262

U62

C233

C239

C25

4

TP158

C23

8

R47

5R

461

FB26

C603

R443

C605

TP128U52

U49

U45

U39

TP106

U27

R21

5

R20

6

R20

7

R21

1

R20

9

R30

6


System Specifications www.ti.com




Figure 7 shows the DDR3L device placement relative to the 66AK2Gx device on the EVMK2G board.

Figure 7. DDR3L Device Placement near the 66AK2Gx Device on the EVMK2G Board

Figure 8 shows the DDR devices on the EVMK2G.

Figure 8. DDR Devices on the EVMK2G

http://www.ti.com


ddr3A_setup(int ECC_Enable, int DUAL_RANK){

… …

if(ECC_Enable == 0){

read_val = DDR3A_DATX8_4;DDR3A_DATX8_4 = read_val & 0xFFFFFFFE; //Disable ECC byte lane

}… …

if(ECC_Enable==1){

//Enable ECC//0xB0000000: ECC_EN=1, ECC_VERIFY_EN=1, RMW_EN=1//0x50000000: ECC_EN=1, ECC_VERIFY_EN=0, RMW_EN=1DDR3A_ECC_CTRL = 0xB0000000;read_val = DDR3A_ECC_CTRL;if(read_val!=0xB0000000){

GEL_TextOut("\nIncorrect data written to DDR3A_ECC_CTRL..");}

}

www.ti.com Software




4 SoftwareThe processor SDK supports configuration, initialization, and testing on the DDR ECC, for systems usingthe feature.

4.1 InitializationECC and RMW options are controlled by memory mapped registers. Refer to the device datasheet(SPRSP07) for the exact register address and assignment. The RMW feature is always enabled wheneverECC is enabled. The following steps are involved to enable ECC:1. Enable bit[35:32] of the PHY macro (including leveling and training)2. Enable ECC + RMW3. Read back control register and verify ECC+RMW is enabled4. Initialize DDR memory to validate ECC syndrome

NOTE: The entire ECC enabled DDR space must be initialized before any of the ECC memoryregion is used. Otherwise, due to RMW operations, a non-aligned write operation may invokethe DDREMIF to read back an incorrect ECC syndrome and thus cause ECC error.

Figure 9 shows an example GEL script to enable ECC.

Figure 9. GEL Script to Enable ECC and RMW

http://www.ti.com


http://www.ti.com/lit/pdf/SPRSP07

Software www.ti.com




4.2 Verification and DiagnosticsFrequently, it may be required to verify the proper operation of the ECC, especially when the final productis presented to an independent safety compliance assessment body. A simple technique to prove out theproper operation of ECC may be:1. Enable ECC, write a set of data to DDR. The data could be a combination of aligned and non-aligned

bytes.2. Read and verify these data matched to originals.3. Disable the ECC by changing the control register.4. Write a modified data set to the same address, modified means some data has 1 bit errors and some

data has 2 or more bits of errors.5. Reenable ECC.6. Read back these data and compare with original, verify that single bit error counter increased when

accessing single bit modified data, and a kernel panic happened when more than one bit modified datais accessed.

This procedure must be performed to ensure that no other DDR access is present. A real-life randommemory bit error may be generated in a laboratory where the device is running under bombardment ofhigh-energy particles such as a high-energy physics accelerator facility.

4.3 ECC Error HandlingKernels of operating systems typically handle ECC error interrupts. Single-bit errors are automaticallycorrected when the data is presented to the host, however, data stored in the memory is not corrected. Toreduce the probability of another single-bit error from happening in the same quanta block,performsoftware scrubbing where a scrubbing software performs periodic access to ECC-protected DDR space.When a single-bit error occurs, the scrubbing software first reads, and then writes back the correct data sothe memory content is correct. Current K2G Processor SDK Linux® kernel does not perform scrubbing.For a 1-bit ECC error, no direct interrupt will be generated, instead the EMIF can be programmed with athreshold to its ECC Error Count Register. An interrupt will be generated so the host software can re-writememory addresses containing error bits.

The 2-bit ECC will immediately trigger an interrupt to the host, typically causes a kernel panic andsubsequently causes a device reset.

4.4 Processor SDK Software SupportBoth Linux and RTOS branch of the Processor SDK support initialization, verification and error handing ofthe ECC. Table II lists sub-modules in each branch related to ECC functions.

ECC and RMW are enabled by default in both Processor SDK Linux and Processor SDK TI-RTOS tomatch to K2G GP EVM hardware. But can be disabled if not required by customer systems.

Table 2 lists software support for DDR ECC.

Table 2. Software Support for DDR ECC

OPERATIONS DESCRIPTION PROCSDK-RTOS PROCSDK-LinuxEnablement /Initialization Enable data macros, leveling and training GEL file scripts u-boot

Memory Initialization Initialize memory for correct syndrome Yes u-bootKernel Handling –

ScrubbingFrequently scrub memory to correctsingle-bit errors in memory device No (user software) No (user software)

Kernel Handling –Unrecoverable

Cause kernel panic if double-bit error isencountered

Not supported (usersoftware) Kernel Panic

Verification /Diagnostics Utility or example to verify ECC support Example code (user

software) Linux Utility (user software)

http://www.ti.com


www.ti.com Test Data




5 Test DataFor DDR access 8-byte aligned addresses, the ECC is transparently read and verified by the hardwarecontroller. Therefore no impact on latency or memory throughput is expected. Table 3 lists measuredblock data transfers from the C66x L2 memory to the DDR space, with- and without- ECC enabled in thecontroller.

Table 3. Throughput Comparison of DDR ECC With and Without ECC Enabled

TEST SOURCE DESTINATION ACNT BCNT BIT LENGTH THROUGHPUT1 DSP L2 DDR3L 16384 1 131072 98.27%2 DSP L2 DDR3L 32768 1 262144 99.13%3 DSP L2 DDR3L 1 32768 262144 99.19%5 DSP L2 DDR3L 2 32768 524288 99.59%6 DSP L2 DDR3L 4 32768 1048576 99.65%7 DSP L2 DDR3L 8 32768 131072 98.27%

In cases where non-aligned write access made to the DDR, the RMW procedure will be performed, wherethe DDREMIF controller first read the aligned data from the DDR, merge with requested write bytes, re-calculate ECC error correction code, then write to the DDR memory. Latency due to RMW operation isdependent on the background simultaneous access to the DDR, and the DDR command and data FIFO filllevels.

6 Design FilesThe design files for the K2G General Purpose EVM may be found at http://www.ti.com/tool/evmk2gx.

7 Related Documentation

1. Keystone II Architecture DDR3 Memory Controller User's Guide (SPRUHN7)2. Hardware Design Guide for KeyStone II Devices (SPRABV0)3. DDR3 Design Requirements for KeyStone Devices (SPRABI1)4. Advantages of ECC Memory, https://www.pugetsystems.com/labs/articles/Advantages-of-ECC-

Memory-520/5. 66AK2Gx Multicore DSP + ARM KeyStone II System-on-Chip (SoC) Technical Reference Manual

(SPRUHY8)

7.1 TrademarksKeyStone is a trademark of Texas Instruments.Arm is a registered trademark of ARM Limited.Linux is a registered trademark of Linus Torvalds.

http://www.ti.com



http://www.ti.com/lit/pdf/SPRUHN7

http://www.ti.com/lit/pdf/SPRABV0

http://www.ti.com/lit/pdf/SPRABI1

https://www.pugetsystems.com/labs/articles/Advantages-of-ECC-Memory-520/

https://www.pugetsystems.com/labs/articles/Advantages-of-ECC-Memory-520/

http://www.ti.com/lit/pdf/SPRUHY8

About the Author www.ti.com




8 About the AuthorDR. JIAN WANG is a Chip Architect with the Catalog Processor Group. Dr. Wang joined TI in 2006 as aVideo Systems Engineer, working on Davinci family of digital media processors. His recent roles focus onSOC system architecture for machine vision and next-generation industrial applications.

http://www.ti.com


www.ti.com Revision History



Revision History

Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (April 2016) to B Revision .......................................................................................................... Page

• Changed document title to "66AK2Gx" ................................................................................................. 1• Added 66AK2G12 Product Folder ...................................................................................................... 1• Changed EVM Tool Folder to EVMK2G (1GHz version)............................................................................. 1• Changed "at 600 MHz" to "up to 1000 MHz" for both Cortex-A15 and C66x ..................................................... 2• Added MSMC subsystem details........................................................................................................ 2• Changed datasheet URL to 66AK2G12 version (SPRSP07)........................................................................ 9

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ddr ecc to improve memory reliability in 66ak2g2x-based

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