decoder explanation
TRANSCRIPT
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VHDL 4Building blocks of a computer
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VHDL 4
Building blocks of a computer
We will study the building blocks of a computer.
Control units are state machines, which have Flip-flops,
decoders, multiplexers etc.
Beware that , there are usually more than one way todesign the same digital system in VHDL
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A typical
CPU FFs=Flip-flops
A state machine
contains FFs
VHDL 4 : (ver.2b) 3
ALU(state machine)
Control Unit
State machine
I/O control logic
(state machine)
Registers
(FFs)
data-busTransceivers
(bi-directional
buffers )
Memory
Address bus
(latches)
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Use VHDL to make digital system building blocks
1) latch,
2) flipflop with asynchronous reset,
3) flipflop with synchronous reset,
4) tri state buffer,
5) decoder,
6) multiplexer,
7) bi-directional buffer,
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VHDL Exercise 4
1) Latch: when gate=1,
output follows input (level sensitive) 1 entity latch_exis
2 port (gate, in1 : in std_logic;
3 out1 : out std_logic);
4 end latch_ex; 5 architecture latch_ex_archoflatch_exis
6 begin
7 process (gate,in1)
8 begin
9 if (gate= '1') then
10 out1
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Exercise 4.1 on latch: draw q
VHDL 4 : (ver.2b) 6
in1
gate
q
qIn1gate
Latch
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2) Edge-triggered Flip-flop with asyn. reset : reset before clock
statement 1 architecture dff_asyn_archofdff_asynis
2 begin
3 process(clock, reset)
4 begin
5 if (reset= '1') then
6 out1
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Exercise 4.2 on flip-flops:draw qe
VHDL 4 : (ver.2b) 8
CK
D
qe
qeDCK
Edge(50%)
triggered
FF
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Exercise 4.3 on architecturedff_asyn_aWhen will line 3 be executed?
Which is more powerful: clockorreset?
1 architecture dff_asyn_archofdff_asynis
2 begin
3 process(clock, reset)
4 begin
5 if (reset= '1') then
6 out1
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Exercise 4.4 on different flip-flops
What is the difference between level triggered and edge
triggered flip-flops?
**In Xilinx-Foundation all flip-flops are treated as 50%
edge triggered flip-flops. What is the difference between
synchronous reset (syn-reset) flip-flops and
asynchronous reset (asyn-reset) flip-flops?
Discuss the difference between a latch and a flip flop.
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3) Flip-flop with syn. reset: clock before reset statement 1 architecture dff_syn_archofdff_synis
2 begin process(clock,reset)reset can be removed,
4 begin -- but allowed
5 ifclock= '1' and clock'event then
6 if (reset= '1') then
7 out1
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Difference between
Syn. & Asyn. RESET flip-flops (FF)
The order of the statements inside the
process determines Syn. or Asyn. reset
ifclock= '1' and clock'event then
if (reset= '1') then
if (reset= '1') then
q
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4) Tri state buffer: using when-else
(Use capital letter big Z for float, Z is a reserved character)
1 entity tri_exis
2 port (in1, control: in std_logic;
3 out1 : out std_logic); 4 end tri_ex;
5 architecture tri_ex_archoftri_exis
6 begin
7 out1
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A decoder (N bits --> 2N bits)
VHDL 4 : (ver.2b) 14
Picture from: http://www.safesdirect.com/safes/meilink/safes.html
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5) Decoder: using if statements
1 architecture decoder_a of decoder is
2 begin
3 process (in1, in2)
4 begin
5 ifin1 = '0' and in2= '0' then
6 out00
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(contin.)Decoder
15 if in1 = '1' and in2= '0' then
16 out10
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6) Multiplexer (2N bits --> Nbits)
(the reverse of decoder)
1 architecture mux_archofmuxis
2 begin
3 process (in1, in2, ctrl)
4 begin
5 ifctrl= '0' then
6 out1
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Note:7) Bi-directional bus: using data flow
concurrent statements 1 entity inout_exis
2 port (io1, io2: inout std_logic;
3 ctrl : in std_logic);
4 end inout_ex;
5
6 architecture inout_ex_aofinout_exis
7 --signal outbuf, inbuf: std_logic;
8 begin
9 io1
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Exercise 4.5 for Bi-directional bus
Crt=1, io1 follow io2_in
Crt=0, io2 follow io1_in
Plot io1 io2
VHDL 4 : (ver.2b) 19
Io1_in
io1
Io2_in
Io2
ctrl
io1ctrl
io2Io1_inIo2_in
R=10K R=10K
VHDL 4 ( 2b) 20
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Quick revision
You should know how to design
asynchronous , synchronous reset flip-flops
tri state buffers,
Combination logics
decoders,
multiplexers,
bi-directional buffers,
VHDL 4 : (ver.2b) 20
VHDL 4 ( 2b) 21
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Appendix: do variables in processes have memory. (Goodpractice: Initialize variables before use; assign values to variables from
input first) library IEEE;
use IEEE.std_logic_1164.all;
entity test is port (a,reset_v1: in std_logic;
b ,c: out std_logic); end test;
architecture test_arch of test is
begin
label_proc1: process (a,reset_v1)
variable v1 : std_logic;
begin if reset_v1 ='1' then
v1:= not a;
end if;
b