Deepak Kumar SinghEmail: mailtodeepak.k.singh@gmail.com No.4/3, 2nd cross, opp. Ganesha Temple, Thavarekere,Mobile: +91.782.956.9440 Near Bus stop, BTM Layout 1st stage.

Karnataka, Bangalore- 560029 _______________________________________________________________________

Career Objective: To utilize my knowledge and technical skills towards the growth andattainment of the goal of the organization while being flexible, innovative and ASAP driven.

Summary of Qualifications Good understanding of the ASIC and FPGA design flow Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog Very good knowledge in verification methodologies Experience in using industry standard EDA tools for the front-end design and verification

Subject of InterestsLearning effective verification methods in UVM, RTL Design and Verification, Digital system design,CMOS, FPGA, STA, Floor planning, CDC, Perl, Python, C language,System Verilog, Verilog.

Work Experience:Current : Designation: System Engineer (Embedded Department).Company: Jenesys Technology (From July 2015 to April 2016).

Previous:Designation: Software Engineer (Embedded Department).Company: Safran Engineering Services (From Nov 2013 to Feb 2015).

Projects Undertaken

SPI Controller Core - Verification HVL: SystemVerilogEDA Tools: Modelsim, Questa -- Verification Platform

Description: The SPI Controller Core is an interface between wishbone compatible Master Device and SPI interface Slave device. It supports variable length of transfer word and the core can be configured for 1 to 32 bit, 64 & 128 bit. It supports data latching and data transfer at both edges of clock. This core can be configured to connect with 32 slaves. The SPI Clock frequency can be adjusted by configuring desirable value in 32 bit clock divider register. The SPI Core RTL is technology independent and fully synthesizable.

Architected the class based verification environment using SystemVerilog Verified the RTL module using SystemVerilog Generated functional and code coverage for the RTL verification sign-off. Writing script in Perl for regression testing and makefile.

A350XWB Braking Control System

Overview : The A350 XWB is equipped with a nose landing gear (NLG) and two main landing gears (MLG). The Landing Gear System consists of the different systems like Extension/Retraction System, Wheel Steering Control System, Landing Gear Monitoring System and Braking Control System which controls and monitors the landing gear functions.

Braking Control System (BCS) consists of 2 COM-MON modules based on IMA architecture and 2 Remote Braking Control Units (RBCU). Braking IMA COM module is dedicated to the main braking control and monitoring tasks, while Braking IMA MON module is dedicated to the monitoring and to confirm braking control orders. RBCU channel A and channel B compute the braking orders applied on each wheel depending on the braking control orders computed by IMA sides and depending on the wheel skidding.

Technology used : DOORs, RTC,RQM,Rhapsody,CM Synergy, Trace32, Test Case Manager

Role: Writing the test plan for the high level specifications Technical review of the test plan. Preparing the test scripts (python) in Test Case Manager which is a customer specific tool and

executing these test scripts in the target. After the target execution, preparing the Test report. Technical review of the test scripts and results.

Avionics Domain Skills

Guideline : DO178B,DO254Configuration Management Tool : CM SynergyRequirement Management Tool : DOORs

VLSI Domain Skills

HDLs: Verilog and VHDLHVL: System Verilog and PSLVerification Methodologies: Coverage Driven Verification Assertion Based Verification TB Methodology: UVMEDA Tool: Modelsim and ISEDomain: ASIC/FPGA Design Flow, Digital Design methodologiesKnowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis, ABV

Academic Qualification

B.Tech , IMPS College Of Engineering and TechnologyWest Bengal University Of Technology, West Bengal, India Discipline: Electronics and Communication Engineering Percentage:81.20% First ClassYear: June 2012.12th, Sunrise (Eng.Medium), 63.87% 2007.10th, Sunrise (Eng.Medium), 65.33% 2005.Professional Training

June 2013 – November 2013, Maven Silicon, VLSI Design and Training Center, http://www.vlsitraining.com

Achievements Won winners certificates at school level in table tennis, football and various racing events. Played inter school cricket tournament.

VLSI Projects Undertaken

Dual Port RAM – verification

HVL: VerilogEDA Tools: Modelsim, Questa – Verification Platform and ISE

Description: Dual Port RAM is a basic prototype of functioning of RAM, wherein it has a single Data_in and Single Data_out ports. Reading and writing the data can be done simultaneously.

Implemented the Dual Port Ram using Verilog HDL and Verilog. Architected the class based verification environment using Verilog. Verified the RTL module using Verilog Generated functional and code coverage for the RTL verification sign-off

Router 1x3 – RTL design and Verification

HDL: VerilogHVL: SystemVerilog EDA Tools: Modelsim, Questa -- Verification Platform and ISE

Description: The router accepts data packets on a single 8-bit port called data and routes the packets to one of the three output channels, channel0, channel1 and channel2.

Architected the design and described the functionality using Verilog HDL. Architected the class based verification environment using system Verilog Verified the RTL model using System Verilog. Generated functional and code coverage for the RTL verification sign-off Synthesized the design

Personal Profile

Name : DEEPAK KUMAR SINGH.Father’s Name : Mr. PRAHLAD SINGH.Date of Birth : Nov 9, 1989Sex : Male.Marital Status : Single.Passport No : M8555107Nationality : Indian.Languages Known : English, Hindi and Bengali.I here by declare that the information given herewith is correct to my knowledge and I will responsible for any discrepancy.

Place: Bangalore DEEPAK KUMAR SINGH