defect isolation tools accelerate the failure analysis process

International Symposium for Testing and Failure Analysis, November 3-7, 2013

Defect Isolation Tools Accelerate the Failure Analysis Process

Adam Winterstrom*, Kevin Meehan*, Ralph Sanchez and Rich Ackerman

*International Rectifier Teseda Corporation

Temecula, CA, USA Portland, OR, USA

Introduction

This paper presents case studies that highlight the use of

new scan technologies and techniques to quickly test,

diagnose, localize and isolate the root cause of the defects

demonstrating that the solution meets the rapid and

constant changing demands of industry. Cases include; a)

a device that is seemingly passing functional test, but not

scan test with emission, b) a device with emission

requiring resolution to its location and c) a device having a

timing issue that does not have emission.

Traditional Techniques Meets Scan

The devices diagnosed were primarily designed as a single

chip solution for complete inverter controlled appliance

motor control applications. It consists of a collection of

control elements, motion peripherals, a dedicated motion

control sequencer and dual port RAM to map internal

signal nodes.

Traditional techniques to locate physical defects in digital

integrated circuits include static observation techniques

such as emissions microscopy and static bias laser

stimulation techniques. These include Optical Beam

Induced Resistance Change (OBIRCH), Voltage Bias

voltage sensing Amplifier (VBA), and Thermally Induced

Voltage Alteration (TIVA). With continued growth in

diagnostic tools and applications using scan technology,

new tools are being added to enhance failure analysis

laboratories methodologies [1] [2]. Both hardware and

software scan diagnostic tools, together with equipment

commonly used in failure analysis laboratories were used

to diagnose the motor control devices.

The new scan diagnosis methods were incorporated as part

of the overall diagnosis flow depicted by the methodology

depicted in Figure 1. After initial inspection the devices,

whether field returns or production test failures, are tested

to recreate and capture all the failures. The failures,

captured as mismatches in the scan chains, are mapped

against the physical design in the diagnostic software. The

scan based diagnostic software physically identifies

mismatching scan cells resulting from ATPG test by

mapping them with the XY coordinates in reference to the

device. The logic observed by these scan cells can be

traced to localize the defect. Logic cone and pruning

techniques in the software are used to isolate the location

of the failure which in turn is the suspect defect.

Confirmation of the suspects are determined through both

nondestructive and destructive means in failure analysis.

The compact scan test hardware is easily placed within the

chambers of FA equipment, such as XIVA and photo-

emission equipment. Once situated in the chamber, the

test hardware stimulates the device for emission. The

diagnostic software was also used in finding the physical

location of the actual emission as well as aiding the FA

engineer in determining the best placement for FIB points.

FA destructive techniques for the device become a lower

risk with higher success in revealing the actual root cause.

This approach quickly localized the defect and established

an enhanced FA methodology to isolate the root cause for

final confirmation. The time reduction of localization and

isolation was dramatically reduced from what is typically

several months to a number of days.

External Visual Inspection

All the samples were subject to initial nondestructive

failure analysis techniques, such as X-RAY and C-SAM

inspections, to examine the interior details of the devices.

X-RAY radiography was used to detect any wire sweep

and other wire bond problems, die attach voids, package

voids and cracks. C-Mode Scanning Acoustic Microscopy

(C-SAM) was used to detect any delaminations between

package interfaces such as Plastic-to-Leadframe, Plastic-

to-Die, Plastic-to-Die Attach, Die Attach Voids and

Internal Cracks. No anomalies were detected in either of

these inspections.

Sample 1 Diagnosis

Electrical Verification and Test

In the first sample examined, initial verification confirmed

normal leakages and switching during the functional

testing in the device. However running the ATPG test on

the hardware system revealed scan test failures, as

summarized in Figure 2. 97 scan cell failures at room

temperature and 135 scan cell failures at 70°C were

captured. In both tests, at different temperatures, the

failures were captured in the same scan cells, showing a

consistency in the defect behavior.


2

Figure 1. Failure Analysis Flow

S/N IQCC IQBS1,2,3 BV/IDSS

M1-M6

Functional

Switching

Engineering

Test System

Failing unit OK OK OK OK Fails scan test

and related

functional test

Figure 2. Initial Device Inspection and Test Summary

Figure 3. Scan Debug Software highlights failing register

16-bit register with

scan highlighting

mismatching scan

cells in ATPG test


3

Scan Test Debug

The scan debug software drives the hardware system and

starts the analysis process with the failing device by

highlighting the logical representation of the scanned

register reporting failure by way of instance names. Figure

3 illustrates the summary of the scan cell mismatches with

their instance name, i.e., pwm_cnt_32x_reg[0-15]. The

test results indicate that 14 of the 16 bits of a register are

mismatching. The proximity of the register identifies the

logical register index numbers, 0 - 15, and the correlated

index numbers of the scan cell index numbers of the scan

chain the register is embedded in. The scan debug

software provides the pattern and statistical data such as

number of times the mismatch occurs in each scan cell of

the register.

Given this information, it is surmised that the logical

information provided in the scan debug software results

that the physical location of the register scan cells are in

close proximity. From the results of the ATPG testing, it

can be concluded that the scan cells are working properly

due to the fact that the first pattern is typically the integrity

test that checks the connectivity of the scan chain. The

mismatching values occur later in the ATPG test after the

initial integrity test. Thus the scan cells are correctly

reporting the defect behavior in the logic of the design.

Physical Correlation and Localization

The test results were further analyzed in the physical

environment of the diagnostic software. The scan debug

software test results were directly read into the physical

diagnostic software to cross correlate the logical failure

data and map it against the physical design, Figure 4.

The tracing of logic was done within the diagnostic

software to further get a fix on the defect candidate with

the XY coordinates. This established the area localization

of the defect.

Cone Tracing

Knowing that the ATPG integrity test pattern executes and

returns results correctly indicates proper functionality of

the scan chain operation. As such, the ATPG test also

indicates proper shift and capture of the scan data.

Further, high confidence that the scan enable and clock are

operational is assessed.

By tracing from the d inputs of the mismatching scan cells,

cone tracing for each of scan cells can reveal commonality

of nets and cells in their paths. After tracing into a couple

of the mismatching scan cells, a common net (n_401) is

input to the driving cell (an AND gate) for each scan cell.

Figure 5 illustrates this finding (the small component cells

are the AND gates and the highlighted trace is net n_401.

The findings of the cone trace effectively leads to the

convergence of a single net (n_369) and cell (a NAND

gate), Figure 6.

Photo Emission Analysis

To confirm the finding, the device, hardware system and

fixture were set up in the photoemission chamber to

stimulate the device for emission, Figure 7.

Figure 4. Logical to Physical Cross Correlation


4

Figure 5. Physical diagnostic software for cone tracing common nets/cells

Figure 6. Physical diagnostic software for convergence to the suspect net/cell

Figure 7. Photoemission Set Up

Taking the failing pattern of the device, the scan debug

software enabled the pausing of several failing vectors for

defect stimulus and at each vector two abnormal emission

sites appeared. These two emissions could be identified to

logic traced in the diagnostic software, Figure 8. The

emission sites determined by the data were identified as;

Emission site 1 location (2493, 1307.8)

Cell macro name = nand4i_adn_4

Cell output net = x = _n_369

Emission site 2 location (2584, 1249.9)

Cell maro name = adfull_adn_apr_2

Cell output net = co = _21bmod_u_mod2_3phsvpwm_01f

Hardware Test

System


5

Figure 8. Emission site determination with the diagnostic software for coordiantes

Scan Test Pause

(Cycle) Location

Control unit Failing unit

Pad 1

(_n_369)

Pad 2

co

Pad 1

(_n_369)

Pad 2

co

26518 1 0 0 0

46408 1 0 1 0

55248 1 0 1 0

187848 1 0 0 0

Pad 1 = emission site 1 – output net - fib pad location (2489.35, 1288.8)

Pad 2 = emission site 2 – output net – fib pad location (2542.5, 1235.05)

Figure 9. Probing Results – State of node at different scan test pause locations

Focused Ion Beam (FIB) Analysis

With XY coordinates determined, FIB pads were made at

the output signal of the cells with emission sites. The

emission site cells (Site 1 = nand4i_adn_4 and Site 2 =

adfull_adn_apr_2) are highlighted, Figure 8, in the

diagnostic software as well as the output net path for the

cells. Repeating the ATPG test for stimulus in the

photoemission procedure, the scan test was paused at

specific cycles before the capture point of the scan pattern.

Doing so keeps the scanned input pattern constantly

propagated through the logic to stimulate the defect for

emission. Measurements of the logic states of the block

outputs were taken, reported in Figure 9. It was confirmed

that the nand_4i_adn_4 cell had the incorrect logic value.

The input B of nand4i_adn_4 was resistively shorted to

Vdd which would not allow input B to be pulled down to

VSS. This behavior ultimately resulted in mismatches that

were captured in the scan cells.


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Photoemission Analysis Confirmation

The device sample was delayered down to metal 1 and

photoemission was performed at high magnification to

determine the precise location of the emission leakage,

Figure 10.

Figure 10. Photoemission at Metal 1

Overlay software was used to determine emission site

location relative to gate poly layout, Figure 11.

Figure 11. Overlay software on the emission site

TEM Analysis

The device sample was then prepared for planar

Transmission Electron Microscope, TEM, inspection by

thinning the device to a very thin sheet. TEM inspection

revealed residual silicide causing a leakage path at the

emission site location, Figure 12.

Energy dispersive X-ray Spectroscopy, EDS, analysis, was

performed to identify the elemental composition of the

small area of interest in the device sample and confirmed

residuals of Titanium (Ti) Silicide at the leakage location,

Figure 13.

Figure 12. Overlay software on the emission site


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Figure 13. EDS Analysis confirms Ti Residuals

Sample 2 Diagnosis

Applying the Flow to Confirm Emission

In the case of the sample 2, using the same flow for initial

testing and analyzing the results, the diagnostic software

was used determine the exact location of the emission (as

opposed to isolating the defect first then confirming with

emission as shown in the diagnosis of sample 1). Using

the same photoemission setup as before, Figure 7, the

hardware system provided the stimulus to achieve the

emission.

Figure 14 illustrates the correlation between the

photoemission analysis and the diagnostic software XY

coordinate correlation. The emission site location matches

a Vdd-to-input short observed during probing. Residual

silicide type defect in metal layer 3 also corresponds to the

location as shown in Figure 15.

Figure 14. Logical to Physical Cross Correlation

Figure 15. M3 Layer with the Emission Site Location


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Sample 3 Diagnosis

Dianosis of a Timing Issue Without Emission

Sample 3 was a case in which no emission occured during

the photoemission step of the flow. The inital steps of the

flow for inspection and testing, as in the other previous

samples, were again performed. The test results from this

device isolated a segment of the scan chain that was failing

with 7947 mismatches. The mismatches were within a

constant range of scan cells in the scan chain, scan cell

index 2169 through 2200. In looking at the failing scan

results, the behavior of the mismatching values captured

were unlike a stuck-at behavior. The captured results from

the propagated values of the shifted stimulus pattern were

inexplicable when taking into consideration the logic paths

leading to the capturing scan cells. What would be

expilicable for a stuck at value given the stimulus was not

being captured.

Taking a closer look at the shift operation of the test data

reveals what appears to be a shoot-thru type effect on the

captured results of the mismatching segment of the scan

chain, Figure 16. Tracing the scan chain in the diagnostic

Figure 16. Expect and Actual Results Show A "Shoot-thru" Effect

Figure 17. Buffered Clock Tree To Mismatching Scan Chain Segment


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Figure 18. Delay in Clock Buffer

software revealed lock up latches within the mismatching

scan cell segment of the chain, Figure 17.

The initial suspect was a narrow path between nets

sysclk2x_L6_N1, the buffered clock to the scan cells, and

sysclk2x_L5_N1, the signal feeding the buffer. However,

no visible evidence could be seen. When the

sysclk2x_L6_N1 clock further traced, it was discovered

that clock buffering distribution had clock tree segments

going to scan cells bound between the lock up latches. The

five different sub-trees of the clock going to the scan cells

also have an enable to control the clock pulse for capture.

With probe points now placed on the driving buffer output

of suspect sysclk2x_L6_N1 clock net path, the clock

waveform revealed to have a 20ns delay from the source

clock input, Figure 17. sysclk2x_L7_N1 is the buffered

sysclk2x_L6_N1, which is then in turn gated several times

with independent enables. Thus it can be explained how

the delayed edge of the clock affects not only capturing of

data, but also the shifting effect of the captured data. The

input shift data seems to be correct since the mismatching

scan cells (after capture) are near the beginning of the

scan chain. Hence, the effect of the defect occurs during

the time of capture and transistion into the shift operation

of the scan chain.

The driving buffer of sysclk2x_L6_N1 was then fibbed for

a probe point between the two adjacent inverters of the

buffer, Figure 18. The input to the buffer,

sysclk2x_L5_N1, shows no significant difference between

the contol (good) device and the failing device. However,

comparing and overlapping the control and failure

waveforms after the first inverter of the buffer to the input

of the buffer, sysclk2x_L5_N1, it was here that clearly

determined that the output of the first inverter was the

source of the delay. The delay is then propagated to the

output of the buffer and subsequently to the mismatching

scan cells. The delays measured at the probed points are

as follows;

Technique Differentiation

These scan techniques present a different approach for the

failue analyis lab. Defect isolation is kept in a physical

environment where analyis is performed on the phsical

layout of the design. All data is in reference to the

physical views of the device. The algorithms are

interactive search techniques. The effort is performed

totally independent of simulation and mandatory design

modeling providing the autonomy needed for fast and

complete “confirmation” of the defect. Most importantly,

the presented techniques enable the diagnosing engineer to

rationalize to the root cause.

S/N net Ton_delay

(ns)

Toff_delay

(ns) Control sysclk2x_L5_N1 37.23 38.1

sysclk2x_L6_N1 37.54 38.59 Failure sysclk2x_L5_N1 38.29 38.65

sysclk2x_L6_N1 59.09 106.6


10

Summary

The case studies presented concluded with successful

completion of finding root cause of the defect. The first of

the three cases included defect islolation with the new

methodology with FA confirmation using emission

techniques. The second sample demonstrated the usage of

parts of the flow to confirm the exact location of the

emission. The third and final sample uses the flow to find

a timing issue in the case where no emission is achieved.

The diagnosis time for each of the three devices was

within a period of one to three days per device. The

confirmation stage of the defect is now the longest lead

time of the dianosis process.

Product lines are now introducing more and more devices

with scan and mixed mode operations. Along with this is

having the need for a scan diagnosis environment that is

not only contributing, but is also non-intrusive to the FA

flow.

The importance of having complete failure data from scan

testing done on the device rather than just typical pass/fail

results from production test provided insight on the defect

behavior of the device when analyzed and debugged. The

hardware system also played a dual role when it was

configured within the chamber of photo emission

equipment to stimulate the defect for emission. Localizing

failure candidates in real-time with diagnostic software on

the front end of the FA flow and then probing for the

defect proved to be an efficient manner to which root

cause could be found. The correlation of the emission sites

with the localized areas in the early procedure gave way

for the FIB and TEM efforts, all of which contributed

towards establishing the new diagnostic flow.

Acknowledgements

The authors wish to extend thanks to the EAG lab for their

fine efforts in the TEM analysis which was a contributing

factor towards confirming root cause.

References

[1] Frost, Jack, John Raykowski, “A Standards-based,

Tester Independent Tool for Silicon Diagnosis and Volume

Yield Improvement”, Proceedings IEEE Int. Test Conf.,

2010.

[2] Staab, Don, Rich Ackerman, Ralph Sanchez, 2010. "A

Change in Methodology Accelerates the Isolation in Root

Cause of Defects for Improving Yield and Lowering

Costs", Proceedings IEEE Int. Test Conf., 2010.

[3] Ackerman, Rich, John Morris, 2010. “Scan Diagnostic

Support With IG-XL”, Teradyne Users Group.

[4] Hook, Terence B., Randy W. Mann and Edward J.

Nowak, "Titanium Silicide/Silicon Nonohmic Contact

Resistance for NFET's, PFET's, Diffused Resistors, and

NPN's in a CiCMOS Technology", IEEE Transactions n

Electronic Devices, Vol. 42, No. 4, April 1995.

defect isolation tools accelerate the failure analysis process

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