del manual

KJ College of Engg. & Management Research, Pisoli, Pune DEL Manual

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ASSIGNMENT No: 1

Title of Assignment: T.T.L Characteristics (Study and Write up only).

Relevant Theory:

Transistor–Transistor Logic (TTL) is a class of digital circuits built from bipolar

junction transistors (BJT), and resistors. It is called transistor–transistor logic because

both the logic gating function (e.g., AND) and the amplifying function are performed by

transistors (contrast this with RTL and DTL). It is notable for being a widespread

integrated circuit (IC) family used in many applications such as computers, industrial

controls, test equipment and instrumentation, consumer electronics, synthesizers, etc.

Because of the wide use of this logic family, signal inputs and outputs of electronic

equipment may be called "TTL" inputs or outputs, signifying compatibility with the

voltage levels used.

Comparison with other logic families

Generally, TTL devices consume more power than an equivalent CMOS device at rest,

but power consumption does not increase with clock speed as rapidly as for CMOS

devices. Compared to contemporary ECL circuits, TTL uses less power and has easier

design rules, but is typically slower; designers can combine ECL and TTL devices in the

same system to achieve best overall performance and economy. TTL was less sensitive to

damage from electrostatic discharge than early CMOS devices.

Due to the output structure of TTL devices, the output impedance is asymmetrical

between the high and low state, making them unsuitable for driving transmission lines.

This is usually solved by buffering the outputs with special line driver devices where

signals need to be sent through cables. ECL, by virtue of its symmetric output structure,

doesn't have this drawback.

Several manufacturers now supply CMOS logic equivalents with TTL compatible input

and output levels, usually bearing part numbers similar to the equivalent TTL component

and with the same pin-out diagrams.

Now-a-days digital integrated circuits are most commonly used in modern digital systems.

The most of the digital circuits are constructed in single chip, which are referred to as

Integrated Circuits (IC).

A group of compatible ICs with the same logic levels and supply voltages

for performing various logic functions have been fabricated using a specific circuit

configuration, which is referred to as a Logic Family.

There are two types of Logic Families, which are as follows –


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1) Bipolar Logic Family

2) Unipolar Logic Family

Bipolar Logic Families: - The main elements of a bipolar

IC are resistors, diodes (which are also capacitors) and

transistors. Basically there are two types of operations in

bipolar ICs:

a) Saturated, and

b) Non-saturated

The saturated bipolar logic families are:

Resistor-transistor logic (RTL)

Direct-coupled transistor logic (DCTL)

Integrated-injection logic (I2L)

Diode-transistor logic (DTL)

High-threshold logic (HTL) and

Transistor-transistor logic (TTL)

The non-saturated bipolar logic families are:

Schottky TTL, and

Emitter-coupled logic (ECL)

Unipolar Logic Families: - MOS devices are unipolar

devices and only MOSFETs are employed in MOS logic

circuits. The MOS logic families are:

a) PMOS

b) NMOS, and

c) CMOS

Characteristics of Digital ICs: We know that there are various logic families. The

selection of logical families for the application is based on its characteristics, and hence it

is necessary to study the characteristics of digital ICs. The various parameters of digital

ICs used to compare their performance are:

1. Speed of operation

2. Power dissipation

3. Figure of merit

4. Fan-out

5. Fan-in


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6. Current and voltage parameters

7. Noise immunity

8. Operating temperature range

9. Power supply requirements

10. Propagation Delay

11. Current Sinking

12. Current Sinking

13. Loading Factor

Speed of operation: It is one of the important parameters of digital ICs. Speed of

operation of digital ICs should be high. The speed of a digital circuit is specified in terms

of the propagation delay time. The input and output waveforms of a logic gate are shown

in Fig.1.

50%

Input

Output

50%

Fig.1 Input and Output waveforms to define propagation delay time

The propagation delay time of the logic gate is the average of propagation delay time

from high state to low state and propagation delay time from low to high state.

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t+t=t

PLHPHLP

The delay times are measured between 50 percent voltage levels of input and output

waveforms. There are two delay times:

tPHL: It is the delay time measured, when output changes from high to low state.

tPLH: It is the delay time measured, when output changes from low to high state.

The propagation delay between input and output should be as minimum as possible so that the

operating speed of IC is high.

Power Dissipation: We know that every electronic circuit requires amount of electric

power. Power dissipation is the amount of power dissipated in an IC. It is determined by

the current ICC, that it draws from the VCC supply, and is given by VCC X ICC. ICC is the

average value of ICC(0) and ICC(1). This power is specified in milliwatts.

TpHL TpLH


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Figure of Merit: The figure of merit of a digital IC is defined as the product of speed and

power. The speed is specified in terms of propagation delay time expressed in

nanoseconds.

Figure of merit = propagation delay time (ns) X power (mW)

It is specified in pico joules (ns X mW = pJ) A low value of speed-power product is desirable. In a digital circuit, if it is desired to have high

speed, i.e. low propagation delay, then there is a corresponding increase in the power dissipation

and vice-versa.

Fan-Out: This is the number of similar gates, which can be driven by a gate. High fan-

out is advantageous because it reduces the need for additional drivers to drive more gates.

Consider the Fig. 2.

N number

of load

gates

Fig. 2

The driver gate drives the N gate (N is fan-out). If more than one N gates are connected

to a load, the current supply by the driver gate is not sufficient to drive the gates or the

current sink by the driver gate is more than the rating of the driver gate and gate may be

damaged.

Using the fan-out of a logic family we can calculate the current component.

Fan-out = minimum of {IL

OL

IH

OH

I

I,

I

I}


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Fan-In: Number of inputs are connected to gate, which is known as fan-in of the gate.

For two inputs gate, fan-in is two and for four inputs gate, fan-in is four.

Current and Voltage Parameters: The following currents and voltages are specified

which are very useful in the design of digital systems.

High-level input voltage, VIH: This is the minimum input voltage, which is recognized

by the gate as logic 1.

Low-level input voltage, VIL: This is the maximum input voltage, which is recognized by

the gate as logic 0.

High-level output voltage, VOH: This is the minimum voltage available at the output

corresponding to logic 1.

Low-level output voltage, VOL: This is the maximum voltage available at the output

corresponding to logic 0.

High-level input current, IIH: This is the minimum current, which must be supplied by a

driving source corresponding to 1 level voltage.

Low-level input current, IIL: This is the minimum current, which must be supplied by a

driving source corresponding to 0 level voltage.

High-level output current, IOH: This is the maximum current, which the gate can sink in

1 level.

Low-level output current, IOL: This is the maximum current, which the gate can sink in 0

level.

High-level supply current, ICC (1): This is the supply current when the output of the gate

is at logic 1.

Low-level supply current, ICC (0): This is the supply current when the output of the gate

is at logic 0.

The current directions are illustrated in Fig. 3.

Fig. 3 A gate with current directions marked

Noise Immunity: The circuit‘s ability to tolerate noise signals without causing spurious

changes in the output voltage is called as Noise Immunity.

To avoid noise problem voltage level VIH(min) is kept a few fractions of voltages

below VOH(min) and voltage level VIL(max) is kept above VOL(max) at the design time.

IIL

IIH

IoL

IoH


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Fig. 4

Noise Margin: A quantitative measure of noise immunity is known as noise margin.

* DC Noise Margin:

1. Low-level noise margin (NML)- The difference between VIL and VOL i.e. VIL -

VOL is known as low-level noise margin.

NML = VIL - VOL = 0.8 - 0.4 = 400mV

2. High-level noise margin (NMH)- The difference between VOH and VIH i.e. VOH –

VIH is known as high-level noise margin.

NMH = VOH – VIH = 2.4 – 2 = 400mV

Operating Temperature: The temperature range in which an IC functions properly must

be known. The accepted temperature ranges are: 0 to +70o C for consumer and industrial

applications and -55o C to +125

o C for military purposes.

Power Supply Requirements: The supply voltage (s) and the amount of power required

by an IC are important characteristics required to choose the proper power supply.

Propagation Delay :- It is time required by gate to give output when input is applied.

Always in ns.

Current Sinking :- The current supply by driver gate to load gate is called as sinking

current.

VOH

VIH

VOL

VIL VNL

VNH


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When driver gate output is low, then the EB junction of loaded gate become forward bias,

and the VCC of load gate passes current through T3 of driver gate this called as sink

current.

Current Sourcing :- Source current is a current supply by driver gate to load gate.

When driver gate output is high the current is supplied to the load gate is a sourcing

current.

Standard TTL logic levels Operating conditions: V CC 4.75 V min. to 5.25 V max. 74XX chips

PARAMETER CONDITIONS MIN MAX UNITS

Logic 1 input voltage

VCC = min 2.0 -- V

Logic 0 input voltage

VCC = min -- 0.8 V

Logic 1 output voltage

VCC = min - - Iout = -0.4 mA

2.4 -- V

Logic 0 output voltage

VCC = min - - Iout = 16 mA

-- 0.4 V

Logic 1 input current

VCC = min - - Vin = 2.4 V

-- 0.04 mA


V CC = min - - Vin = 5.5 V

-- 1 mA


VCC = min - - V in = 0.4 V

-- - 1.6 mA


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What does it all mean?

VOH Min = Output voltage high minimum with up to 0.4 mA load A good chip is guaranteed to output a minimum of 2.4 V logic high up to 0.4 mA

VOL Max = Output voltage low maximum with up to 16 mA load A good chip is guaranteed to output a maximum of 0.4 volts up to 16 mA

VIH Min = Input voltage high minimum 2.0 V A good chip will recognize 2.0 V or greater as a logic high and draw no more than 0.04 mA input current.

VIL Min = Input voltage low maximum 0.8 V A good chip will recognize 0.8 V or less as a logic low and draw no more than 1.6 mA input current.

Fan out

For a logic high, a good chip will source 0.4 mA and maintain a minimum of 2.4 V For a logic high, the input will draw no more than 0.04 mA This means that a high output of a good chip will drive 10 inputs high.

For a logic low, a good chip will sink 16 mA and hold the voltage at 0.4 V maximum. For a logic low, the input will draw no more than 1.6 mA This means that a low output of a good chip will drive 10 inputs low.

This is what is meant by a Fan Out of 10. Any Standard TTL chip that does not meet these specifications is

defective and should be replaced.

Noise Margin

Notice the 400 mV difference between the specified output voltage of a TTL chip and the input voltage required to recognize a logic level. This 400 mV difference provides a margin such that noise added to the signal does not cause errors. An output voltage with


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up to 400 mV peak of noise added will still provide a valid logic level to the input of the next stage.

7400 series TTL IC's: 7400...7449

7400

Quad 2-input NAND gates.

+---+--+---+ +---+---*---+ __

1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB

1B |2 13| 4B +===+===*===+

/1Y |3 12| 4A | 0 | 0 | 1 |

2A |4 7400 11| /4Y | 0 | 1 | 1 |

2B |5 10| 3B | 1 | 0 | 1 |

/2Y |6 9| 3A | 1 | 1 | 0 |

GND |7 8| /3Y +---+---*---+

+----------+

Positive Logic

__

Y = AB

Equivalent Chips

SN5400 (J)

SN54H00 (J)

SN54L00 (J)


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SN54LS00 (J,W)

SN54S00 (J,W)

SN7400 (J,N)

SN74H00 (J,N)

SN74L00 (J,N)

SN74LS00 (J,N)

SN47S00 (J,N)

7401

Quad 2-input open-collector NAND gates. +---+--+---+ +---+---*---+ __

/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = AB

1A |2 13| /4Y +===+===*===+

1B |3 12| 4B | 0 | 0 | Z |

/2Y |4 7401 11| 4A | 0 | 1 | Z |

2A |5 10| /3Y | 1 | 0 | Z |

2B |6 9| 3B | 1 | 1 | 0 |

GND |7 8| 3A +---+---*---+

+----------+

7402

Quad 2-input NOR gates. +---+--+---+ +---+---*---+ ___

/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = A+B

1A |2 13| /4Y +===+===*===+

1B |3 12| 4B | 0 | 0 | 1 |

/2Y |4 7402 11| 4A | 0 | 1 | 0 |

2A |5 10| /3Y | 1 | 0 | 0 |

2B |6 9| 3B | 1 | 1 | 0 |

GND |7 8| 3A +---+---*---+

+----------+

7403

Quad 2-input open-collector NAND gates. +---+--+---+ +---+---*---+ __

1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB

1B |2 13| 4B +===+===*===+

/1Y |3 12| 4A | 0 | 0 | Z |

2A |4 7403 11| /4Y | 0 | 1 | Z |

2B |5 10| 3B | 1 | 0 | Z |

/2Y |6 9| 3A | 1 | 1 | 0 |

GND |7 8| /3Y +---+---*---+

+----------+

7404

Hex inverters.


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+---+--+---+ +---*---+ _

1A |1 +--+ 14| VCC | A |/Y | /Y = A

/1Y |2 13| 6A +===*===+

2A |3 12| /6Y | 0 | 1 |

/2Y |4 7404 11| 5A | 1 | 0 |

3A |5 10| /5Y +---*---+

/3Y |6 9| 4A

GND |7 8| /4Y

+----------+

Positive Logic

_

Y = A

Equivalent Chips

SN5404 (J)

SN54H04 (J)

SN54L04 (J)

SN54LS04 (J,W)

SN54S04 (J,W)

SN7404 (J,N)

SN74H04 (J,N)

SN74L04 (J,N)

SN74LS04 (J,N)

SN47S04 (J,N)


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7405

Hex open-collector inverters. +---+--+---+ +---*---+ _

1A |1 +--+ 14| VCC | A |/Y | /Y = A

/1Y |2 13| 6A +===*===+

2A |3 12| /6Y | 0 | Z |

/2Y |4 7405 11| 5A | 1 | 0 |

3A |5 10| /5Y +---*---+

/3Y |6 9| 4A

GND |7 8| /4Y

+----------+

7406

Hex open-collector high-voltage inverters.

Maximum output voltage is 30V. +---+--+---+ +---*---+ _

1A |1 +--+ 14| VCC | A |/Y | /Y = A

/1Y |2 13| 6A +===*===+

2A |3 12| /6Y | 0 | Z |

/2Y |4 7406 11| 5A | 1 | 0 |

3A |5 10| /5Y +---*---+

/3Y |6 9| 4A

GND |7 8| /4Y

+----------+

7407

Hex open-collector high-voltage buffers.

Maximum output voltage is 30V. +---+--+---+ +---*---+

1A |1 +--+ 14| VCC | A | Y | Y = A

1Y |2 13| 6A +===*===+

2A |3 12| 6Y | 0 | 0 |

2Y |4 7407 11| 5A | 1 | Z |

3A |5 10| 5Y +---*---+

3Y |6 9| 4A

GND |7 8| 4Y

+----------+

7408

Quad 2-input AND gates.


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+---+--+---+ +---+---*---+

1A |1 +--+ 14| VCC | A | B | Y | Y = AB

1B |2 13| 4B +===+===*===+

1Y |3 12| 4A | 0 | 0 | 0 |

2A |4 7408 11| 4Y | 0 | 1 | 0 |

2B |5 10| 3B | 1 | 0 | 0 |

2Y |6 9| 3A | 1 | 1 | 1 |

GND |7 8| 3Y +---+---*---+

+----------+

Positive Logic

Y = AB

7409

Quad 2-input open-collector AND gates. +---+--+---+ +---+---*---+

1A |1 +--+ 14| VCC | A | B | Y | Y = AB

1B |2 13| 4B +===+===*===+

1Y |3 12| 4A | 0 | 0 | 0 |

2A |4 7409 11| 4Y | 0 | 1 | 0 |

2B |5 10| 3B | 1 | 0 | 0 |

2Y |6 9| 3A | 1 | 1 | Z |

GND |7 8| 3Y +---+---*---+

+----------+

7410

Triple 3-input NAND gates.


14

+---+--+---+ +---+---+---*---+ ___

1A |1 +--+ 14| VCC | A | B | C |/Y | /Y = ABC

1B |2 13| 1C +===+===+===*===+

2A |3 12| /1Y | 0 | X | X | 1 |

2B |4 7410 11| 3C | 1 | 0 | X | 1 |

2C |5 10| 3B | 1 | 1 | 0 | 1 |

/2Y |6 9| 3A | 1 | 1 | 1 | 0 |

GND |7 8| /3Y +---+---+---*---+

+----------+

Positive Logic

___

Y = ABC

7411

Triple 3-input AND gates. +---+--+---+ +---+---+---*---+

1A |1 +--+ 14| VCC | A | B | C | Y | Y = ABC

1B |2 13| 1C +===+===+===*===+

2A |3 12| 1Y | 0 | X | X | 0 |

2B |4 7411 11| 3C | 1 | 0 | X | 0 |

2C |5 10| 3B | 1 | 1 | 0 | 0 |

2Y |6 9| 3A | 1 | 1 | 1 | 1 |

GND |7 8| 3Y +---+---+---*---+

+----------+

7412

Triple 3-input open-collector NAND gates.


15

+---+--+---+ +---+---+---*---+ ___

1A |1 +--+ 14| VCC | A | B | C |/Y | /Y = ABC

1B |2 13| 1C +===+===+===*===+

2A |3 12| /1Y | 0 | X | X | Z |

2B |4 7410 11| 3C | 1 | 0 | X | Z |

2C |5 10| 3B | 1 | 1 | 0 | Z |

/2Y |6 9| 3A | 1 | 1 | 1 | 0 |

GND |7 8| /3Y +---+---+---*---+

+----------+

7413

Dual 4-input NAND gates with schmitt-trigger inputs.

0.8V typical input hysteresis at VCC=+5V. +---+--+---+ +---+---+---+---*---+ ____

1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD

1B |2 13| 2D +===+===+===+===*===+

|3 12| 2C | 0 | X | X | X | 1 |

1C |4 7413 11| | 1 | 0 | X | X | 1 |

1D |5 10| 2B | 1 | 1 | 0 | X | 1 |

/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |

GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 |

+----------+ +---+---+---+---*---+

7414

Hex inverters with schmitt-trigger inputs.

0.8V typical input hysteresis at VCC=+5V. +---+--+---+ +---*---+ _

1A |1 +--+ 14| VCC | A |/Y | /Y = A

/1Y |2 13| 6A +===*===+

2A |3 12| /6Y | 0 | 1 |

/2Y |4 7414 11| 5A | 1 | 0 |

3A |5 10| /5Y +---*---+

/3Y |6 9| 4A

GND |7 8| /4Y

+----------+

7415

Triple 3-input open-collector AND gates. +---+--+---+ +---+---+---*---+

1A |1 +--+ 14| VCC | A | B | C | Y | Y = ABC

1B |2 13| 1C +===+===+===*===+

2A |3 12| 1Y | 0 | X | X | 0 |

2B |4 7415 11| 3C | 1 | 0 | X | 0 |

2C |5 10| 3B | 1 | 1 | 0 | 0 |

2Y |6 9| 3A | 1 | 1 | 1 | Z |

GND |7 8| 3Y +---+---+---*---+

+----------+

7416

Hex open-collector high-voltage inverters.

Maximum output voltage is 15V. +---+--+---+ +---*---+ _

1A |1 +--+ 14| VCC | A |/Y | /Y = A


16

/1Y |2 13| 6A +===*===+

2A |3 12| /6Y | 0 | Z |

/2Y |4 7416 11| 5A | 1 | 0 |

3A |5 10| /5Y +---*---+

/3Y |6 9| 4A

GND |7 8| /4Y

+----------+

7417

Hex open-collector high-voltage buffers.

Maximum output voltage is 15V. +---+--+---+ +---*---+

1A |1 +--+ 14| VCC | A | Y | Y = A

1Y |2 13| 6A +===*===+

2A |3 12| 6Y | 0 | 0 |

2Y |4 7417 11| 5A | 1 | Z |

3A |5 10| 5Y +---*---+

3Y |6 9| 4A

GND |7 8| 4Y

+----------+

7418

Dual 4-input NAND gates with schmitt-trigger inputs.

0.8V typical input hysteresis at VCC=+5V. +---+--+---+ +---+---+---+---*---+ ____

1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD

1B |2 13| 2D +===+===+===+===*===+

|3 12| 2C | 0 | X | X | X | 1 |

1C |4 7418 11| | 1 | 0 | X | X | 1 |

1D |5 10| 2B | 1 | 1 | 0 | X | 1 |

/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |

GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 |

+----------+ +---+---+---+---*---+

7419

Hex inverters with schmitt-trigger line-receiver inputs.

0.8V typical input hysteresis at VCC=+5V. +---+--+---+ +---*---+ _

1A |1 +--+ 14| VCC | A |/Y | /Y = A

/1Y |2 13| 6A +===*===+

2A |3 12| /6Y | 0 | 1 |

/2Y |4 7414 11| 5A | 1 | 0 |

3A |5 10| /5Y +---*---+

/3Y |6 9| 4A

GND |7 8| /4Y

+----------+

7420

Dual 4-input NAND gates. +---+--+---+ +---+---+---+---*---+ ____

1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD

1B |2 13| 2D +===+===+===+===*===+

|3 12| 2C | 0 | X | X | X | 1 |


17

1C |4 7420 11| | 1 | 0 | X | X | 1 |

1D |5 10| 2B | 1 | 1 | 0 | X | 1 |

/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |

GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 |

+----------+ +---+---+---+---*---+

7421

Dual 4-input AND gates. +---+--+---+ +---+---+---+---*---+

1A |1 +--+ 14| VCC | A | B | C | D | Y | Y = ABCD

1B |2 13| 2D +===+===+===+===*===+

|3 12| 2C | 0 | X | X | X | 0 |

1C |4 7421 11| | 1 | 0 | X | X | 0 |

1D |5 10| 2B | 1 | 1 | 0 | X | 0 |

1Y |6 9| 2A | 1 | 1 | 1 | 0 | 0 |

GND |7 8| 2Y | 1 | 1 | 1 | 1 | 1 |

+----------+ +---+---+---+---*---+

7422

Dual 4-input open-collector NAND gates. +---+--+---+ +---+---+---+---*---+ ____

1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD

1B |2 13| 2D +===+===+===+===*===+

|3 12| 2C | 0 | X | X | X | Z |

1C |4 7422 11| | 1 | 0 | X | X | Z |

1D |5 10| 2B | 1 | 1 | 0 | X | Z |

/1Y |6 9| 2A | 1 | 1 | 1 | 0 | Z |

GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 |

+----------+ +---+---+---+---*---+

7424

Quad 2-input NAND gates with schmitt-trigger line-receiver inputs.

0.8V typical input hysteresis at VCC=+5V. +---+--+---+ +---+---*---+ __

1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB

1B |2 13| 4B +===+===*===+

/1Y |3 12| 4A | 0 | 0 | 1 |

2A |4 7424 11| /4Y | 0 | 1 | 1 |

2B |5 10| 3B | 1 | 0 | 1 |

/2Y |6 9| 3A | 1 | 1 | 0 |

GND |7 8| /3Y +---+---*---+

+----------+

7425

Dual 4-input NOR gates with enable input. +---+--+---+ __________

1A |1 +--+ 14| VCC Y = G(A+B+C+D)

1B |2 13| 2D

1G |3 12| 2C

1C |4 7425 11| 2G

1D |5 10| 2B

/1Y |6 9| 2A

GND |7 8| /2Y


18

+----------+

7426

Quad 2-input open-collector high-voltage NAND gates.

Maximum output voltage is 15V. +---+--+---+ +---+---*---+ __

1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB

1B |2 13| 4B +===+===*===+

/1Y |3 12| 4A | 0 | 0 | Z |

2A |4 7426 11| /4Y | 0 | 1 | Z |

2B |5 10| 3B | 1 | 0 | Z |

/2Y |6 9| 3A | 1 | 1 | 0 |

GND |7 8| /3Y +---+---*---+

+----------+

7427

Triple 3-input NOR gates. +---+--+---+ +---+---+---*---+ _____

1A |1 +--+ 14| VCC | A | B | C |/Y | /Y = A+B+C

1B |2 13| 1C +===+===+===*===+

2A |3 12| /1Y | 0 | 0 | 0 | 1 |

2B |4 7427 11| 3C | 0 | 0 | 1 | 0 |

2C |5 10| 3B | 0 | 1 | X | 0 |

/2Y |6 9| 3A | 1 | X | X | 0 |

GND |7 8| /3Y +---+---+---*---+

+----------+

7428

Quad 2-input NOR gates with buffered outputs. +---+--+---+ +---+---*---+ ___

/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = A+B

1A |2 13| /4Y +===+===*===+

1B |3 12| 4B | 0 | 0 | 1 |

/2Y |4 7428 11| 4A | 0 | 1 | 0 |

2A |5 10| /3Y | 1 | 0 | 0 |

2B |6 9| 3B | 1 | 1 | 0 |

GND |7 8| 3A +---+---*---+

+----------+

7430

8-input NAND gate.


19

+---+--+---+ ________

A |1 +--+ 14| VCC /Y = ABCDEFGH

B |2 13|

C |3 12| H

D |4 7430 11| G

E |5 10|

F |6 9|

GND |7 8| /Y

+----------+

Positive Logic

________

Y = ABCDEFGH

7431

Hex delay elements.

Typical delays are 27.5ns (1,6), 46.5ns (2,5), 6ns (3,4). Improved output currents IoH=-

1.2mA, IoL=24mA for gates 3 and 4. +---+--+---+ _ _____

1A |1 +--+ 16| VCC /1Y=1A /4Y=4A.4B

/1Y |2 15| 6A

2A |3 14| /6Y 2Y=2A 5Y=5A

2Y |4 13| 5A _____ _

3A |5 7431 12| 5Y /3Y=3A.3B /6Y=6A

3B |6 11| 4B

/3Y |7 10| 4A

GND |8 9| /4Y

+----------+


20

7432

Quad 2-input OR gates.

+---+--+---+ +---+---*---+

1A |1 +--+ 14| VCC | A | B | Y | Y = A+B

1B |2 13| 4B +===+===*===+

1Y |3 12| 4A | 0 | 0 | 0 |

2A |4 7432 11| 4Y | 0 | 1 | 1 |

2B |5 10| 3B | 1 | 0 | 1 |

2Y |6 9| 3A | 1 | 1 | 1 |

GND |7 8| 3Y +---+---*---+

+----------+

Positive Logic

Y = A+B

7433

Quad 2-input open-collector NOR gates. +---+--+---+ +---+---*---+ ___

/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = A+B

1A |2 13| /4Y +===+===*===+

1B |3 12| 4B | 0 | 0 | Z |

/2Y |4 7433 11| 4A | 0 | 1 | 0 |

2A |5 10| /3Y | 1 | 0 | 0 |

2B |6 9| 3B | 1 | 1 | 0 |

GND |7 8| 3A +---+---*---+

+----------+


21

7437

Quad 2-input NAND gates with buffered output. +---+--+---+ +---+---*---+ __

1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB

1B |2 13| 4B +===+===*===+

/1Y |3 12| 4A | 0 | 0 | 1 |

2A |4 7437 11| /4Y | 0 | 1 | 1 |

2B |5 10| 3B | 1 | 0 | 1 |

/2Y |6 9| 3A | 1 | 1 | 0 |

GND |7 8| /3Y +---+---*---+

+----------+

7438

Quad 2-input open-collector NAND gates with buffered output. +---+--+---+ +---+---*---+ __

1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB

1B |2 13| 4B +===+===*===+

/1Y |3 12| 4A | 0 | 0 | Z |

2A |4 7438 11| /4Y | 0 | 1 | Z |

2B |5 10| 3B | 1 | 0 | Z |

/2Y |6 9| 3A | 1 | 1 | 0 |

GND |7 8| /3Y +---+---*---+

+----------+

7440

Dual 4-input NAND gates with buffered output. +---+--+---+ +---+---+---+---*---+ ____

1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD

1B |2 13| 2D +===+===+===+===*===+

|3 12| 2C | 0 | X | X | X | 1 |

1C |4 7440 11| | 1 | 0 | X | X | 1 |

1D |5 10| 2B | 1 | 1 | 0 | X | 1 |

/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |

GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 |

+----------+ +---+---+---+---*---+

7442

1-of-10 inverting decoder/demultiplexer. +---+--+---+ +---+---+---+---*---+---+---+---+

/Y0 |1 +--+ 16| VCC | S3| S2| S1| S0|/Y0|/Y1|...|/Y9|

/Y1 |2 15| S0 +===+===+===+===*===+===+===+===+

/Y2 |3 14| S1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |

/Y3 |4 13| S2 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |

/Y4 |5 7442 12| S3 | . | . | . | . | 1 | 1 | . | 1 |

/Y5 |6 11| /Y9 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |

/Y6 |7 10| /Y8 | 1 | 0 | 1 | X | 1 | 1 | 1 | 1 |

GND |8 9| /Y7 | 1 | 1 | X | X | 1 | 1 | 1 | 1 |

+----------+ +---+---+---+---*---+---+---+---+


22

7446, 7447

Open-collector BCD to 7-segment decoder/common-anode LED driver with ripple blank

input and output.

7446 has 30V outputs, 7447 has 15V outputs. +---+--+---+

A1 |1 +--+ 16| VCC

A2 |2 15| /YF

/LT |3 14| /YG

/RBO |4 13| /YA

/RBI |5 7447 12| /YB

A3 |6 11| /YC

A0 |7 10| /YD

GND |8 9| /YE

+----------+

7448

BCD to 7-segment decoder/common-cathode LED driver with ripple blank input and

output. +---+--+---+

A1 |1 +--+ 16| VCC

A2 |2 15| YF

/LT |3 14| YG

/RBO |4 13| YA

/RBI |5 7448 12| YB

A3 |6 11| YC

A0 |7 10| YD

GND |8 9| YE

+----------+

Testing:

Answer the following questions:

1) What is a logic family?

2) What are different classifications of logic family?

3) What is difference between TTL and CMOS?

4) What series used in TTL and CMOS?

5) Why 74XX preferred over 54XXss?

6) Why IC colour is black?

7) What is power supply requirement of TTL and CMOS ICs?

8) What are different characteristics of a digital IC? Explain with typical values for

CMOS and TTL.

9) Is TTL gate output directly connected to CMOS gate input and vice versa?


23

10) Explain Interfacing between TTL and CMOS, with Voltage and current relations.

11) Which advantageous to use TTL or CMOS? Why?

12) What is tri-state logic?

13) Which is a fastest logic family?

14) What is schottky TTL? Draw symbol of schottky transistor.

15) What is mean by LS, ASL, AS logic families?

16) What is input output profile of TTL IC?

17) Is floating input allowed in TTL? Justify.

18) What is wire anding?

19) What are different configurations of TTL?

Conclusion:

TTL logic family characteristics and ICs are thoroughly studied.


24

ASSIGNMENT No: 2

Title of Assignment: Code converters, e.g. Excess-3 to BCD and vice versa.

AIM: - To study following code converters and verify the truth table.

a) Binary to Gray

b) Gray to Binary

c) Excess 3 to BCD

d) BCD to Excess 3

APARATUS: - 1) Digital Trainer kit

2) Connecting wires

3) ICs-- 7404,7486,7408,7432.

THEORY: -

A) Binary to Gray:-

Any Binary no. converted into Gray code using following method.

For example: - Binary ---- 1 0 0 1

(add)

1 1 0 1

B) Gray to Binary :-

Any Gray no. converted into Binary code using following method .

For Example :- Gray ---- 1 1 0 1

1 0 0 1

C) BCD to Excess 3 :-

Add 3 to each digit of BCD no. which is to be converted into Excess 3.

For Example :- BCD ---- 0 1 1 0

+ 0 0 1 1

1 0 0 1


25

D) Excess 3 to BCD :-

Subtract 3 from the given no. to get BCD no.

For Example: - XS3 ---- 1 0 0 1

- 0 0 1 1

0 1 1 0

DESIGN: - Convert 4 bit Binary code into Gray code.

1) Truth table.

Binary Inputs Gray Outputs

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

2) K-Map :- For G3

B1B0

B3B2 00 01 11 10

00

01

11

10

G3 = B3

0 0 0 0

0 0 0 0

1 1 1 1

1 1 1 1


26

For G2

B1B0

B3B2 00 01 11 10

00

01

11

10

G2 = B3B2 + B3 B2 = B3 B2

For G1

B1B0

B3B2 00 01 11 10

00

01

11

10

G1 = B2 B1 + B2 B1 = B2 B1

For G0

B1B0

B3B2 00 01 11 10

00

01

11

10

G0 = B1 B0 + B1 B0

0 0 0 0

1 1 1 1

0 0 0 0

1 1 1 1

0 0 1 1

1 1 0 0

1 1 0 0

0 0 1 1

0 1 0 1

0 1 0 1

0 1 0 1

0 1 0 1


27

b) Convert 4 bit Gray code into Binary code.

3) Truth table.

Gray Inputs Binary Outputs

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

4) K-Map: - For B3

G3G2

G1G0 00 01 11 10

00

01

11

10

B3 = G3

For B2

G3G2

G1G0 00 01 11 10

00

01

11

10

B2 = G3 G2 + G3 G2 = G3 G2

0 0 1 1

0 0 1 1

0 0 1 1

0 0 1 1

0 1 0 1

0 1 0 1

0 1 0 1

0 1 0 1


28

For B1

G3G2

G1G0 00 01 11 10

00

01

11

10

B1 = G1 G2 G3

For B0

G3G2

G1G0 00 01 11 10

00

01

11

10

B0 = G0 G1 G2 G3

c) Convert BCD to Excess – 3 code.

a. Truth table.

Decimal

Digit

BCD Code Excess – 3 Code

B3 B2 B1 B0 E3 E2 E1 E0

0

1

2

3

4

5

6

7

8

9

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

b. K-Map: - For E3

B3B2

B1B0 00 01 11 10

00

01

11

10

0 1 0 1

0 1 0 1

1 0 1 0

1 0 1 0

0 1 0 1

1 0 1 0

0 1 0 1

1 0 1 0

0 0 X 1

0 1 X 1

0 1 X X

0 1 X X


29

E3 = B3 + B2B0 + B2B1

For E2

B3B2

B1B0 00 01 11 10

00

01

11

10

E2 = B2B0 + B2B1 + B2B1B0

For E1

B3B2

B1B0 00 01 11 10

00

01

11

10

E1 = B1B0 + B1B0

For E0

B3B2

B1B0 00 01 11 10

00

01

11

10

E0 = B0

0 1 X 0

1 0 X 1

1 0 X X

1 0 X X

1 1 X 1

0 0 X 0

1 1 X X

0 0 X X

1 1 X 1

0 0 X 0

0 0 X X

1 1 X X


30

d) Convert Excess – 3 to BCD.

c. Truth table.

Decimal

Digit

Excess – 3 Code BCD Code

E3 E2 E1 E0 B3 B2 B1 B0

0

1

2

3

4

5

6

7

8

9

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

d. K-Map: - For B3

E3E2

E1E0 00 01 11 10

00

01

11

10

B3 = E3E2 + E3E1E0

For B2

E3E2

E1E0 00 01 11 10

00

01

11

10

B2 = E2E1 + E2E1E0 +E3E1E0

X 0 1 0

X 0 X 0

0 0 X 1

X 0 X 0

0 1 X 0

1 0 X 1

1 0 X X

1 0 X X


31

For B1

E3E2

E1E0 00 01 11 10

00

01

11

10

B1 = E1E0 + E1E0

For B0

E3E2

E1E0 00 01 11 10

00

01

11

10

B0 = E0

Testing:

1. Make the connections as shown in Fig.

2. Switch ON the supply and verify the truth table.

Conclusion:

Code converters studied successfully.

1 1 X 1

0 0 X 0

1 1 X X

0 0 X X

1 1 X 1

0 0 X 0

0 0 X X

1 1 X X


32

ASSIGNMENT No: 3

Title of Assignment: Multiplexers: Application likes Realization of Boolean expression

using Multiplexer.

Aim :- Study of MUX.

a) Verification of functionality of Mux IC.

b) Realization of Boolean expression using Mux.

Theory :-

Multiplexer is a combinational logic circuit with multiple input,

single output and select lines to select particular input and applied it at

output. For N input mux M select inputs are required where N = 2M

N input Multiplexer Block diagram

When E (Enable ) input is active low. Depending upon digital code applied

at the select inputs, one out of N data inputs is get selected at output. Enable

input is also used for cascading of Mux.

N:1

Mux

E

Select inputs

Y

Y

Io

I1

I2

In


33

8:1 Multiplexer Block diagram

Truth Table

Select Inputs

Enable

Y(output) S2 S1 S0

0 0 0 0 I0

0 0 1 0 I1

0 1 0 0 I2

0 1 1 0 I3

1 0 0 0 I4

1 0 1 0 I5

1 1 0 0 I6

1 1 1 0 I7

Types of Designing Boolean Expression using Mux :

1) LSB Method

2) MSB Method

8:1

Mux

E

S0 S1 S2

LSB MSB

Y

Y

Io

I1

I2

I7


34

Circuit Diagram :- 4:1 Mux

A) According to truth table verify the IC 74151

B) Implement the following Boolean function using MUX.

Use LSB Method

1) Step I :- Designing

Y(A,B,C,D)= ∑ m(1,3,4,11,12,13,14,15)

S1 S0 Enable

I0

I1

I2

I3

Y


35

INPUT OUTPUT

A B C D Y I/P OF MUX

0 0 0 0 0

D 0 0 0 1 1

0 0 1 0 0

D 0 0 1 1 1

0 1 0 0 1 D 0 1 0 1 0

0 1 1 0 0

0 0 1 1 1 0

1 0 0 0 0

0 1 0 0 1 0

1 0 1 0 0

D 1 0 1 1 1

1 1 0 0 1

1 1 1 0 1 1

1 1 1 0 1

1 1 1 1 1 1

Representation of input line in terms of variable D

Select Inputs

Y S2 S1 S0

0 0 0 D

0 0 1 D

0 1 0 D

0 1 1 0

1 0 0 0

1 0 1 D

1 1 0 1

1 1 1 1


36

3) Step-II

Logical Diagram :-

Testing:

1. Make the connection according to circuit diagram

2. Connect Vcc & GND to IC.

3. verify the functionality of given function according to truth table.

Conclusion:

Multiplexer applications successfully implemented.

VCC GND

I0

I1

I2

I3 IC 74151

I4 8:1 MUX

I5

I6

I7

E S0 S1 S2

Y

Y


37

ASSIGNMENT No: 4

Title of Assignment: Demultiplexers: Application like Realization of ROM using

Demultiplexer.

Aim :- Study of DEMUX.

c) Verification of functionality of DEMux IC.

d) Realization of 4*4 ROM using Demux.

Theory :- Demultiplexer is a combinational logic circuit with sigle

input, multiple outputs and select lines to select particular output and

applied input at selected output. For N output demux M select inputs are

required where N = 2M

N output Demultiplexer Block diagram

When E (Enable ) input is active low. Depending upon digital code applied

at the select inputs, one out of N data outputs is get selected and input data

get applied at that output. Enable input is also used for cascading of Demux.

Select inputs

1 : 8

Demux

E

Do

D1

D2

Dn

Data input


38

Block Diagram of 1 : 8 Demux

Function table :-

For active low output :-

Select Inputs Enable Outputs

S2 S1 S0 Y0 Y1 Y2 Y3 Y4 Y5 Y Y7

0 0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 0 1 0 0 0 0 0 0

0 1 0 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 0 1

1 : 8

Demux

E

S0 S1 S2

Do

D1

D2

D7

Data input


39

Circuit Diagram of 1:4 Demux

Realization of 4*4 ROM using DEMUX

D0 (P, Q, R) = ∑ m (2, 3)

D1 (P, Q, R) = ∑ m (1, 2)

D2 (P, Q, R) = ∑ m (0, 2,3)

D3 (P, Q, R) = ∑ m (1, 2, 3)

S1 S0 Enable

Data Input

Y0

Y1

Y2

Y3


40

Select lines Data in bits Data

S0 S1 S2 D0 D1 D2 D3

0 0 0 0 0 1 0 2

0 0 1 0 1 0 1 5

0 1 0 1 1 1 1 F

0 1 1 1 0 1 1 B

Logic Diagram for given function.

Testing:

1) Verify the functiontable by connecting input and output according to

pin diagram.

VCC GND

D0

D1

D2

1: 8 D3

Demux

D4

D5

En1 D6

En2 D7

En3

D0

D1

D2

D2

Date line

Vcc

S0 S1 S2


41

2) Realization of 4*4 ROM : Make the connection according to logic

diagram

3) Connect Vcc & GND connection

4) verify the output data shown in truth table.

Conclusion:

Demultiplexer applications successfully studied.


42

ASSIGNMENT No: 5

Title of Assignment: Write BCD adder / subtractor using 4 bit binary adder 7483.

AIM: - Design and Implement 4 bit BCD Adder using IC 7483. APPARATUS: - Digital Trainer kit. Connecting wires, IC 7483, 7408, 7432.

THEORY: BCD adder is combinational logic circuit, which performs the

addition of two BCD digits and produces the sum in BCD

forms. BCD is four-bit binary coded decimal number; BCD

addition can be performed using the binary

addition. The result of binary adder may be valid or invalid

BCD. If result is invalid, BCD can be converted into valid

BCD by adding 0110 to the result as shown below.

In this practical 4 bit binary adder is used as a BCD adder. So

for valid BCD

addition 3 cases are checked.

Case I :- Result is less than 9 and carry zero.

Case II :- Result is less than 9 and carry is one.

Case III :- Result is greater than 9 and carry is zero.

Example for above conditions :-

Case I :- Result is less than 9 and carry zero.

4 + 3 = 7 0 1 0 0 + 0 0 1 1 0 1 1 1 Result is

valid


43

Case II :- Result is less than 9 and carry is one.

8 + 8 = 16 1 0 0 0

+ 1 0 0 0

1 0 0 0 0 Result is

invalid

To make invalid result valid add 6 in the result.

1 0 0 0 0

+ 0 1 1 0

10 1 1 0 Valid

result

Case III :- Result is greater than 9 and carry is zero.

8 + 5 = 13 1 0 0 0

+ 0 1 0 1

1 1 0 1 Result is

invalid

To make invalid result valid add 6 in the result.

1 1 0 1

+ 0 1 1 0

1 0 0 1 1 Valid result

Truth Table for detecting invalid result:-

The result of addition is valid upto 9 because for 4 bit 1 to 9 is

valid range for BCD code. The result above 9 is invalid this invalid result is

detected by generation of carry. So above 9 number upto 15 the carry output

considered as 1 and below 9 it is 0 as shown in table below.


44

S3 S2 S1 S0 Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

o. 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

K- Map for carry out Y.

S1S0

00 01 11 10

S3S2

00

01

11

10

Y = S1 S3 + S3 S2

S3 (S1 + S2)

0 0 0 0

0 0 0 0

1 1 1 1

0 0 1 1


45

Logical Diagram :-

B3 B2 B1 B0 A3 A2 A1 A0

4 Bit Binary Adder IC 7483 Cin

Cout S3 S2 S1 S0

B3 B2 B1 B0 A3 A2 A1 A0

Cout 4 Bit Binary Adder IC 7483 Cin

S3 S2 S1 S0

ignored

Final valid Result unit‘s digit

Ten‘s Digit


46

Testing:

1) Make connection as shown in fig.

2) Check the output for 3 cases mentioned aboved.

Conclusion:

BCD adder and subtractor successfully implemented.


47

ASSIGNMENT No: 6

Title of Assignment: Parity generator / detector.

Aim To study Parity Generator And checker and to Verify Even parity and odd

parity

Apparatus : - Digital Trainer kit, Connecting wires, IC 74180

Theory :-

Parity bit is an extra bit included with Binary information to detect the errors during

transmission of binary information. In binary communication, extra bit is added in

binary message such that total number of ones in the massage can be either odd or

even. The combinational circuit, which generates the parity bit, is known as parity

generator.

At receiving end, a combinational circuit is used to check the parity of receiving

information, and determines whether the error is included in the massage or not. This

combinational circuit is known a parity checker.

IC 74180

IC 74180 is nine input parity generator / checker . It can used as a parity generator as

well as parity checker. It has eight parity inputs A to H and two cascading inputs. It

has two outputs, Even and Odd.

Logic symbol of IC 74180 is shown in fig.

Parity Inputs

Outputs

Cascading Inputs

A

B

C Σ Even

D

E IC

F 74180

G

H Σ Odd

Even

Odd


48

The truth table of 74180 is given below

Parity

Input

Cascading Inputs Outputs

Even Odd Even Odd

Even 1 0 1 0

Odd 1 0 0 1

Even 0 1 0 1

Odd 0 1 1 0

X 1 1 0 0

From the truth table of IC 74180, it is found that.

Parity input + Cascading inputs = Outputs

Even + Even = Even

Odd + Odd = Even

Odd + Even = Odd

Even + Odd = Odd

It is important to note that when cascading inputs are logic ‗1‘ , then

outputs are logic ‗0; and when both cascading inputs are logic ‗0‘,then

output are logic 1.

Problem statement:

Design a 9 bit even parity checker using IC 74180 and suitable gate

I

Problem: Design 9-Bit Odd parity generator using IC 74180

IC 74180 is a 9-bit parity generator. It has 8 parity inputs, two cascading

inputs and two outputs. It generates parity bit according to the 8 inputs

messages.

A

B

C Σ Even

D

E IC

F 74180

G

H Σ Odd

Even

Odd


49

The logic diagram of 9-bit parity generator is shown below:

Testing:

Make appropriate connections and check the output.

Conclusion:

Parity generation and detection successfully implemented.

A

B

C

D Σ Even

E

F

G Σ Odd

H

I

Logic 1


50

ASSIGNMENT No: 7

Title of Assignment: Flip flops, Registers and Counters (Study and Write up only).

Aim :- (A) To study various types of flip-flops

(B) Implementation of T and D flip-flop using M/S JK flip-flop

Apparatus : - Digital Trainer kit, Connecting wires, IC 7476, IC 7474, IC 7473.

Theory :-

Fundamental building block of sequential circuits is flip-flop. Flip-flop is a 1-bit

storage element. It is edge triggered device.

(a) +ve edge triggered (b) -ve edge triggered

Types of flip-flops:

SR Flip-Flop:

FLIP-FLOPS

Asynchronous Output change as soon as

input applied changes the state

Synchronous Output change in

synchronism with the clock pulses

1. SR FLIP-FLOP

2. JK FLIP-FLOP

3. M/S JK FLIP-FLOP

4. T FLIP-FLOP

5. D FLIP-FLOP


51

Symbol of SR F/F Internal Diagram

TRUTH TABLE OF SR FLIP-FLOP LIMITATION OF SR FLIP-FLOP:

In SR F/F, when S=R=1, the output Q and Q

are

same.Logically it is not possible. Such state is

refered as forbidden state.

JK Flip-Flop:

Symbol of JK F/F Internal Diagram

TRUTH TABLE OF SR FLIP-FLOP LIMITATION OF JK FLIP-FLOP

S R Pr Cr Qn

X X 0 1 1

X X 1 0 0

0 0 1 1 Qn

0 1 1 1 0

1 0 1 1 1

1 1 1 1 ?

Q

Q

Q

S

CLK

R

S Q

CLK

R Q

Pr

Cr

J Q

CLK

K Q

Pr

Cr

Q

Q

Q

J

CLK

K

Pr

Cr


52

In JK flip-flop when J=K=1, it acts as toggle

switch,

In presence of clock the output toggles and at

the end

of clock we can not predict what will be Q

and Q.

this is called as race around condition.

MS JK Flip-Flop:

Internal Diagram

J K Pr Cr Qn+1

X X 0 1 1

X X 1 0 0

0 0 1 1 Qn

0 1 1 1 0

1 0 1 1 1

1 1 1 1 Qn

Pr

Q

Q

Q

J

CLK

K

Q

Q

Q

J

CLK

K

Cr

J Q

CLK

K Q

Pr

Cr

J Q

CLK

K Q

Pr

Cr


53

(B) Implementation of T and D flip-flop using M/S JK flip-flop

Implementation of T Flip-flop using MS JK F/F

The T flip-flop is obtained from JK flip-flop by shorting J & K inputs

Implementation of D Flip-flop using MS JK F/F

The D flip-flop is obtained from JK flip-flop by complementing the J & K inputs.

Procedure:

1. Make the connections according to pin diagram.

2. Apply the clock input.

3. Apply different combinations of the inputs.

4. Verify the truth table

5. Build T and D flip-flops from the MS JK flip-flop.

Input

T

Output

Qn+1

0 Qn

1 Qn

Input

D

Output

Qn

0 0

1 1

Cr

J Q

CLK

K Q

Pr T

J Q

CLK

K Q

Pr

Cr

D


54

Registers

A flip-flop can store 1-bit information. A group of flip-flops can be used to store a word,

which is called as register.

Shift Registers: -

The Binary information (data) in a register can be moved from stage to

stage with the register or into or out of the register upon application of clock pulses. This

type of bit movement or shifting is essential for certain arithmetic & logic operation, used

in microprocessors. This gives rise to a group of registers called ‗ Shift registers‘ They

are very important in application involving the storage & transfer of data in a digital

system.

Modes of operation of shift registers.

1) Serial In Serial out Shift Registers. (SISO)

2) Serial In parallel out shift Registers. (SIPO)

3) Parallel in Serial out Shift Register. (PISO)

4) Parallel in Parallel out Shift Register. (PIPO)

Data bit Data bits

a) Serial shift right , then out b) serial shift left , then out

Data bit

Data bit

c) Parallel shift in d) Parallel shift out

e) Rotate Right f) Rotate left.

Universal Shift register: -

IC 74194 is a 4-bit universal shift Register. It can perform all the operation of

SISO, SIPO, PISO, PIPO. Or Bidirectional .


55

Application of shift registers

1) Delay line

2) Serial to parallel converter

3) Shift register counters

4) Ring counters.

Counters

Counter is register capable of counting the number of clock pulse arriving at its

clock inputs. Count represent the number of clock pulse arrived. A specified sequence of

states appear, as the couter output. This is the main difference between a register & a

counter

There are two types of counters

1) SYNCHRONOUS COUNTER

2) A SYNCHRONOUS COUNTER

SYNCHRONOUS COUNTER:-

In synchronous counter, the clock pulse is given

simultaneously to all the flip-flops. Transition occurs at output with synchronous of clock

inputs.

ASYNCHRONOUS/RIPPLE COUNTER:-

In asynchronous counter commonly called

ripple counter ,the first flip-flop is clocked by the external clock pulse & then each

successive flip-flop is clocked by the Q or /Q output of the previous flip-flop .

Counter application :-

1) digital clock

2) Frequency counter.

Testing:

NA

Conclusion:

Flip-flops, registers and counters successfully implemented.


56

ASSIGNMENT No:08

Title of Assignment: Ripple counter using flip-flops.

Aim: To study the 3 bit asynchronous up/down counter using JK flip-flop

Apparatus: Digital Trainer Kit, IC 7476, IC 7408, IC 7432.

Theory:

In asynchronous counter commonly called ripple counter, the first flip-flop is

clocked by the external clock pulse & then each successive flip-flop is clocked by the Q

or /Q output the previous flip-flop. Therefore in an asynchronous counter the flip-flop are

not clocked simultaneously. The input of MSJK is connected to VCC because when both

inputs are one output is toggled. As MSJK is negative edge triggered at each high to low

transition the next flip-flop is triggered. On this basis the design is done for MOD-8

counter.

Up Counter down Counter

Logic diagram:

Counter

States Count

QA QB QC

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

Counter

States Count

QA QB QC

7 1 1 1

6 1 1 0

5 1 0 1

4 1 0 0

3 0 1 1

2 0 1 0

1 0 0 1

0 0 0 0


57

3 Bit Asynchronous Up Counter

3 Bit Asynchronous Down Counter

QC QB Q A

J Q

K Q

J Q

K Q

J Q

K Q

J Q

K Q

J Q

K Q

J Q

K Q

QC QB QA


58

3 Bit Asynchronous Up/Down Counter

Testing:

1. Make the connections as show In fig.

2. Make connection for Asynchronous up counter..

3. Make connection for Asynchronous down counter..

4. Make connection for Asynchronous up/down counter..

5. Verify the counter operation in different mode.

Conclusion:

Ripple counter is successfully implemented.

QC QB QA

J Q

K Q

J Q

K Q

J Q

K Q


59

ASSIGNMENT No:09

Title of Assignment: Sequence generator using JK flip-flop

Aim : Design & implement Sequence Generator using JK flip-flop

Apparatus : Digital Trainer Kit, IC 7476, IC 7432

Theory :- A Sequence Circuit, Which generates a prescribed sequence of bits

in synchronism with a clock, is referred to as sequence generator. In

synchronous or clocked flip-flops are used as memory elements, which

change their individual states in synchronism with the periodic clock

signal. Therefore, the change in states of flip-flops & change in states of

the entire circuit occur at the transition of the clock signal.

Generalized Block diagram for sequence generator

Excitation table of JK flip-flop

Present

state

Next state Jn Kn

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Next state

decoder

F F1

F F2

F Fn


60

Problem statement :- Design sequence generator to go through the following states by

using J K flip-flop

Solution :- Excitation Table.

Present states Next state A B C

QA QB QC QA+1 QB+1 QC+1 JA KA JB KB JC KC

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 1 0 X 1 X X 0

0 1 0 X X X X X X X X X

0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 1 0 X 0 1 X 0 X

1 0 1 X X X X X X X X X

1 1 0 0 0 0 X 1 X 1 0 X

1 1 1 X X X X X X X X X

K Map :-

For JA For KA

QBQC QBQC

QA 00 01 11 10 QA 00 01 11 10

0 0 0 1 X 0 X X X X

1 X X X X 1 0 X X 1

JA = QB KA = QB

For JB For KB

QBQC QBQC

QA 00 01 11 10 QA 00 01 11 10

0 0 1 X X 0 X X 1 X

1 1 X X X 1 X X X 1

JB = QA+QC KB = 1

0

1 6

3 4


61

For JC For KC

QBQC QBQC

QA 00 01 11 10 QA 00 01 11 10

0 1 X X X 0 X 0 1 X

1 0 X X 0 1 X X X X

JC = QA KC = QB

Connection Diagram:-

Testing:

1) Design a logic circuit to generate given logic sequence.

2) Connect circuits as per logic diagram

3) Apply clock inputs & verify logic sequence

Conclusion: Sequence generator is implemented successfully.

J Q

C

K Q

J Q

B

K Q

J Q

A

K Q vcc

QC QB QA

PR

CLR

CLK


62

ASSIGNMENT No: 10

Title of Assignment: Sequence detector using JK flip-flop.

Aim : Design & implement Sequence Detector using JK flip-flop

Apparatus : Digital Trainer Kit, IC 7476, IC 7432, IC 7408

Theory:-

• A sequence detector is a special kind of sequential circuit that looks for a special bit

pattern in some input.

• The recognizer circuit has only one input, X.

– One bit of input is supplied on every clock cycle. For example, it would take 20 cycles

to scan a 20-bit input.

–This is an easy way to permit arbitrarily long input sequences.

• There is one output, Z, which is 1 when the desired pattern is found.

• Our example will detect the bit pattern ―1001‖:

Inputs: 11100110100100110…

Outputs: 00000100000100100…

• Here, one input and one output bit appear every clock cycle.

• This requires a sequential circuit because the circuit has to ―remember‖ the inputs from

previous clock cycles, in order to determine whether or not a match was found.

•What state do we need for the sequence recognizer?

–We have to ―remember‖ inputs from previous clock cycles.

–For example, if the previous three inputs were 100 and the current input is 1, then the

output should be 1.

–In general, we will have to remember occurrences of parts of the desired pattern—in this

case, 1, 10, and 100.

• A basic state diagram:

State Meaning

A None of the desired pattern (1001) has been input yet (BLIND).

B We‘ve already seen the first bit (1) of the desired pattern.

C We‘ve already seen the first two bits (10) of the desired pattern.

D We‘ve already seen the first three bits (100) of the desired pattern.

A B C D 1/0 0/0 0/0


63

•What happens if we‘re in state D (the last three inputs were 100), and the current input is

1?

–The output should be a 1, because we‘ve found the desired pattern.

–But this last 1 could also be the start of another occurrence of the pattern! For example,

1001001 contains two occurrences of 1001.

–To detect overlapping occurrences of the pattern, the next state should be B.

•Remember that we need two outgoing arrows for each node, to account for the

possibilities of X=0 and X=1.

•The remaining arrows we need are shown in next figure. They also allow for the correct

detection of overlapping occurrences of 1001.

•We have four states ABCD, so we need at least two flip-flops Q1Q0.

•The easiest thing to do is represent state A with Q1Q0 = 00, B with 01, C with 10, and D

with 11.

•The state assignment can have a big impact on circuit complexity, but we won‘t worry

about that too much in this class.

• Now the transition truth table can be constructed from the state diagram.

A B C D 1/0 0/0 0/0

1/1

A B C D 1/0 0/0 0/0

1/1

0/0

0/0

1/0

1/0


64

Present

State

Input

Next

State

Output

Q1 Q0 X Q1 Q0 Z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 1 0 0

0 1 1 0 1 0

1 0 0 1 1 0

1 0 1 0 1 0

1 1 0 0 0 0

1 1 1 0 1 1

•Now you can make K-maps and find equations for each of the four flip-flop inputs, as

well as for the output Z.

•These equations are in terms of the present state and the inputs.

J1 = X‘ Q0, K1 = X + Q0

J0 = X + Q1, K0 = X‘, Z = Q1Q0X

Lastly, we use these simplified equations to build the completed circuit.

Z = Q1Q0X


65

Testing:

Step 1:

Make a state table based on the problem statement. The table should show the

present states, inputs, next states and outputs. (It may be easier to find a state diagram

first, and then convert that to a table.)

Step 2: Assign binary codes to the states in the state table, if you haven‘t already.

If you have n states, your binary codes will have at least

[log2 n] digits, and your circuit will have at least [log2 n] flip-flops.

Step 3: For each flip-flop and each row of your state table, find the flip-flop input

values that are needed to generate the next state from the present state. You can use flip-

flop excitation tables here.

Step 4: Find simplified equations for the flip-flop inputs and the outputs.

Step 5: Build the circuit!

Conclusion:

Sequence detector is successfully tested and implemented.


66

ASSIGNMENT No: 11

Title of Assignment: Up-down counter using JK flip-flop.

Aim : To study the 3 bit synchronous up/down counter using JK flip-flop

Apparatus: Digital Trainer Kit, IC 7476, IC 7408, IC 7432.

Theory : In synchronous counter, the clock pulse is given simultaneously to

all the flip-flops. Transition occurs at output with synchronous of clock

inputs.

The Basic idea of construction is to keep the J&K inputs, of each

flip-flop high, such that the flip-flop will toggle with any clock negative

going at its clock input. The clock is applied directly to flip-flop A. Since

the JK flip-flop used responds to a negative transition at the clock inputs

& toggles when both the J&K input are high. Whenever A is high And

gate is enabled & clock pulse is passed through the gate to the next stage

B. For the 3-bit synchronous counter we used 3 flip-flop stages.

UP COUNTER :- In the count-up mode, B is the required to

change state each time A is high & clk goes low. Whenever count-up line

& A are both high, the output of gate is X1 is high. Whenever either input

Z1 is high, the output is high. Therefore the J&K inputs to flip-flop B are

high whenever both count-up modes a clock negative going will toggle B,

Each time A is high. Thus UP-COUNTING operation is done

DOWN COUNTER :- In the count down mode B must change

state each time A is high & the clock goes low . the output of gate Y1 is

high & thus the J & k inputs to flip-flop B are high. Whenever A & count-

down are high. Thus in the count down mode, B changes state every time

A is high & the clock goes low 7 to 0

Problem Statement: - The 3-bit binary Up/Down synchronous counter with a

direction control M. Use J-K Flip-flop.

Excitation Table :- The designing is given in excitation table. For M = 0, it acts as

an Up counter and for M =1 as an Down counter. The number

of flip-flops required is 3. The inputs of flip-flops are

determined by using excitation table.

Present State Next State J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0


67

Control

input M

Present State Next State Input for Flip-flop

QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA

0 0 0 0 0 0 1 0 X 0 X 1 X

0 0 0 1 0 1 0 0 X 1 X X 1

0 0 1 0 0 1 1 0 X X 0 1 X

0 0 1 1 1 0 0 1 X X 1 X 1

0 1 0 0 1 0 1 X 0 0 X 1 X

0 1 0 1 1 1 0 X 0 1 X X 1

0 1 1 0 1 1 1 X 0 X 0 1 X

0 1 1 1 0 0 0 X 1 X 1 X 1

1 1 1 1 1 1 0 X 0 1 X 1 X

1 1 1 0 1 0 1 X 0 X 0 X 1

1 1 0 1 1 0 0 X 0 X 1 1 X

1 1 0 0 0 1 1 X 1 0 X X 1

1 0 1 1 0 1 0 0 X 1 X 1 X

1 0 1 0 0 0 1 0 X X 0 X 1

1 0 0 1 0 0 0 0 X X 1 1 X

1 0 0 0 1 1 1 1 X 1 X X 1

K MAP-

JA

QBQA

MQC 00 01 11 10

00

01

11

10

JA = 1

JA

QBQA

MQC 00 01 11 10

00

01

11

10

KA = 1

1 X X 1

1 X X 1

1 X X 1

1 X X 1

X 1 1 X

X 1 1 X

X 1 1 X

X 1 1 X


68

JB

QBQA

MQC 00 01 11 10

00

01

11

10

JB = M QA + M QA

KB

QBQA

MQC 00 01 11 10

00

01

11

10

JB = M QA + M QA

JC

QBQA

MQC 00 01 11 10

00

01

11

10

JB = M QA QB + M QA QB

KC

QBQA

0 1 X X

0 1 X X

1 X 0 X

1 X 0 X

X X 1 0

X X 1 0

X 0 X 1

X 0 X 1

0 0 1 0

X X X X

X X X X

1 0 0 0


69

MQC 00 01 11 10

00

01

11

10

JB = M QA QB + M QA QB

Logical Diagram:-

Testing:

1) Connect the circuit as shown

2) Connect DC power supply & provide clock signal

3) Connect Up select line to logic high to verify the truth table of up counter

4) counter down select line to logic high to verify the troth table of down counter

Conclusion:

Up and down counters are successfully implemented.

X X X X

0 0 1 0

1 0 0 0

X X X X

J Q

A

K Q

J Q

B

K Q

J Q

C

K Q

M

PR

CLR

M

CLK

VCC

QA QB QC


70

ASSIGNMENT No: 12

Title of Assignment: Study of few more examples with 7490 and 74190.

Aim :- To study Decade Binary Counter IC 7490

A) Design Mod 6 using 7490 Counter (without using gates)

B) Design Mod 10 counter with de-fragmented even and odd

counts

C) Verification of truth table of 74190

Apparatus :- Digital Trainer Kit, IC7490, IC74190, Connecting wires.

Theory :- IC 7490 is a decade binary counter . It consist of Four master slave

flip-flops & additional gating to provide a divide by two counter & a three

stage binary counter for Which the count cycle length is divide by five .

Since the output from the divide by two sections is not internally

connected to the succeeding stage, for counting further up to 10 states

connect the MOD 2 output to the input of MOD 5counter.

In fig 2 flip-flops (FFA) operates as a mod 2 counter where as the

combination flip-flop i.e. FFB, FFC, FFD Form Counter. There are two

RESET i/p i.e. R0, R1 & two SET inputs S0, S1.

Internal Diagram:

Fff1

fff

R(0) R(1) S(0) S(1)

Clk A

Clk B

MOD - 5

MOD – 2

LSB QA QB QC QD MSB

Vcc

GND


71

Reset Input Output

Ro(1) Ro(2) Rg(1) Rg(2) QD QC QB QA

H H L X L L L L

H H X L L L L L

X X H H H L L H

X L X L COUNT

L X L X COUNT

L X X L COUNT

X L L X COUNT

A)

Design Statement: Design MOD 6 counter using IC 7490 without using logic gates.

Theoretical Method :-

Logical Diagram for MOD – 6

B)

Design Statement : Design Mod 10 counter with de-fragmented even and odd counts

Logical Method :-

S0 S1 R0 R1

A

IC7490(1)

B

QA QB QC QD


72

C) Verification of truth table of 74190


73

Testing:

1) Check all the three designs described in this experiment

Conclusion:

All the three designs are successfully implemented and tested.


74

ASSIGNMENT No: 13

Title of Assignment: Pseudo random number generator using 74194

Aim :- To study pseudo random number generator using IC 74194.

Equipment :- Logic board with IC sockets & LEDs ,IC74194, IC 7486.

Theory :-

IC 74194 : Universal Shift Register

We know that a register may operate in any of the mode .like SISO,PISO,PIPO,

or Bi-directional.

IC 74194 has 4 parallel data i/p‘s (D0-D3) & S0 & S1 are the control i/p‘s. When

S0 & S1 are high, data appearing on D0-D3 i/p‘s is transferred to the Q0-Q3 o/ps

respectively. Following the next low to high transition of the clock shift right is

accomplished by setting S1 S0 = 0 1., & serial data is entered at the shift right serial i/p

DSR. Shift Left is accomplished by setting S1 S0 = 1 0, & serial data is entered at the

shift left serial i/p ,DSL. CP(clock pulse) is Positive edge triggered.

Operation Mode

I/P'S O/P'S

CP /MR S1 S0 DSR DSL Dn Q0 Q1 Q2 Q3

Reset(clear) X 0 X X X X X 0 0 0 0

Shift Left

1 1 0 X 0 X Q1 Q2 Q3 0

1 1 0 X 1 X Q1 Q2 Q3 1

Shift Right

1 0 1 0 X X 0 Q0 Q1 Q2

1 0 1 1 X X 1 Q0 Q1 Q2

Parallel Load

1 1 1 X X Dn D0 D1 D2 D3

Hold X 1 0 0 X X X Q0 Q1 Q2 Q3


75

Pseudo Random Number Generator Using IC 74194

Another important application of a shift register is the pseudo random generator .it is

used for the generating the random sequences. The PBRS generator consists of a flip flop

& a combinational circuit for providing a suitable feedback.

Q3 Q2 Q1 Q0 = 0 0 1 1.

Clock Pulse Number Shift Register EX-OR Gate PBRS Sequence

Q3 Q2 Q1 Q0 Q3 Q2 Q3

0 0 0 1 1 0

1 0 1 1 0 0

2 1 1 0 1 1

3 1 0 1 0 1

4 0 1 0 1 0

5 1 0 1 1 1

6 0 1 1 1 0

7 1 1 1 1 1

8 1 1 1 0 1

9 1 1 0 0 1

10 1 0 0 0 1

11 0 0 0 1 0

12 0 0 1 0 0

13 0 1 0 0 0

14 1 0 0 1 1

15 0 0 1 1 0

16 0 1 1 0 0

17 1 1 0 1 1

The PBRS generator cannot generate a truly random sequence because this structure is a

deterministic structure. This is reason why the sequence repeats itself.

The maximum length of sequence will be 2 m-1. This is because the state 0 0 0 . . . . . .0

must be excluded.

Binary sequence of Q3.

Length of PBRS :- 2m-1

For m = 4 :- 24-1 =15.

PBRS sequence repeats itself after every 15 clock pulse. The logical diagram for the

above designing is as given below.

0 0 1 1 0 1 0 1 1 1 1 0 0 0


76

Logical Diagram :-

74194 As a PBRS Generator

PBRS Sequence

5V

VCC Q0 Q1 Q2 Q3 CP S1 S0

MR DSR D0 D1 D2 D3 DSL GND

Application of PBRS.

Since the sequence produced is random, PBRS generator is also called as Pseudo

Noise Generator. This noise can be used to test the noise immunity of the system

under test.

PBRS Generator is an important part of data encryption system. Such a system is

required to protect the data from data hackers.

Testing:

1) Adjust data o/p of Q3 Q2 Q1 Q0 = 0 0 1 1. using parallel load operation mode.

2) Connect EX-OR gate o/p to DSR pin of IC 74194 & i/p for EX-OR is Q2 & Q3.

3) Apply clock pulse to pin 11 of IC 74194 & check PRB sequence at Q3 o/p

pin –12 of IC 74194.

Conclusion:

Pseudo random generator successfully implemented.

16 15 14 13 12 11 10 9

IC 74194

1 2 3 4 5 6 7 8


77

ASSIGNMENT No: 15

Title of Assignment: Simple ASM using multiplexer controller method.

Aim :- Design a sequential circuit using multiplexer method.

Equipment : Digital trainer kit, connecting wires, IC 74151, IC 7474.

Theory :- Generally any sequence circuit can be designed using gates & flip flops.

In this method the gates are replaced by multiplexers & flip flops are replaced by

registers.

There are 3 levels of components.

1] First level consist of multiplexers that determine the next state by the register.

2] The second level consist of register that holds the present binary state.

3] The third level has the decoder that provides a separate o/p for each control state.

Problem Statement : Draw an ASM chart for a 2 bit binary counter having one enable

line E such that

E =1 (Counting Enabled).

E =2 (Counting Disabled).


78

1) ASM chart ASM Chart :

E 0

1

0

E

1

0

E

1

E 0

1

Out = 01

Out = 10

Out = 00

Out = 11

00

q0

01

q1

11

q2

q3

10


79

(2) State Table:

Present State Next State Condition for

transition

q0

q0 /E

q1 E

q1

q0 /E

q2 E

q2

q0 /E

q3 E

q3

q0 /E

q0 E

(3) Transition Table :

Preset State Next State Condition For

Transition

A B An+1 Bn+1

S1 S0

0 0 0 0 /E

0 1 E

0 1 0 0 /E

1 0 E

1 0 0 0 /E

1 1 E

1 1 0 0 /E

0 0 E

(4) Multiplexer Method :

We required two mux one for A & one for B

A => Mux 1

B => Mux 2

Mux 1 Mux 2

0 0 0 E

1 E 1 0

2 E 2 E

3 0 3 0


80

(5) Register :

Here we are required two bit register for two bit state. Here we used two

(DA & DB ) D FF for generating present binary state .This present binary state given to

the mux .Mux select the particular i/p & generate the next state .

Connection Diagram :

E

D0 Y

QA

D1

D2

D3

D4 Y QB

D5

D6

D7

CLK

6

5 MUX

4:1

4

3

10

MUX

11

4:1

12

13

DA Q

FF

Q

DB Q

FF

Q


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Testing:

Design a logic circuit to generate given Problem Statement

Connect circuits as per logic diagram

Apply clock inputs & verify 2 bit binary counter

Conclusion:

Given problem is successfully solved and implemented using ASM.


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ASSIGNMENT No: 16

Title of Assignment: Implementation of combinational logic using PALs

Relevant Theory:

The term Programmable Array Logic (PAL) is used to describe a family of

programmable logic device semiconductors used to implement logic functions in digital

circuits introduced by Monolithic Memories, Inc. (MMI) in mid 1978.

PAL devices consisted of a small PROM (programmable read-only memory) core and

additional output logic used to implement particular desired logic functions with few

components.

Using specialized machines, PAL devices were "field-programmable". Each PAL device

was "one-time programmable" (OTP), meaning that it could not be updated and reused

after its initial programming. (MMI also offered a similar family called HAL, or "hard

array logic", which were like PAL devices except that they were mask-programmed at

the factory.)

PAL architecture

The programmable elements (shown as a fuse) connect both the true and complemented

inputs to the AND gates. These AND gates, also known as product terms, are ORed

together to form a sum-of-products logic array.

The PAL architecture consists of two main components: a logic plane and output logic

macrocells.

http://en.wikipedia.org/wiki/Image:Programmable_Logic_Device.jpg




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Programmable logic plane

The programmable logic plane is a programmable read-only memory (PROM) array that

allows the signals present on the devices pins (or the logical complements of those

signals) to be routed to an output logic macrocell.

PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-

AND" plane used to implement "sum-of-products" binary logic equations for each of the

outputs in terms of the inputs and either synchronous or asynchronous feedback from the

outputs.

Output logic

The early 20-pin PALs had 10 inputs and 8 outputs. The outputs were active low and

could be registered or combinational. Members of the PAL family were available with

various output structures called "output logic macrocells" orOLMCs. Prior to the

introduction of the "V" (for "variable") series, the types of OLMCs available in each PAL

were fixed at the time of manufacture. (The PAL16L8 had 8 combinational outputs and

the PAL16R8 had 8 registered outputs. The PAL16R6 had 6 registered and 2

combinational while the PAL16R4 had 4 of each.) Each output could have up to 8

product terms (effectively AND gates), however the combinational outputs used one of

the terms to control a bidirectional output buffer. There were other combinations that

have fewer outputs with more product term per output and were available with active

high outputs. The 16X8 family or registered devices had an XOR gate before the register.

There were also similar 24-pin versions of these PALs.

AMD 22V10 Output Macrocell

This fixed output structure often frustrated designers attempting to optimize the utility of

PAL devices because output structures of different types were often required by their

applications. (For example, one could not get 5 registered outputs with 3 active high

combinational outputs.) So, in 1983 AMD (source needed) introduced the 22V10, a 24

pin device with 10 output logic macrocells. Each macrocell could be configured by the

user to be combinational or registered, active high or active low. The number of product

term allocated to an output varied from 8 to 16. This one device could replace all of the

http://en.wikipedia.org/w/index.php?title=Sum-of-products&action=edit

http://en.wikipedia.org/w/index.php?title=Output_logic_macrocell&action=edit

http://en.wikipedia.org/w/index.php?title=OLMC&action=edit

http://en.wikipedia.org/wiki/Image:AMD_22V10_Macrocell.jpg




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24 pin fixed function PAL devices. Members of the PAL "V" ("variable") series included

the PAL16V8, PAL20V8 and PAL22V10.

PAL 16R4 Block Diagram

AMD 22V10 Block Diagram

Testing:

Build 2-bit counter using PAL.

Conclusion:

PAL is used to successfully implement the counter.

http://en.wikipedia.org/wiki/Image:PAL_Block_Diagram.jpg

http://en.wikipedia.org/wiki/Image:22V10_Block_Diagram.jpg


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ASSIGNMENT No: 17

Title of Assignment: Study of FPGA devices (Study and Write up only).

Relevant Theory:

A field-programmable gate array is a semiconductor device containing programmable

logic components called "logic blocks", and programmable interconnects. Logic blocks

can be programmed to perform the function of basic logic gates such as AND, and XOR,

or more complex combinational functions such as decoders or simple mathematical

functions. In most FPGAs, the logic blocks also include memory elements, which may be

simple flip-flops or more complete blocks of memories.

A hierarchy of programmable interconnects allows logic blocks to be interconnected as

needed by the system designer, somewhat like a one-chip programmable breadboard.

Logic blocks and interconnects can be programmed by the customer/designer, after the

FPGA is manufactured, to implement any logical function—hence the name "field-

programmable".

FPGAs are usually slower than their application-specific integrated circuit (ASIC)

counterparts, as they cannot handle as complex a design, and draw more power. But their

advantages include a shorter time to market, ability to re-program in the field to fix bugs,

and lower non-recurring engineering costs. Vendors can sell cheaper, less flexible

versions of their FPGAs which cannot be modified after the design is committed. The

designs are developed on regular FPGAs and then migrated into a fixed version that more

resembles an ASIC. Another alternative are complex programmable logic devices

(CPLDs).

Architecture

The typical basic architecture consists of an array of configurable logic blocks (CLBs)

and routing channels. Multiple I/O pads may fit into the height of one row or the width of

one column in the array. Generally, all the routing channels have the same width (number

of wires).

An application circuit must be mapped into an FPGA with adequate resources.

A classic FPGA logic block consists of a 4-input lookup table (LUT), and a flip-flop, as

shown below. In recent years, manufacturers have started moving to 6-input LUTs in

their high performance parts, claiming increased performance.

http://en.wikipedia.org/w/index.php?title=I/O_pad&action=edit


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Logic block

There is only one output, which can be either the registered or the unregistered LUT

output. The logic block has four inputs for the LUT and a clock input. Since clock signals

(and often other high-fanout signals) are normally routed via special-purpose dedicated

routing networks in commercial FPGAs, they and other signals are separately managed.

For this example architecture, the locations of the FPGA logic block pins are shown

below.

Logic Block Pin Locations

Each input is accessible from one side of the logic block, while the output pin can

connect to routing wires in both the channel to the right and the channel below the logic

block.

Each logic block output pin can connect to any of the wiring segments in the channels

adjacent to it.

Similarly, an I/O pad can connect to any one of the wiring segments in the channel

adjacent to it. For example, an I/O pad at the top of the chip can connect to any of the W

wires (where W is the channel width) in the horizontal channel immediately below it.

Generally, the FPGA routing is unsegmented. That is, each wiring segment spans only

one logic block before it terminates in a switch box. By turning on some of the

programmable switches within a switch box, longer paths can be constructed. For higher

http://en.wikipedia.org/wiki/Image:Logic_block2.svg



http://en.wikipedia.org/wiki/Image:Logic_block_pins.svg


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speed interconnect, some FPGA architectures use longer routing lines that span multiple

logic blocks.

Whenever a vertical and a horizontal channel intersect there is a switch box. In this

architecture, when a wire enters a switch box, there are three programmable switches that

allow it to connect to three other wires in adjacent channel segments. The pattern, or

topology, of switches used in this architecture is the planar or domain-based switch box

topology. In this switch box topology, a wire in track number one connects only to wires

in track number one in adjacent channel segments, wires in track number 2 connect only

to other wires in track number 2 and so on. The figure below illustrates the connections in

a switch box.

Switch box topology

Modern FPGA families expand upon the above capabilities to include higher level

functionality fixed into the silicon. Having these common functions embedded into the

silicon reduces the area required and gives those functions increased speed compared to

building them from primitives. Examples of these include multipliers, generic DSP

blocks, embedded processors, high speed IO logic and embedded memories.

FPGAs are also widely used for systems validation including pre-silicon validation, post-

silicon validation, and firmware development. This allows chip companies to validate

their design before the chip is produced in the factory, reducing the time to market.

Manufacturers and their specialties

As of late 2005, the FPGA market has mostly settled into a state where there are two

major "general-purpose" FPGA manufacturers and a number of other players who

differentiate themselves by offering unique capabilities.

http://en.wikipedia.org/wiki/Image:Switch_box.svg


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Xilinx and Altera are the current FPGA market leaders. Xilinx also

provide free Linux design software.

Lattice Semiconductor provides both SRAM and non-volatile, flash-based

FPGAs.

Actel has antifuse and reprogrammable flash-based FPGAs, and also

offers mixed signal flash-based FPGAs.

Atmel provides fine-grain reconfigurable devices, as the Xilinx XC62xx

were. They focus on providing Atmel AVR Microcontrollers with FPGA

fabric on the same die.

QuickLogic has antifuse (programmable-only-once) products and heavily

focused on military applications.

Achronix Semiconductor has very fast FPGAs in development, focusing

on speeds approaching 2 GHz.

MathStar offers an FPGA-like device called an FPOA (field

programmable object array).

Conclusion:

FPGAs are studied in detail.


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ASSIGNMENT No: 19

Title of Assignment: VHDL modeling

Theory:


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Design Analysis/ Implementation Logic:

Sample Codes:

1. `timescale 10 ns / 1 ns

module counter;

reg clock;


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integer count;

initial begin

clock = 0; count = 0;

#340 $finish;

end

always

#10 clock = ~clock ;

always begin

@ (negedge clock);

if ( count == 7 )

count = 0 ;

else

count = count + 1 ;

$display ("time = ", $time, " Count = ", count);

end

endmodule

2. ripple counter:

`timescale 10 ns/ 1 ns

module ripple_carry_counter(q, clk, reset);

output [3:0] q;

input clk, reset;

//4 instances of the module TFF are created.

TFF tff0(q[0],clk, reset);

TFF tff1(q[1],q[0], reset);



endmodule

.

Testing:

Test the output waveforms for the correctness of the implementation.

Conclusion:

Counters successfully implemented using VHDL.

del manual

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