delay analysis of series-connected mosfet...
TRANSCRIPT
Delay Analysis of Series-Connected MOSFET Circuits
By Peng Gao
What They Did in This Paper
1. Series-Connected MOSFET Structure(SCMS) is analyzed.
2. A nth power law MOS Model for short-channel device is introduced.
Nth Power law MOS model
VT0 is zero back-gate bias threshold voltage
n, m, K and B are empirical constant
Inverter Example
ID is drain current when VGS=VDS=VDD
VD0 is drain saturation voltage when VGS=VDD
Series-connected MOSFET
Series-connected MOSFET
Vin,ap is ramp input signal
Transition Time Definition
tT0: input transition time Co output capacitance
The Fast Changing Signal
The VD0 , λ’ are approximated by 1/2+λ’/7, so there will be a tiny error.
Slow Changing Signal
The two signal can be connected by tT0’ , That’s
how we get tT0’.
Comparison of Calculated Delay
Delay Degradation Factor(DDF) with Large Output Cap
FD (DDF) ratio of the delay of SCMS to a single MOS
When N=2
How to Get DDF
Curve of upper MOS will pass (UM ,IU)and (0,ID0)two points.
Curve of the lower MOS will pass (UM ,IL) and (0,0) two points.
By Solving the intersection of L and U we get B6, and assume λ is small we get B7, the one we used in this paper.
FD =N ?
Because of the nonlinear nature of MOSFET,
the FD =N is a ideal case for long channel device.
With Small Output Cap.
FD = N2
General Case
Capacitance ratio is unchanged.
Current ratio is improved.
Delay Dependence on Input Terminal Position
Small output Cap: Show in the figure.
Large output Cap: Lower terminal will be fast.