delay testing - computer systems & reliable soc...
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Delay Testing
Sungho Kang
Yonsei University
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2CS&RSOC YONSEI UNIVERSITY
Outline
IntroductionDelay Fault ModelsTest Strategy Test Pattern GenerationFault SimulationConclusion
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3CS&RSOC YONSEI UNIVERSITY
IntroductionDelay Testing
Delay FaultsFailures that cause circuits to malfunction at desired clock rates or not meet timing specificationsModeled defects that cause signal propagation delays in a circuit to increase above the modeled delays
Delay TestingChecks if a circuit has delay faults or notDetermines input patterns to be applied to detect and locate delay defectsRequires at least two clock cyclesVarious types according to hardware models
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4CS&RSOC YONSEI UNIVERSITY
Delay Fault ModelsGate Delay Fault Model
Localized defects onlyThe number of faults is proportional to the number of inputs and outputs of gatesCannot test distributed delay defectsEasy to testAll possible single GDF can be considered
x1
x2
x3
x4
x5
x6
x7
1100
XX
XX
XX
11
11
00G1
G2
G3
G5
G6
11
XXG4
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Delay Fault ModelsPath Delay Fault Model
Can test both lumped & distributed defectsEffective in statistical design philosophyLarge number of paths
x1
x2
x3
x4
x5
x6
x7
1100
XX
XX
XX
11
11
11G1
G2
G3
G5
G6
G4
11
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Delay Fault ModelsSegment Delay Fault ModelHybrid type of gate and path delay models
Slow-to-rise and slow-to-fall defects on segment, whose length L can be chosen from statistics about the manufacturing defectsFault list will comprise of all segments of length L and all paths whose entire length is less than LPrevent an explosion of the number of faults being consideredA defect over a segment is large enough to affect any path passing through it
x1
x2
x3
x4
x5
x6
x7
11
00
XX
11
G1
G2
G3
G5
G6
G4XX
XXXX
00 11
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7CS&RSOC YONSEI UNIVERSITY
Test Strategy
InputsInput
LatchesCombinational
CircuitsOutputLatches Outputs
Input Clock Output Clock
t0V1
applied
t1V2
applied
t2outputssampled
Tc
Input Clock
SamplingClock
Hardware Model for Delay Testing
Failures that cause logic circuits to malfunction at desired clock rates or not meet timing specification
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Test Strategy
G1
G2
G3
G4
11
11A
B
C
D
E
F
G5
00
11
11
00
XX
Test Strategy of Static Gates
Two pattern test
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9CS&RSOC YONSEI UNIVERSITY
Test StrategyCombinational Circuits
Application of two patternsTests <V1, V2>, <V2, V3>, ....Apply V1 and let the signal settleApply V2 and sample outputs after desired timeLet the circuit settle under V2Apply V3 and sample outputs after desired time
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Test StrategySequential Circuits
Pure sequential circuitsUse fast and slow clocksToo difficult
Enhanced scan designsRequire additional chip areaUse the same strategy as for combinational circuitsLonger test time
Standard scan designsDifficult to handle sequential part of the circuitScan shifting Functional Justification
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Test StrategyStandard Scan Designs
Same test application strategy except that the states are now shifted in, which implies that the state variable portion of V(i+1) be a (single) shift of V(i)
Scan shifting
0
1
0
A
B0 1
1 0
0
1
0
0
1 0
0 0
1
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Test Strategy
FF
FF
01
S0
X1
S11X
1X
A
B
C
D
Standard Scan Designs
Functional JustificationThe first vector can be scanned into flip-flopsThe second vector is determined by function of circuits
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Test StrategyNon-standard Scan Designs
Tests <V1, V2>, <V2, V3>, ...Use a third latch to hold V(I) while V(I+1) is being shifted inThis makes the test application time identical to that of combinational logic circuit with exception of shifting in the state variables for V(I+1)
Initializing faulty circuit may require slowing down the clockFault effect propagation may require slowing down the clockAt speed testing may be feasible in initializable circuitsIn the case of non-initializable circuits, single gate fault assumption may be necessary
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14CS&RSOC YONSEI UNIVERSITY
Test Strategy
clock
input
T T Ts s f T Ts s
4 51 2 3
Test Strategy for Path Delay Faults
Test Application
At-speed TestingAssumption : All signal-transitions settle within one clock cycle after they were initiated
clock
input
synch 1 2 3T T Tf f f
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Test StrategyTypes of Path Delay Tests
Hazard Free Robust Test [HFR]Guarantees the signals on the path are free from dynamic hazardsGuarantees to detect the delay defects independent of the delaysin other circuits
Robust Test [ROB]Guarantees to detect the delay defects independent of the delaysin other circuits
Weak Non-Robust TestGuarantees to detect the delay defects if all off-path inputs reach their final values prior to the on-path transition
Strong Non-Robust TestBecomes ROB if off-path inputs do not have static hazards, otherwise becomes WNR
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Test StrategyLocal Requirements of Tests
Hazard Free RobustHazard free constant values for all off path inputs
RobustFirst vector : On-path elements must have initial values according to the specified transition typesSecond vector : On-path elements must have final values due to the on-path fanin values
Non RobustFirst vector : The first element on the path must have initial values according to the specified transition typesSecond vector : On-path elements must have final values due to the on-path fanin values
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Test StrategyTest Strategy
Advantages of Robust TestsInaccuracies in circuit delay models toleratedTests valid even if the technology or clock rate or layout changes occur, as long as the logical topology is not changedUsed for binning
Off-path sensitizing inputsLet P be a path in a logic circuit and G be a gate on the pathThe inputs to G that are not on the path P
Delay faults vs stuck-at faultsThe robust and non robust tests defined are such that V2 in a two pattern test set <V1, V2> for slow-to-rise (slow-to-fall) fault, is a test for s-a-0 (s-a-1) fault on root lead of the path being tested of <V1, V2> is a path delay fault test and on the lead tested if <V1, V2> is a gate delay fault test
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ATPGATPG for Path Delay Faults
Reddy, Lin and PatilLine justification objectives are known right at the beginningPath delay faults in combinational circuits only5 value logicS0, S1, U0, U1, XX
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ATPGDSTEED
Cheng, Devadas and KeutzerScan DesignsFunctional JustificationOn-sets and Off-setsVery memory intensive
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ATPGFASTPATH
Scan Based Microprocessor DesignPath Delay ModelsSet of Longest PathsBinningLeast Memory Intensive Approach
Reverse Time ProcessingBegin with last time frame and proceed backward in timestate transition : transfer logic values between outputs and inputs of flip-flops
The most restrictive test is considered first
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ATPGLogic Values
28-Valued LogicAll Combinations of 0,1, X and Z
00 01 0X 0Z 10 11 1X 1Z X0 X1 XX XZ Z0 Z1 ZX ZZLogic Y : Constrained X + ZStable Values
S0 S1 SZStable Impossible Values
00T 0XT X0T XT0 11T 1XT X1T XT1 XTBTypes of 0
Hazard status undetermined (00)Hazard free zero (S0)Possible hazard (00T)
S1
00
00 00T
01 10
S0S0 01
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ATPG
X1T(X1)
1X
10XX
01
0X
XTB(XX)AB
C
D 11
S1
Logic Values
Stable Impossible Values00T, 0XT, X0T, XT0, 11T, 1XT, X1T, XT1 and XTBT Indicates the signal would not be stable through both time framesCan avoid unsuccessful searchesSpecify unjustifiable values
S0
XXS0
X0
0X 00
10
10
01
00T
A
B
C
D
E
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ATPG
O f f -p a th R e q u ir e m e n tsE le m e n ts O n -p a th
T r a n s it io n H F R R O B S N R W N R
R is in g S 1 X 1 X 1 X 1A N DN A N D F a ll in g S 1 S 1 1 1 X 1
R is in g S 0 S 0 0 0 X 0O RN O R F a ll in g S 0 X 0 X 0 X 0
Requirements of Tests
Requirements HierarchyWNR < SNR < ROB < HFR
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ATPG
Generate(){ for(I=0; I<Num_paths; I++){ path = read_path(); flag=find_one_test(path,HFR); if(flag!=TEST_GENERATE){ flag=find_one_test(path,ROB); if(flag!=TEST_GENERATE){ falg=find_one_test(path,SNR); if(flag!=TEST_GENERATE) falg=find_one_test(path, WNR); } } }}
find_one_test(path, test_type){ flag=set_constraints(path, test_type); if(flag==UNTESTABLE || flag==ABORTED)
return(flag); flag=implication(); if(flag==UNTESTABLE || flag==ABORTED)
return(flag); flag=justification(); if(flag==UNTESTABLE || flag==ABORTED)
return(flag); else
mark_success(path);}
Test Generation Algorithm
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ATPG
FF1
FF2
AB
CD
E
F
G
H
I
J
K
L
M
01
10
01
10
•Path:B-G-J-L•Signal Name
•On-path Transition
FASTPATH Example
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ATPG
FF1
FF2
AB
CD
E
F
G
H
I
J
K
L
M
01
10
01
10S1*
X1*
S0*00T
•Path: B-G-J-L•Signal Name
•On-path Transition
•Off-path Constraints
•Implication
FASTPATH Example
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ATPG
FF1
FF2
AB
CD
E
F
G
H
I
J
K
L
M
01
10
01
10S1*
X1*
S0*
S1
S1
00T
S0S1
S0
•Path:B-G-J-L•Signal Name•On-path
Transition•Off-path
Constraints•Implication•Stable Value•Implication•Justification
FASTPATH Example
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ATPG
FF1
FF2
AB
CD
E
F
G
H
I
J
K
L
M
01
10
01
10S1*
X1*
S0*
S1
S1
1X
00T
01
S0S1
S0
•Path:B-G-J-L•Signal Name•On-path
Transition•Off-path
Constraints•Implication•Stable Value•Implication•Justification•Second TF•Implication•First TF•ImplicationA B C D FF1 FF2
Initial Vector 0 1 1 1 X XSecond Vector 0 0 1 1
FASTPATH Example
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Fault SimulationDelay Fault Simulation
Ensures target faults are tested by the generated vectorsOther sources of vectors
Functional vectorsVectors that designers provide
Useful for large sequential circuits
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Fault SimulationFASTPATH Fault Simulation
Standard scan designs4 logic values : 0 1 X ZSet data structures to hold data for 2 clock cyclesCompute a steady value flag during second clock cycleAdvantages
Each bit in a machine word represents a separate patternEach pattern cycle treated as independent of all othersEvaluating sequential devices is a single word copyCircuit inputs loaded only once for each patternEach pattern is evaluated for the same number of clock cycles which is known in advance
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Fault SimulationFASTPATH Fault Simulation
AlgorithmGood simulationHazard free robust fault detectionRobust fault detectionStrong non robust fault detectionWeak non robust fault detection
Logic Value Encoding ( i:time frame, j:fanin)bvi[j] xvi[j]
0 0 01 1 0X 1 1Z 0 1
Steady Value Mark
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Fault Simulation2 input AND (on path : fanin 0)
Parallel Evaluation RoutineXVout[t]=XV0[t]&BV1[t] | XV1[t]&BV0[t] | XV [t]&XV1[t]BVout[t]=XVout[t] | (BV1[t] & BV0[t] )
Steady Value Mark EvaluationSVout = (~XV0[0] & ~BV0[0] & ~XV0[1] & ~BV0[1] & SV0 ) | (~XV1[0] & ~BV1[0] & ~XV1[1] & ~BV1[1] & SV1 ) | (~XV0[0] & BV0[0] & ~XV0[1] & BV0[1] & SV0 & ~XV1[0] & BV1[0] & ~XV1[1] & ~BV1[1] & SV1 )
Robust TestsRising : BV1[1] & ~XV1[1]Falling : BV1[0] & ~XV1[0] & BV1[1] & ~XV1[1] & SV1
Strong Non Robust TestsRising : BV1[1] & ~XV1[1]Falling : BV1[0] & ~XV1[0] & BV1[1] & ~XV1[1]
Weak Non Robust TestsRising : BV1[1] & ~XV1[1]Falling : BV1[0] & ~XV1[0]
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ConclusionConclusion
Cost effective delay fault testingUse transition fault model to generate testsEvaluate the small delay defect coverage of the tests derived for transition faultsDerive and apply robust tests for as many longest delay paths asone can afford