For U.S.A., Canada, Europe & Japan model

SERVICE MANUAL

Ver. 1

MODEL

S-301

DVD HOME THEATER SYSTEM

HOME THEATER SYSTEM (S-301) consists of DVD SURROUND RECEIVER (ADV-S301) and SUB WOOFER (DSW-S301) and SPEAKER SYSTEM (SC-S301)

For purposes of improvement, specifications and design are subject to change without notice.

8

Please use this service manual with referring to the operating instructions without fail.

Some illustrations using in this service manual are slightly different from the actual set.

TOKYO, JAPAN Denon Brand Company, D&M Holdings Inc.X0245 V.01 DE/CDM 0508

S-301

SAFETY PRECAUTIONSThe following check should be performed for the continued protection of the customer and service technician.

LEAKAGE CURRENT CHECKBefore returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the power cord is less than 460 kohms, the unit is defective.

LASER RADIATIONDo not stare into beam or view directly with optical instruments, class 3A laser product.

500 1

(1) (2)

(1) (2)

2

S-301

DISASSEMBLY(Follow the procedure below in reverse order when reassembling.)

1. Loader Panel(1) Switch on, and press [ to open the Disc tray. (OPEN/CLOSE)] button

1. (1) (OPEN/CLOSE) (2)

(2) Detach the Loader Panel by lifting.

2. Side Panel, Bottom Cover(1) Remove 13 bottom screws. (2) Remove 7 rear screws, then detach Side Panel and Bottom Cover.

2. (1) 13 (2) 7

3

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3. Top Cover(1) Remove 9 top screws, then detach Top Cover.

3. (1) 9

4. Front Panel Assy(1) Remove 3 Front panel screws, then detach P.W.B. and chassis. (2) Remove 4 Front panel side screws, then detach the Front Panel Assy.

4. (1) 3 (2) 4 2

5. Front Panel Assy(1) Remove each terminal screws, Back Panel screws and Chassis screws, then detach the Back Panel.

5. (1)

4

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6. DVD Mecha(1) Remove 4 screws, then detach P.W.B.(1U-3695-1, 1U-3695-2, 1U-3695-3) and TUNER PACK.

6. DVD (1) 4 1U-3695-1 1U-3695-2 1U-3695-3 TUNER PACK

1U-3695-3 TUNER PACK 1U-3695-1

1U-3695-2

(2) Remove 6 screws, then detach 1uU-3692 P.W.B. with DVD mecha from bottom chassis.

(2) 6 1U-3692 DVD

DVD mecha 1U-3692

5

S-301

7. Traverse Unit DisassemblyCaution: The optical pickup can be damaged easily by static electricity charged on human body. Take necessary anti-static measures when repairing around the optical pickup.

7.

7.1. Guide Clamp Bracket disassembly(1) Remove 2 screws. (2) Remove Guide Clamp Bracket to arrow direction.

7.1. (1) 2 (2)

7.2. Tray disassembly(1) Remove to arrow direction. (2) Solder the short-circuit (see in the frame).

7.2. (1) (2) )

6

S-301

7.3. Traverse Unit disassembly(1) Remove 24P FFC (CX241), 15P FFC (CX151), 5P PH WIRE (CX051) connecting with from 1U-3692 P.W.B. (2) Remove 4 screws fixing Damper. (3) Remove Traverse Unit to arrow direction.

7.3. (1) 1U-3692 24P FFCCX241) 15P FFCCX151) 5P PH CX051) (2) 4 (3)

1U-3692 P.W.B.

Note for disassembly Traverse Unit(1) When assembling, reverse the order of the above. (2) When inserting Tray, confirm boss on Slide Cam set to ditch of the Tray (Compare with below drawing).

(1) (2)

7

S-301

DIAGNOSTICS OF OPTICAL PICKUP AND REPLACING TRAVERSE UNITMake failure diagnostics of the Optical Pickup as follows. If the laser drive current (Iop) becomes more than 1.5 times of the initial value, the Optical Pickup should be replaced. The laser drive current is registered on the seal attached to the rear of the Mecha.Unit. In case of replacing the Pickup, change the whole part of the Traverse Unit. No mechanical adjustment is necessary after the replacement.

Iop 1.5

Example: DVD 30mA CD 30mA

Disc no read, unsteady playback, etc.

Laser drive current (Iop) check HF wave form check (Refer to WAVE FORMS)

Iop WAVE FORMS

Present value exceeds the initial value by 1.5 times

1.5

Traverse Unit replacing (See page 6, 7 for details)

6, 7

Laser current registering after replacement.

Step: Disc playback Write the measured value on the seal attached to the Mecha. Unit * As to the measuring method, refer to page 9, 10.

Iop * Iop 9, 10

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S-301

1. Label Indication of SACD Mechanism.

1. SACD

Laser current consumption value ex) DVD mA, CD mA

DVD mA, CD mA

2. Note for Handling the Laser Pick-UpThe protection for the damage of laser diode. If you want to change the optical device unit from any other units, you must keep the following. (1) It should be done at the desk already took measures the static electricity in care of removing the OPU's (Optical device unit) connector cable. (2) Workers should be put on the "Earth Band". (3) It should be done to add the solder to the short land to prevent the broken Laser diode before removing the 24P FFC cable. (4) Don't touch OPU's connector parts carelessly.

2. (1) (2) (3) 24P FFC (4)

3. Replacement of the Laser Pick-up (Traverse Unit)Check the Iop (Laser drive current) If the present Iop (current) value exceeds.+150% of the initial value, replace the Traverse unit (Laser Pick-up) with a new one.

3. ( ) Iop( Iop 150

4. Iop Measurement MethodWhen measuring Laser drive current (Iop), playback the discs (CD,DVD) described below, measure Iop for CD Laser and DVD Laser by the test point (+5V-A2~ LD (CD), LD (DVD))on the Main P.W.B.

4. Iop CD,DVD) Main (+5V-A2 LD (CD), LD (DVD)) CD DVD Iop DVD/DVDT-S01 CD/TCD-784 ALMEDIO

Test Disc : DVD/DVDT-S01 or commercially available discs. : CD/TCD-784 (manufactured by ALMEDIO INC) or commercially available discs.

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4.1. DVD Laser current measurementLD (DVD) +5V-A2 Oscilloscope (1) Connect the oscilloscope to +5V-A2 of test point for GND side and LD (DVD) of test point for signal side. (2) Playback the multi layer track 1 of the DVD Test Disc. (3) Measure the voltage between +5V-A2 and LD (DVD), calculate Iop by the formula as shown below.

4.1. DVD LD (DVD) +5V-A2 Oscilloscope (1) +5V-A2 (GND) LD (DVD) ( ) (2) DVD 1 (3) +5V-A2 LD (DVD) Iop

Measurement Voltage Value Iop = ---------------------------------------------------------------------------14 (Resistance value)

Iop = ---------------------------14()4.2. CD (1) +5V-A2 (GND) LD (CD) ( ) (2) CD 1 (3) +5V-A2 LD (CD) Iop

4.2. CD Laser current measurement(1) Connect the oscilloscope to +5V-A2 of test point for GND side and LD (CD) of test point for signal side. (2) Playback the track 1 of the CD Test Disc. (3) Measure the voltage between +5V-A2 and LD (CD), calculate Iop by the formula as shown below.

Measurement Voltage Value Iop = ---------------------------------------------------------------------------11.75 (Resistance value)

Iop = ----------------------------------11.75()

+5V_A2

LD(CD)

LD(DVD)

1u-3692 foil side

10

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Special operating procedures1. Initialization This initializes the data for the function, volume,

1. VOL DVD (RL-874)

DVD mechanism (RL-874), etc. (1) Check that the AC cord is disconnected from the power outlet. (AC OFF) (2) While pressing the FUNCTION and OPEN/CLOSE ( ) buttons on the main unit, plug the AC cord into the power outlet. (AC ON) (3) Check that the entire display and all the LEDs light, then release the FUNCTION and OPEN/CLOSE ( ) buttons. (4) After about 3 seconds, "INITIALIZE" appears on the display. (5) After initialization is complete (when "INITIALIZE" turns off), the function is set to "DVD" and the volume level is set to - ("-dB" is displayed).

(1) AC (AC OFF) (2) FUNCTION OPEN/CLOSE ( ) AC (AC ON) (3) LED FUNCTION OPEN/CLOSE ( ) (4) 3 "INITIALIZE" (5) ("INITIALIZE" ) FUNCTION "DVD" VOL - ( "---dB")

2. System check mode Use this to display the version information, etc.

2.

(1) In the standby mode, while pressing the STOP ( ) and A.FWD ( ) buttons on the main unit, press the ON/STANDBY button. (2) Press the STATUS button on the remote control unit (RC-1005 or RC-1006) to display the following information, in this order: Time (TIME) System microprocessor version (SYS Ver) Date of system microprocessor version updating (SYS Date) DSP version (DSP Ver) Date of DSP version updating (DSP Date) Date of drive microprocessor version updating (Dr Date) ESS version (Ess Ver) Date of ESS version updating (Ess Date) Region number (Region No.) (3) To cancel, unplug the AC cord. (AC OFF) NOTE 1: The DVD mechanism driver version and ESS version are not displayed unless the function is once set to DVD.

(1) STANDBY STOP A.FWD ON/STANDBY (2) RC-1005 or RC-1006 STATUS (TIME) (SYS Ver) (SYS Date DSP (DSP Ver) DSP (DSP Date) (Dr Date) ESS (Ess Ver) Ess (Ess Date) (Region No.) (3) AC (AC OFF) ( 1) DVD ESS 1 DVD

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ADJUSTMENT1. SETTING(1) Connect the oscilloscope to the Y-signal, PB-signal and CB-signal, PR-signal and CR-signal of ZONE2 COMPONENT OUT terminal and each terminate at 75 Ohms. Use the 75 Ohms resistance must be 1% (2) DVD test disc : DVDT-S01 (3) S OUT of DVD player is connected to AUX1 S IN.

1. (1) ZONE2 COMPONENT OUT Y, PB/CB, PR/CR 75 75 1 (2) DVD DVDT-S01 (3) DVD S OUT AUX1 S IN

2. Before Adjustment 2.1. Setting the Oscilloscope as below.(1) PB/CB, PR/CR (a) TIME/DIV : 10s (b) VOLT/DIV : 100mV (Use the probe : x10 ) (2) Y (a) TIME/DIV : 10s (b) VOLT/DIV : 200mV (Use the probe : x10 ) Power on. Power Supply USA & Canada : 120V Europe : 230V Japan : 100V China & Korea : 220V

2. 2.1. (1) PB/CB, PR/CR (a) TIME/DIV : 10s (b) VOLT/DIV : 100mV x10 (2) Y (a) TIME/DIV : 10s (b) VOLT/DIV : 200mV x10 100V

2.2. Setup the DVD player and confirmation of the stators(1) Set to "INTERLACED" mode at the COMPONENT OUT. (2) Confirm the DVD players out put level is equal as the item 2.4. in following.

2.2. DVD (1) COMPONENT OUT "" (2) DVD 2.4.

2.3. Preparation(1) Push the FUNCTION knob to select "AUX1" input. (2) Push [OPEN/CLOSE] button of DVD player, then open the Disc Tray. Set DVD test disc (DVDT-S01) on the Disc Tray, and then push [CLOSE] button. (3) DVD player FL display appear "STOP", push [PLAY] button to playback DVD. (4) Push the [DISPLAY] button of remote control of DVD player unit and then appear the ON-Screen Display (GUI) on the monitor TV. (5) Push the [+10] and [2] button, select Title 12 of DVD. (6) Push the [ENTER] button, playback Title 12. (color bar 75%)

2.3. (1) FUNCTION "AUX1" (2) DVD OPEN/CLOSE DVD DVDT-S01 CLOSE (3) DVD "STOP" PLAY (4) DVD DISPLAY (GUI) (5) +10 , 2 Title 12 (6) ENTERTitle 12 75

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S-301 2.4. Procedure(1) Adjust the signal of COMPONENT OUT by the wave of oscilloscope. (a) Target, Y-signal Point Adjustment Value Waveform : : 1U-3695-3 VR601 714 35mV

2.4. (1) COMPONENT OUT (a) Y 1U-3695-3 VR601 714 35V

Y

Y

Y-signal COMPONENT OUT

COMPONENT OUT Y

(b) Target, PB/CB-signal Point : Adjustment Value : Waveform

1U-3695-3 VR602 *525 25mV

(b) PB/CB

1U-3695-3 VR602 525 25V

PB

PB/CB

PB/CB-signal COMPONENT OUT

COMPONENT OUT PB/CB

(c) Target, PR/CR-signal Point : Adjustment Value : Waveform

1U-3695-3 VR603 *525 25mV

(c) PR/CR

1U-3695-3 VR603 525 25V

PR/CR

PR/CR

PR/CR-signal COMPONENT OUT * : 486 10mV for U.S.A. & Canada model

COMPONENT OUT PR/CR

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BLOCK DIAGRAM IN DATP20:FL/FR DAIP19:C/SW DAIP18:SL/SR

OUT DAIP16:FL/FR DAIP16:0/SW DAIP15:0/0 DAIP14:RECL/RECR

14

LEVEL DIAGRAM

15

S-301

1. ICs

ES6138F (IC101: 1U-3692)

SEMICONDUCTORS /

VEE HA2/AUX4[4] VEE I2CDATA/AUX[0] I2C_CLK/AUX[1] AUX[2]/IOW# VSS VEE AUX[3]/IOR# AUX[4] AUX[5] AUX[6] AUX[7] LOE# VSS VCC LCS0# LCS1# LCS2# LCS3# VSS LD0 LD1 LD2 LD3 LD4 VEE VSS LD5 LD6 LD7 LD8 LD9 LD10 LD11 VSS VEE LD12 LD13 LD14 LD15 LWRLL# LWRHL# VSS VEE CAMIN0 CAMIN1 LA0 LA1 LA2 LA3 VSS

PINOUT DIAGRAM

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

Only major semiconductors are shown, general semiconductors etc. are omitted to list.

ES6138F

16

VEE LA4 LA5 LA6 LA7 LA8 LA9 VSS VCC LA10 LA11 LA12 LA13 LA14 LA15 LA16 VSS VEE LA17 LA18 LA19 LA20 LA21 RESET# TDMDX/RSEL VSS VEE TDMDR TDMCLK TDMFS TDMTSC# TWS/SEL_PLL2 TSD0/SEL_PLL0 VSS VCC TSD1/SEL_PLL1 TSD2 TSD3 MCLK TBCK SEL_PLL3/SPDIF_OUT SPDIF_IN VSS VCC RSD RWS RBCK NC XIN XOUT AVEE AVSS 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VSS HA1/AUX4[3] HA0/AUX4[2] HCS3FX#/AUX3[6] HCS1FX#/AUX3[7] HIOCS16#/CAMCLK/AUX3[4] HRD#/DCI_ACK#/AUX4[6] HWR#/DCI_CLK/AUX4[5] VEE VSS HIORDY/AUX3[3] HRST#/AUX3[5] HIRQ/DCI_ERR#/AUX4[7] HRRQ#/AUX4[0] HWRQ#/DCI_REQ#/AUX4[1] HD15/AUX2[7]/IR HD14/AUX2[6] VCC VSS HD13/AUX2[5]/SP HD12/AUX2[4]/C2PO HD11/AUX2[3]//IRQ HD10/AUX2[2] HD9/AUX2[1] HD8/DCI_FDS#/AUX2[0]/VFD_CLK HD7/DCI7/AUX1[7]/VFD_DIN VEE VSS HD6/DCI6/AUX1[6]/VFD_DOUT HD5/DCI5/AUX1[5] HD4/DCI4/AUX1[4] HD3/DCI3/AUX1[3] HD2/DCI2/AUX1[2] HD1/DCI1/AUX1[1] HD0/DCI0/AUX1[0] VCC VSS HSYNC#/CAMIN7/AUX3[0] VSYNC#/CAMIN6/AUX3[1] PCLKQSCN/CAMIN5/AUX3[2] PCLK2XSCN/CAMIN4 YUV7/FDAC/CAMIN3 YUV6/VDAC YUV5/YDAC ADVSS ADVEE YUV4/RSET YUV3/COMP YUV2/CDAC YUV1/VREF YUV0/CAMIN2/UDAC DCLK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

VEE VSS DSCK DQM DCS0# VEE VSS DCS1# DB15 DB14 DB13 DB12 VEE VSS DB11 DB10 DB9 DB8 DB7 DB6 VSS VCC DB5 DB4 DB3 DB2 DB1 DB0 VSS VEE DMBS1 DMBS0 DRAS# DWE# DOE#/DSCK_EN DCAS# VEE VSS DMA11 DMA10 DMA9 DMA8 DMA7 DMA6 VSS VEE DMA5 DMA4 DMA3 DMA2 DMA1 DMA0

S-301

S-301

ES6138F Pin DescriptionName VEE Pin Numbers 1,18, 27, 59, 68, 75, 92, 99, 104, 130, 148, 157, 159, 164, 183, 193, 201 2:7, 10:16, 19:23, 204:207 8, 17, 26, 34, 43, 60, 67, 76, 84, 91, 98, 103, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 9, 35, 44, 83, 121, 139, 172 24 I/O Definition

P

I/O power supply.

LA[21:0] VSS

O

RISC port address bus.

G

Ground.

VCC RESET# TDMDX RSEL

P I O I

Core power supply. Reset input (active-low). TDM transmit data output. LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-k resistor; read only during reset. RSEL 0 1 Selection 16-bit ROM 8-bit ROM

25

TDMDR TDMCLK TDMFS TDMTSC# TWS SEL_PLL2

28 29 30 31

I I I O O I

TDM receive data input. TDM clock input. TDM frame sync input. TDM output enable (active-low). Audio transmit frame sync output. System and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Strapped to VCC or ground via 4.7-k resistor; read only during reset. SEL_PLL2 0 SEL_PLL1 0 0 1 1 0 0 1 1 SEL_PLL0 0 1 0 1 0 1 0 1 PLL Settings DCLK 4.5 DCLK 5.0 Bypass DCLK 4.0 DCLK 4.25 DCLK 4.75 DCLK 5.5 DCLK 6.0

32

0 0 0 1 1 1 1

17

S-301pName TSD0 33 SEL_PLL0 TSD1 36 SEL_PLL1 TSD2 TSD3 NC MCLK TBCK SEL_PLL3 37 38 48 39 40 I O O I/O O I Refer to the description and matrix for SEL_PLL2 pin 32. Audio transmit serial data output 2. Audio transmit serial data output 3. No connect pins. Leave open. Audio master clock for audio DAC. Audio transmit bit clock. Clock source select. Strapped to VCC or ground via 4.7-k resistor; read only during reset. SEL_PLL3 41 0 1 Clock Source Crystal oscillator DCLK input I O Refer to the description and matrix for SEL_PLL2 pin 32. Audio transmit serial data port 1.

(

)I/O O Definition Audio transmit serial data port 0.

Pin Numbers

SPDIF_OUT SPDIF_IN RSD RWS RBCK XIN XOUT AVEE AVSS DMA[11:0] DCAS# DOE# 70 DSCK_EN DWE# DRAS# DMBS0 DMBS1 DB[15:0] DCS[1:0]# DQM 71 72 73 74 77:82, 85:90, 93:96 97,100 101 42 45 46 47 49 50 51 52 53:58, 61:66 69

O I I I I I O P G O O O O O O O O I/O O O

S/PDIF output. S/PDIF input. Audio receive serial data. Audio receive frame sync. Audio receive bit clock. 27-MHz crystal input. 27-MHz crystal output. Analog power for PLL. Analog ground for PLL. DRAM address bus. DRAM column address strobe. DRAM output enable (active-low). DRAM clock enable. DRAM write enable (active-low). DRAM row address strobe (active-low). DRAM bank select 0. DRAM bank select 1. DRAM data bus. DRAM chip select (active-low). Data input/output mask.

18

S-301pName DSCK DCLK YUV0 CAMIN2 UDAC

(102 105

)I/O O I O I O Definition Output clock to DRAM. Clock input to PLL. YUV pixel 2 output data. Camera YUV 2. Video DAC output. Pin Value 0 1 2 3 4 5 6 115 F DAC CVBS/Chroma CVBS/Chroma CVBS/Chroma CVBS/Chroma CVBS/Chroma CVBS/Chroma CVBS/Chroma N/A CVBS/Chroma CVBS CVBS N/A CVBS/Chroma CVBS/Chroma Chroma 114 V DAC CVBS1 CVBS1 N/A CVBS1 CVBS1 CVBS1 N/A SYNC Chroma CVBS1 CVBS1 SYNC N/A CVBS1 Y 113 Y DAC Y Y Y N/A N/A Y Y G Y G G G Y Y G 108 C DAC C C C N/A N/A Pb Pb B Pb B R R Pr Pr R 106 U DAC N/A CVBS2 N/A CVBS2 N/A Pr Pr R Pr R B B Pb Pb B

Pin Numbers

106 7 8 9 10 11 12 13 14

F: CVBS/chroma signal for simultaneous mode. Y: Luma component for YUV and Y/C processing. C: Chrominance signal for Y/C processing. U: Chrominance component signal for YUV mode. V: Chrominance component signal for YUV mode. YUV1 107 VREF YUV2 108 CDAC YUV3 109 COMP YUV4 110 RSET ADVEE 111 I P DAC current adjustment resistor input. Analog power for video DAC. I O O O Video DAC output. Refer to description and matrix for UDAC pin 106. YUV pixel 3 output data. Compensation input. Bypass to ADVEE with 0.1-F capacitor. YUV pixel 4 output data. I O O YUV pixel 1 output data. Internal voltage reference to video DAC. Bypass to ground with 0.1-F capacitor. YUV pixel 2 output data.

19

S-301pName ADVSS YUV5 113 YDAC YUV6 114 VDAC YUV7 FDAC CAMIN3 PCLK2XSCN 116 CAMIN4 PCLKQSCN CAMIN5 AUX3[2] VSYNC# CAMIN6 AUX3[1] HSYNC# CAMIN7 AUX3[0] HD[5:0] DCI[5:0] AUX1[5:0] HD6 DCI6 128 AUX1[6] VFD_DOUT HD7 DCI7 131 AUX1[7] VFD_DIN HD8 DCI_FDS# 132 AUX2[0] VFD_CLK I/O I Aux2 data I/O. VFD clock input. I/O I I/O I/O Aux1 data I/O. VFD data input. Host data bus line 8. DVD input sector start (active-low). I/O I I/O I/O Aux1 data I/O. VFD data output. Host data bus line 7. DVD channel data I/O. 122:127 119 118 117 I O I I/O I/O I I/O I/O I I/O I/O I/O I/O I/O I/O Camera YUV 4. 13.5-MHz video output pixel clock. Camera YUV 5. Aux3 data I/O. Vertical sync (active-low). Camera YUV 6. Aux3 data I/O. Horizontal sync (active-low). Camera YUV 7. Aux3 data I/O. Host data bus lines 5:0. DVD channel data I/O. Aux1 data I/O. Host data bus line 6. DVD channel data I/O. 115 O O O I I/O Video DAC output. Refer to description and matrix for UDAC pin 106. YUV pixel 7 output data. Video DAC output. Refer to description and matrix for UDAC pin 106. Camera YUV 3. 27-MHz video output pixel clock. O O Video DAC output. Refer to description and matrix for UDAC pin 106. YUV pixel 6 output data.

(112

)I/O G O Definition Analog ground for video DAC. YUV pixel 5 output data.

Pin Numbers

20

S-301pName HD9 133 AUX2[1] HD10 134 AUX2[2] HD11 AUX2[3] IRQ HD12 AUX2[4] C2PO HD13 AUX2[5] SP HD14 140 AUX2[6] HD15 AUX2[7] IR HWRQ# DCI_REQ# AUX4[1] HRRQ# 143 AUX4[0] HIRQ DCI_ERR# AUX4[7] HRST# 145 AUX3[5] HIORDY 146 AUX3[3] HWR# DCI_CLK AUX4[5] 149 I/O I/O I/O I/O Aux3 data I/O. Host write (active-low). DVD channel data clock. Aux4 data I/O. I/O I Aux3 data I/O. Host I/O ready. 144 I/O I/O I/O I/O O Aux4 data I/O. Host interrupt. DVD channel data error (active-low). Aux4 data I/O. Host reset (active-low). 142 141 I/O I/O I/O I O O I/O O Aux2 data I/O. Host data bus line 15. Aux2 data I/O. IR remote control input. Host write request (active-low). DVD control interface request (active-low). Aux4 data I/O. Host read request (active-low). 137 136 135 I/O I/O I/O O I/O I/O I I/O I/O I I/O Aux2 data I/O. Host data bus line 11. Aux2 data I/O. IRQ. Host data bus line 12. Aux2 data I/O. C2PO error correction flag from CD-ROM. Host data bus line 13. Aux2 data I/O. 16550 UART serial port input. Host data bus line 14. I/O I/O Aux2 data I/O. Host data bus line 10.

(

)I/O I/O Definition Host data bus line 9.

Pin Numbers

21

S-301p Name HRD# DCI_ACK# AUX4[6] HIOCS16# CAMCLK AUX3[4] HCS1FX# 152 AUX3[7] HCS3FX# 153 AUX3[6] HA[2:0] 154, 155, 158 AUX4[4:2] AUX[0] 160 I2CDATA AUX[1] 161 I2C_CLK AUX[2] 162 IOW# AUX[3] 165 IOR# AUX[6:4] AUX[7] LOE# LCS[3:0]# LD[15:0] LWRLL# LWRHL# CAMIN0 CAMIN1 166:168 169 170 173:176 178:182, 185:191,194:197 198 199 202 203 O I/O I/O O O I/O O O I I I/O read strobe (LCS1) (active-low). Auxiliary ports. Auxiliary port. RISC port output enable (active-low). RISC port chip select (active-low). RISC port data bus. RISC port low-byte write enable (active-low). RISC port high-byte write enable (active-low). Camera YUV 0. Camera YUV 1. O I/O I/O write strobe (LCS1) (active-low). Auxiliary port. I/O I/O I2C clock I/O. Auxiliary port. I/O I/O I2C data I/O. Auxiliary port 1 (open collector). I/O I/O Aux4 data I/Os. Auxiliary port 0 (open collector). I/O I/O Aux3 data I/O. Host address bus. I/O O Aux3 data I/O. Host select 3 (active-low). 151 150 ( Pin Numbers ) I/O O O I/O I I I/O O Definition Host read (active-low). DVD channel data valid (active-low). Aux4 data I/O. Device 16-bit data transfer (active-low). Camera port pixel clock input. Aux3 data I/O. Host select 1 (active-low).

22

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FLI2310 (IC403: 1U-3692)Pin Diagram

FIELD ID_PORT2 D1_IN_7 D1_IN_6 D1_IN_5

IN_CLK_PORT2

HSYNC_PORT2

AVDD_PLL_BE2 AVDD_PLL_BE1 AVSS_PLL_BE1

VSYNC_PORT2

AVSS_PLL_SDI AVSS_PLL_BE2

R_VSS AVSS_PLL_FE AVDD_PLL_FE

AVDD_PLL_SDI

170

205

200

195

190

185

175

HSYNC1_PORT1 VSYNC1_PORT1 FIELD ID1_PORT1 IN_CLK1_PORT1 HSYNC2_PORT1 VSYNC2_PORT1 FIELD ID2_PORT1 VDD1 VSS IN_CLK2_PORT1 B/Cb/D1_0 B/Cb/D1_1 B/Cb/D1_2 B/Cb/D1_3 B/Cb/D1_4 VDDcore1 VSScore B/Cb/D1_5 B/Cb/D1_6 B/Cb/D1_7 R/Cr/Cb Cr_0 R/Cr/Cb Cr_1 R/Cr/Cb Cr_2 R/Cr/Cb Cr_3 R/Cr/Cb Cr_4 R/Cr/Cb Cr_5 R/Cr/Cb Cr_6 R/Cr/Cb Cr_7 G/Y/Y_0 VDD2 VSS G/Y/Y_1 G/Y/Y_2 G/Y/Y_3 G/Y/Y_4 VDDcore2 VSScore G/Y/Y_5 G/Y/Y_6 G/Y/Y_7 IN_SEL TEST DEV_ADDR1 DEV_ADDR0 SCLK SDATA RESET_N VDD3 VSS SDRAM DATA(0) SDRAM DATA(1) SDRAM DATA(2)

1 155

180

165

160

PLL_PVSS

Reserved Reserved Reserved

Reserved

R_VDD Reserved

R_VDD

PLL_PVDD

VDD9 XTAL OUT

R_VDD1.8

VDDcore8 D1_IN_0

VSScore

R_VDD

Reserved R_VSS

D1_IN_4 D1_IN_3 D1_IN_2 D1_IN_1

XTAL IN TEST2

R_VSS R_VSS

R_VSS R_VDD

R_VDD

R_VSS

R_VSS

R_VDD

TEST1

TEST0

R_VSS

VSS

OE G/Y/Y_OUT_7 G/Y/Y_OUT_6 G/Y/Y_OUT_5 G/Y/Y_OUT_4

5 150

G/Y/Y_OUT_3 G/Y/Y_OUT_2 G/Y/Y_OUT_1 G/Y/Y_OUT_0

10 145

VSS VDD8 R/V/Pr_OUT_7 R/V/Pr_OUT_6 R/V/Pr_OUT_5

15 140

R/V/Pr_OUT_4 R/V/Pr_OUT_3 R/V/Pr_OUT_2 VSScore VDDcore7 R/V/Pr_OUT_1 R/V/Pr_OUT_0

20 135

B/U/Pb_OUT_7 B/U/Pb_OUT_6 B/U/Pb_OUT_5 B/U/Pb_OUT_4

25 130

B/U/Pb_OUT_3 B/U/Pb_OUT_2 VSS VDD7 B/U/Pb_OUT_1

30 125

B/U/Pb_OUT_0 CLKOUT VSScore VDDcore6 CTLOUT4

35 120

CTLOUT3 CTLOUT2 CTLOUT1 CTLOUT0 TEST OUT1 TEST OUT0

40 115

TEST3 SDRAM CLKIN VSS VDD6

45 110

SDRAM CLKOUT SDRAM DQM SDRAM CSN SDRAM BA0 SDRAM BA1

50 100 85 90 70 80 95 105

SDRAM CASN SDRAM RASN

65

55

SDRAM DATA(3)

SDRAM DATA(4)

SDRAM DATA(5)

60

75SDRAM DATA(23) SDRAM DATA(24)

SDRAM DATA(31)

SDRAM DATA(6) SDRAM DATA(7)

SDRAM DATA(8)

SDRAM DATA(20) SDRAM DATA(21)

SDRAM DATA(25)

VSScore SDRAM DATA(26)

SDRAM DATA(27)

SDRAM DATA(9) SDRAM DATA(10)

SDRAM DATA(12)

SDRAM DATA(13)

SDRAM DATA(14)

SDRAM DATA(15) VDDcore3 VSScore SDRAM DATA(16)

SDRAM DATA(17)

SDRAM DATA(18) SDRAM DATA(19)

SDRAM DATA(28)

SDRAM ADDR(9)

SDRAM ADDR(8) SDRAM ADDR(7)

SDRAM ADDR(6)

SDRAM ADDR(5) SDRAM ADDR(4)

SDRAM ADDR(3)

SDRAM ADDR(2)

SDRAM ADDR(1)

SDRAM DATA(22)

SDRAM DATA(29)

SDRAM DATA(11)

SDRAM DATA(30)

TEST IN SDRAM ADDR(10)

SDRAM ADDR(0)

VDDcore4

VDDcore5 VSScore

VDD4

VSS

VDD5 VSS

Block DiagramsPort 2 8-bit 656 Input Port 1 8/16/24-bit RGB/YCrCb Input

Input Processor with Auto Sync and auto Adjust

Noise Reducer, Deinterlacer, Frame Rate Converter and SDRAM interface

Vertical and Horizontal Scalers

Output Processor 16/20/24-bit RBG/YCrCb Digital Outputs

Clock Generation PLLs

2Mx32 SDRAM (external)

Vertical and Horizontal Enhancers

23

SDRAM WEN

S-301

Pin detailsPin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name HSYNC1_PORT1 VSYNC1_PORT1 FIELD ID1_PORT1 IN_CLK1_PORT1 HSYNC2_PORT1 VSYNC2_PORT1 FIELD ID2_PORT1 VDD1 VSS IN_CLK2_PORT1 B/Cb/D1_0 B/Cb/D1_1 B/Cb/D1_2 B/Cb/D1_3 B/Cb/D1_4 VDDcore1 VSScore B/Cb/D1_5 B/Cb/D1_6 B/Cb/D1_7 R/Cr/Cb Cr_0 R/Cr/Cb Cr_1 R/Cr/Cb Cr_2 R/Cr/Cb Cr_3 R/Cr/Cb Cr_4 R/Cr/Cb Cr_5 R/Cr/Cb Cr_6 R/Cr/Cb Cr_7 G/Y/Y_0 VDD2 VSS G/Y/Y_1 G/Y/Y_2 G/Y/Y_3 G/Y/Y_4 VDDcore2 VSScore G/Y/Y_5 G/Y/Y_6 G/Y/Y_7 IN_SEL TEST DEV_ADDR1 DEV_ADDR0 I/O Type Input Input Input Input Input Input Input Power Ground Input Input Input Input Input Input Power Ground Input Input Input Input Input Input Input Input Input Input Input Input Power Ground Input Input Input Input Power Ground Input Input Input Output Input Input Input Voltage Pull up/ Tolerance Drive Pulldown Description Horizontal sync or reference -CTL1 of Port 1 5v Vertical sync or reference -CTL1 of Port 1 5v Odd/Even Field identification -CTL1 of Port 1 5v Data Clock input -CTL1 of Port 1 5v Horizontal sync or reference CTL2 of Port 1 5v Vertical sync or reference CTL2 of Port 1 5v Odd/Even Field identification CTL2 of Port 1 5v 3.3 V - Power pin for IO Ground Data Clock input CTL2 of Port 1 5v Port 1 Digital video input (Blue/Cb/D1) 5v Port 1 Digital video input (Blue/Cb/D1) 5v Port 1 Digital video input (Blue/Cb/D1) 5v Port 1 Digital video input (Blue/Cb/D1) 5v Port 1 Digital video input (Blue/Cb/D1) 5v 1.8 V - Power pin for core Ground Port 1 Digital video input (Blue/Cb/D1) 5v Port 1 Digital video input (Blue/Cb/D1) 5v Port 1 Digital video input (Blue/Cb/D1) 5v Port 1 Digital video input (Red/Cr/CrCb) 5v Port 1 Digital video input (Red/Cr/CrCb) 5v Port 1 Digital video input (Red/Cr/CrCb) 5v Port 1 Digital video input (Red/Cr/CrCb) 5v Port 1 Digital video input (Red/Cr/CrCb) 5v Port 1 Digital video input (Red/Cr/CrCb) 5v Port 1 Digital video input (Red/Cr/CrCb) 5v Port 1 Digital video input (Red/Cr/CrCb) 5v Port 1 Digital video input (Green/Y) 5v 3.3 V - Power pin for IO Ground Port 1 Digital video input (Green/Y) 5v Port 1 Digital video input (Green/Y) 5v Port 1 Digital video input (Green/Y) 5v Port 1 Digital video input (Green/Y) 5v 1.8 V - Power pin for core Ground Port 1 Digital video input (Green/Y) 5v Port 1 Digital video input (Green/Y) 5v Port 1 Digital video input (Green/Y) 5v Output to select external video mux 5v 8 mA Connect to Ground 5v Device address setting 1 5v Device address setting 0 5v

24

S-301

Pin No 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Pin Name SCLK SDATA RESET_N VDD3 VSScore SDRAM DATA(0) SDRAM DATA(1) SDRAM DATA(2) SDRAM DATA(3) SDRAM DATA(4) SDRAM DATA(5) SDRAM DATA(6) SDRAM DATA(7) SDRAM DATA(8) SDRAM DATA(9) SDRAM DATA(10) SDRAM DATA(11) VDD4 VSS SDRAM DATA(12) SDRAM DATA(13) SDRAM DATA(14) SDRAM DATA(15) VDDcore3 VSScore SDRAM DATA(16) SDRAM DATA(17) SDRAM DATA(18) SDRAM DATA(19) SDRAM DATA(20) SDRAM DATA(21) SDRAM DATA(22) SDRAM DATA(23) SDRAM DATA(24) SDRAM DATA(25) VDDcore4 VSScore SDRAM DATA(26) SDRAM DATA(27) SDRAM DATA(28) SDRAM DATA(29) SDRAM DATA(30) SDRAM DATA(31) VDD5

Voltage Pull up/ I/O Type Tolerance Drive Pulldown Description 5v 8 mA 2-wire serial control bus clock I/O 5v 8 mA 2-wire serial control bus data I/O 5v PU Reset Input 3.3 V Power pin for IO Power Ground Ground SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O 3.3 V Power pin for IO Power Ground Ground SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O 1.8 V - Power pin for core Power Ground Ground SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O 1.8 V Power pin for core Power Ground Ground 5v 4 mA PD SDRAM data bus * Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O SDRAM data bus * 5v 4 mA PD Tristate I/O 3.3 V Power pin for IO Power

25

S-301

Pin No 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116

Pin Name VSS TEST IN SDRAM ADDR(10) SDRAM ADDR(9) SDRAM ADDR(8) SDRAM ADDR(7) SDRAM ADDR(6) VDDcore5 VSScore SDRAM ADDR(5) SDRAM ADDR(4) SDRAM ADDR(3) SDRAM ADDR(2) SDRAM ADDR(1) SDRAM ADDR(0) SDRAM WEN SDRAM RASN SDRAM CASN SDRAM BA1 SDRAM BA0 SDRAM CSN SDRAM DQM SDRAM CLKOUT VDD6 VSS SDRAM CLKIN TEST3 TEST OUT0 TEST OUT1 / Interrupt 117 Out 118 CTLOUT0 119 CTLOUT1 120 CTLOUT2 121 CTLOUT3 122 CTLOUT4 123 124 125 126 127 VDDcore6 VSScore CLKOUT B/U/Pb_OUT_0 B/U/Pb_OUT_1

Voltage Pull up/ I/O Type Tolerance Drive Pulldown Description Ground Ground 5V Test input-Connect to ground Input 5v 8 mA SDRAM address bus * Tristate O/P 5v 8 mA SDRAM address bus * Tristate O/P 5v 8 mA SDRAM address bus * Tristate O/P 5v 8 mA SDRAM address bus * Tristate O/P 5v 8 mA SDRAM address bus * Tristate O/P 1.8 V Power pin for core Power Ground Ground 5v 8 mA SDRAM address bus * Tristate O/P 5v 8 mA SDRAM address bus * Tristate O/P 5v 8 mA SDRAM address bus * Tristate O/P 5v 8 mA SDRAM address bus * Tristate O/P 5v 8 mA SDRAM address bus * Tristate O/P 5v 8 mA SDRAM address bus * Tristate O/P 5v 8 mA SDRAM write enable * Tristate O/P 5v 8 mA SDRAM row address select * Tristate O/P 5v 8 mA SDRAM column address select * Tristate O/P 5v 8 mA SDRAM bank select 1* Tristate O/P 5v 8 mA SDRAM bank select 0* Tristate O/P 5v 4 mA SDRAM CS * Tristate O/P 5v 8 mA SDRAM DQM * Tristate O/P 5v 12 mA Clock out to SDRAM * Output 3.3 V - Power pin for IO Power Ground Ground 5v Trace delayed SDRAM Clock in Input Test input Connect to ground Input Test output leave open Output Output Tristate O/P Tristate O/P Tristate O/P Tristate O/P Tristate O/P Power Ground Tristate O/P Tristate O/P Tristate O/P 5v 5v 5v 5v 5v 8 mA 8 mA 8 mA 8 mA 8 mA Interrupt Output Control signal output selectable as HSync1/ CSync/HRef/Monitor coast Control signal output selectable as VSync1/CRef/VRef/Film Indicator Control signal output selectable as Monitor coast/HRef/VDD_en / HSync2 Control signal output selectable as Film Indicator/VRef/backlight_en/VSync2 Control signal output selectable as CRef/Field ID/CSync/Monitor coast 1.8 V - Power pin for core Ground Output data rate clock Digital video output Blue/U/Pb Digital video output Blue/U/Pb

5v 5v 5v

12 mA 8 mA 8 mA

26

S-301

Pin No 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171

Pin Name VDD7 VSS B/U/Pb_OUT_2 B/U/Pb_OUT_3 B/U/Pb_OUT_4 B/U/Pb_OUT_5 B/U/Pb_OUT_6 B/U/Pb_OUT_7 R/V/Pr_OUT_0 R/V/Pr_OUT_1 VDDcore7 VSScore R/V/Pr_OUT_2 R/V/Pr_OUT_3 R/V/Pr_OUT_4 R/V/Pr_OUT_5 R/V/Pr_OUT_6 R/V/Pr_OUT_7 VDD8 VSS G/Y/Y_OUT_0 G/Y/Y_OUT_1 G/Y/Y_OUT_2 G/Y/Y_OUT_3 G/Y/Y_OUT_4 G/Y/Y_OUT_5 G/Y/Y_OUT_6 G/Y/Y_OUT_7 OE PLL_PVDD PLL_PVSS AVSS_PLL_BE1 AVDD_PLL_BE1 AVDD_PLL_BE2 AVSS_PLL_BE2 AVSS_PLL_SDI AVDD_PLL_SDI AVDD_PLL_FE AVSS_PLL_FE DAC_PVSS DAC_VDD DAC_VSS DAC_BOUT DAC_AVDDB

Voltage Pull up/ I/O Type Tolerance Drive Pulldown Description 3.3 V Power pin for IO Power Ground Ground 5v 8 mA Digital video output Blue/U/Pb Tristate O/P Digital video output Blue/U/Pb 5v 8 mA Tristate O/P Digital video output Blue/U/Pb 5v 8 mA Tristate O/P Digital video output Blue/U/Pb 5v 8 mA Tristate O/P Digital video output Blue/U/Pb 5v 8 mA Tristate O/P Digital video output Blue/U/Pb 5v 8 mA Tristate O/P 5v 8 mA Digital video output Red/V/Pr Tristate O/P 5v 8 mA Digital video output Red/V/Pr Tristate O/P 1.8 V Power pin for core Power Ground Ground Digital video output Red/V/Pr 5v 8 mA Tristate O/P Digital video output Red/V/Pr 5v 8 mA Tristate O/P Digital video output Red/V/Pr 5v 8 mA Tristate O/P Digital video output Red/V/Pr 5v 8 mA Tristate O/P Digital video output Red/V/Pr 5v 8 mA Tristate O/P Digital video output Red/V/Pr 5v 8 mA Tristate O/P 3.3 V Power pin for IO Power Ground Ground 5v 8 mA Digital video output Green/Y Tristate O/P Digital video output Green/Y 5v 8 mA Tristate O/P Digital video output Green/Y 5v 8 mA Tristate O/P Digital video output Green/Y 5v 8 mA Tristate O/P Digital video output Green/Y 5v 8 mA Tristate O/P Digital video output Green/Y 5v 8 mA Tristate O/P Digital video output Green/Y 5v 8 mA Tristate O/P Digital video output Green/Y 5v 8 mA Tristate O/P 5v Output data enable for Digital video output Input 1.8 V Power pin for PLL pads Power Ground for PLL pads Ground PLL Ground Ground 1.8 V Power pin for PLL Power 1.8 V Power pin for PLL Power PLL Ground Ground PLL Ground Ground 1.8 V Power pin for PLL Power 1.8 V Power pin for PLL Power PLL Ground Ground Ground for DAC pads Ground Power 1.8 V Digital power pin for DAC Ground DAC digital Ground 34 mA Analog B/U output Output 3.3 V Analog power pin for B channel Power

27

S-301

Pin No 172 173 174 175 176 177 178 179 180

Pin Name DAC_AVSSB DAC_GOUT DAC_AVDDG DAC_AVSSG DAC_ROUT DAC_AVDDR DAC_AVSSR DAC_COMP DAC_RSET

181 DAC_VREFOUT 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Note: DAC_VREFIN DAC_AVDD DAC_AVSS DAC_GR_AVSS DAC_GR_AVDD DAC_PVDD TEST0 TEST1 TEST2 XTAL IN XTAL OUT VDD9 VSS IN_CLK_PORT 2 D1_IN_0 VDDcore8 VSScore D1_IN_1 D1_IN_2 D1_IN_3 D1_IN_4 D1_IN_5 D1_IN_6 D1_IN_7 FIELD ID_PORT 2 VSYNC_ PORT 2 HSYNC_PORT 2

I/O Type Ground Output Power Ground Output Power Ground Output Output Output Input Power Ground Ground Power Power Input Input Input Input Output Power Ground Input Input Power Ground Input Input Input Input Input Input Input Input Input Input

Voltage Pull up/ Tolerance Drive Pulldown Description Analog Ground for B channel 34 mA Analog G/Y output 3.3 V Analog power pin for G channel Analog Ground for G channel 34 mA Analog R/V output 3.3 V Analog power pin for R channel Analog Ground for R channel Compensation for video DACs Current setting resistor for video DACs 1.28 V Internally generated voltage reference for video DACs External Voltage reference for video DACs 3.3 V Analog power pin for DAC Analog Ground for DAC Ground for DAC Guard ring 3.3 V Power pin for DAC Guard ring 3.3 V Power pin for DAC pads 5v Test pin connect to ground 5v Test pin connect to ground 5v Test pin connect to ground External parallel crystal oscillator External parallel crystal oscillator 3.3 V - Power pin for IO Ground 5v 4 mA Port 2 - Data Clock input 5v 4 mA Port 2 - ITU-R BT656 digital data input 1.8 V Power pin for core Ground 5v 4 mA Port 2 - ITU-R BT656 digital data input 5v 4 mA Port 2 - ITU-R BT656 digital data input 5v 4 mA Port 2 - ITU-R BT656 digital data input 5v 4 mA Port 2 - ITU-R BT656 digital data input 5v 4 mA Port 2 - ITU-R BT656 digital data input 5v 4 mA Port 2 - ITU-R BT656 digital data input 5v 4 mA Port 2 - ITU-R BT656 digital data input 5v 4 mA Port 2 - Odd/Even Field identification 5v 4 mA Port 2 - Vertical sync or reference 5v 4 mA Port 2 - Horizontal sync or reference

* - The connection of these pins depends on the type of external SDRAM used.

28

S-301

CXD1885Q (IC805: 1U-3692)

DRAM I/F

PWM.FGDA3 (SLED2_TILT)

D/A

DA2 (FSCON)

DVDD33

DA0 (TSCON)

DA1 (SLED)

GPWM5

GPWM4

GPWM3

GPWM2

GPWM1

GPWM0

SPWM2

SPWM1

DVDD18

DVDD18

RD10

RD11

RD12

RD13

RD14

RD15

DVSS

DVSS

RD9

RD0

RD1

RD2

RD3

RD4

RD5

RA1

RA2

RA3

RA4

RA5

RA6

RA7

RA8

RA9

156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 DVDD33 157 RD8 158 TEST0 159 TEST1 160 TEST2 161 TEST3 162 TEST4 163 TEST5 164 TEST6 165 TEST7 166Test/Monitor Pin

AVDD33

XUCAS

XLCAS

XMWR

XMOE

XRAS

RA10

RA11

AVSS

RD6

RD7

RA0

FG

104 AVDD18 103 VREFL 102 VREFH 101 AD9 100 AD8 99 AD7 98 AD6 97 AD5 96 AD4 95 AD3 94 AVDD33 93 AD2 92 AD1 91 AD0 90 AVSS 89 AVSS 88 RC 87 LPF2 86 LPF1 85 VCOI 83 VFBC 82 CHG 81 JMOUT 80 JMREF 79 AVDD33 78 IREF 77 TLC1 76 TLC0 75 HF 74 ATC 73 AVSS 72 DTC 70 HFD 69 RFOKGH 68 SCLKH 67 SO 66 SI 65 CSL 64 EXPLDT 63 EXVCO 61 LRCK 60 DOTK 59 DADT 58 C2PO 57 DRVRDY 56 DRVCLK 55 DRVRX 53 DVDD33 1DVDD33 VSTEM I/F Audio D/A ASP S-I/O, Defect etc Data PLL/Data Slicer A/D

TEST8 167 TEST9 168 TEST10 169 TEST11 170 TEST12 171 TEST13 172 TEST14 173 TEST15 174 MODSEL0 175 MODSEL1 176 DVSS 177 MODSEL2 178 GIO0 179 GIO1 180 GIO2 181 GIO3 182 DVDD33 183 GIO4 184 GIO5 185 GIO6 186 GIO7 187 DVDD18 188 GIO8 189 GIO9 190 GIO10 191 GIO11 192 GIO12 193 DVSS 194 GIO13 195 GIO14 196 GIO15 197 GIO16 198 GIO17 199 GIO18 200 GIO19 201 TRST 202 TMS 203

84 AVDD18

General Port

71 MIRRORH

62 BCK

JTAG

TDI 204 TCK 205 TDO 206 VMCHG 207 DVDD18 208 2ALCR

54 DRVTX

3MSEL0

4MSEL1

5MA0

6MA1

7MA2

8MA3

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52DVSS DVSS MRDY DVDD33 MINT SYSCK DVDD18 DVSS MCS MD0 MD1 MD2 MD3 MD4 MD5 MRD XO DRVIRQ TESTSEL DRVRST DVDD18 XHAC MD6 MD7 XI HDRQ MALE VEFG XSHD VDT7 VDT6 VDT5 VDT4 VDT3 VDT2 VDT1 VDT0 MWR DCK MA4 MA5 MA6 MA7 MA8

B/E MCU I/F

Clock

VSTEM I/F

29

S-301

16/4M DRAM

HFD

BCA Memory manager

ECC Core EDC MPEG I/F Video

HF

Data Slicer Data-PLL ASP Serial I/F

DVD Demodulation CD-DSP (DDCD) VSTEM Serial I/F Spindle

ASP PWM ATC JTAG Mecha control Servo singnal

Serial Command CD-ROM Header Dec. Audio I/F DSP CLK/Mode Audio MCU I/F ICU D/A PWM Peri. CLK Servo control X'tal MCU

VSTEM

TZC

TC DSP CMD/ RSP reg.

GIO

Direction ROM/RAM ICU

Data RAM Timer

A/D

FunctionsNo. 1 3 4 5 6 7 8 9 10 11 12 Terminal Name DVDD33 MSEL0 MSEL1 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 I/O P I I I I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O P I/O I/O I I I P I O O D D D D D D D D D D D D D D D D D D D D D D D D D D D A/D

(A/D : Analog/Digital, PU : Pull-up, PD : Pull-down, SMT=Schumitt )Classification VDD & GND MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F VDD & GND MCU I/F MCU I/F MCU I/F MCU I/F MCU I/F VDD & GND MCU I/F MCU I/F MCU I/F Digital 3.3V Power for I/O. Chip select input. (L: Reset) MCU I/F mode select 0. MCU I/F mode select 1. MCU Adress input 0 / data I/O 0 . MCU Adress input 1 / data I/O 1. MCU Adress input 2 / data I/O 2. MCU Adress input 3 / data I/O 3. MCU Adress input 4 / data I/O 4. MCU Adress input 5 / data I/O 5. MCU Adress input 6 / data I/O 6. MCU Adress input 7 / data I/O 7. MCU Adress input 8 . TEST Select input. MCU data I/O 0 . MCU data I/O 1. MCU data I/O 2. MCU data I/O 3. MCU data I/O 4. MCU data I/O 5. Digital Ground. MCU data I/O 6. MCU data I/O 7 . MCU Adress latch signal input. MCU Chip Select signal input. MCU Write strobe signal. digital 3.3V Power. (for I/O ) MCU Read Strobe signal. MCU Ready signal. (L: Wait) MCU Interrupt signal. (L: Interrupt request) * * * * * * * * * * * * * * * * * * * * * * * * * * Function PU PD SMT

2 ALCR

13 MA8 14 TESTSEL 15 16 17 18 19 20 22 23 24 25 26 28 29 30 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MALE MCS MWR MRD MRDY MINT

21 DVSS

27 DVDD33

30

S-301

No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Terminal Name SYSCK DVDD18 XI XO DVSS VDT7 VTD6 DVSS VDT5 VDT4 VDT3 VDT2 VDT1 VDT0 HDRQ XHAC VEFG XSHD DCK DRVIRQ DRVRST DVDD18 DVDD33 DRVTX DRVRX DRVCLK DRVRDY C2PO DADT DOTX LRCK BCK EXVCO EXPLDT CSL SI SO SCLKH RFOKGH HFD MIRRORH DTC AVSS ATC HF TLC0 TLC1 IREF AVDD33 JMREF JMOUT CHG VFBC AVDD18 VCOI LPF1 LPF2 RC AVSS AVSS AD0

I/O O P I O P O O P O O O O O O I O O O O O I P P O I I O O O O O O I I O I O O I I I I P I I O O I P I O I I P I O O I P P I

A/D D D D D D D D D D D D D D D D D D D

Classification Clock VDD & GND Clock Clock VDD & GND VSTEM A/V VSTEM A/V VDD & GND VSTEM A/V VSTEM A/V VSTEM A/V VSTEM A/V VSTEM A/V VSTEM A/V VSTEM A/V VSTEM A/V VSTEM A/V VSTEM A/V VSTEM A/V VSTEM Command VSTEM Command VDD & GND VDD & GND Clock Monitor output.

Function Digital 1.8V Power. (Internal logic system power) Crystal oscillation input. Crystal oscillation output. Digital Ground. MPEG data output 7. MPEG data output 6. Digital Ground. MPEG data output 5. MPEG data output 4. MPEG data output 3. MPEG data output 2. MPEG data output 1. MPEG data output 0. MPEG data Request input. Data Valid output. ECC Error-sector Flag output. (L: error sector) DVD Sector Head Flag output. Data Strobe output. Interrupt Request output for Host. (L: interruption is demanded) Drive H/W Reset input. (L: reset) Digital 1.8V power for Internal logic system. Digital 3.3V Power for I/O. Transmitting serial data output to Host. Reception serial data input from Host. Clock input from Host. Drive Ready signal output. (L: ready) CD-DSP C2 Pointer output. Audio serial data output. Digital audio output. L/R Clock output. Audio Bit Clock output. External Channel clock input. External RF data input. (Logic level) SIO for RF signal processing LSI control. Latch signal output. SIO for RF signal processing LSI control. Serial data input. SIO for RF signal processing LSI control. Serial data output. SIO for RF signal processing LSI control. Serial clock output. RF O.K. Signal input. RF lack Signal input. Mirror detected signal input.(H: Mirror detected) Track cross signal input. (Logic level input) Analog Ground. Track Cross signal input. (Analog level input) RF signal input. Asymmetry Charge-pump output 0. Asymmetry Charge-pump output 1 Reference current setting terminal for Asymmetry Circuit. Analog 3.3V Power. Reference current setting terminal for Jitter Monitor Jitter Monitor output. Reference current setting terminal for data PLL. VCO offset frequency setting terminal for data PLL. Analog 1.8V Power. VCO Control voltage input terminal for data PLL. VCO Loop-filter connection terminal 1 for data PLL. VCO Loop-filter connection terminal 2 for data PLL VCO gain setting terminal for data PLL. Analog Ground. Analog Ground. AD0 Input.

PU

PD

SMT

*

*

*

D D D D D D D D D D D D D D D D D D D A A A A A A A A A A A A A

VSTEM Command VSTEM Command VSTEM Command VSTEM Command Audio I/F Audio I/F Audio I/F Audio I/F Audio I/F TEST/Monitor TEST/Monitor ASP I/F ASP I/F ASP I/F ASP I/F ASP I/F ASP I/F ASP I/F ASP I/F VDD & GND Data PLL Data PLL Data PLL Data PLL Data PLL VDD & GND Data PLL Data PLL Data PLL Data PLL VDD & GND Data PLL Data PLL Data PLL Data PLL VDD & GND VDD & GND

*

* * * *

A

ADC

31

S-301

No. 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149

Terminal Name AD1 AD2 AVDD33 AD3 AD4 AD5 AD6 AD7 AD8 AD9 VREFH VREFL AVDD18 AVDD33 DA0 (TSCON) DA1 (SLED) DA2 (FSCON) DA3 (SLED2_ TILT) AVSS FG SPWM1 SPWM2 GPWM0 GPWM1 GPWM2 GPWM3 GPWM4 GPWM5 XLCAS XUCAS XMOE RA11 RA10 DVSS RA9 RA8 RA7 RA6 RA5 DVDD33 RA4 RA3 RA2 RA1 DVDD18 RA0 XRAS XMWR RD7 RD6 DVSS RD5 RD4 RD3 RD2 RD1 RD0 RD15

I/O I I P I I I I I I I I/O I/O P P O O O O P I O O O O O O O O O O O O O P O O O O O P O O O O P O O O I/O I/O P I/O I/O I/O I/O I/O I/O I/O

A/D A A A A A A A A A A A

Classification ADC ADC VDD & GND ADC ADC ADC ADC ADC ADC ADC ADC ADC VDD & GND VDD & GND AD1 Input. AD2 Input. Analog 3.3V Power. AD3 Input. AD4 Input. AD5 Input. AD6 Input. AD7 Input. AD8 Input. AD9 Input.

Function

PU

PD

SMT

Max Reference Voltage input for ADC. (Internal Reference Voltage mode, it will be an output state) Min Reference Voltage input for ADC. (Internal Reference Voltage mode, it will be an output state) Analog 1.8V Power. Analog 3.3V Power. DA0 output. (Track Servo output) DA1 output. (Sled Servo output) DA2 output. (Forcus Servo output) DA3 output. (Sled Servo / Tilt Servo output) Analog Ground FG signal input. Spindle motor PWM output 1. Spindle motor PWM output 2. Multi-purpose PWM output 0. Multi-purpose PWM output 1. Multi-purpose PWM output 2. Multi-purpose PWM output 3. Multi-purpose PWM output 4. Multi-purpose PWM output 5. DRAM LCAS output. (Low-Byte row address strobe output) DRAM UCAS output. (Upper-Byte row address strobe output) DRAM output enable. DRAM address output terminal 11. DRAM address output terminal 10. Digital Ground. DRAM address output terminal 9. DRAM address output terminal 8. DRAM address output terminal 7. DRAM address output terminal 6. DRAM address output terminal 5. Digital 3.3V Power. (for I/O) DRAM address output terminal 4. DRAM address output terminal 3. DRAM address output terminal 2. DRAM address output terminal 1. Digital 1.8V Power. (for Internal Logic power) DRAM address output terminal 0. DRAM RAS output. (Column address strobe output) DRAM Write enable. DRAM data input/output terminal 7. DRAM data input/output terminal 6. Digital Ground. DRAM data input/output terminal 5. DRAM data input/output terminal 4. DRAM data input/output terminal 3. DRAM data input/output terminal 2. DRAM data input/output terminal 1. DRAM data input/output terminal 0. DRAM data input/output terminal 15. * * * * * * * * * *

A A A A

DAC DAC DAC DAC VDD & GND

D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D

SPM SPM SPM General PWM General PWM General PWM General PWM General PWM General PWM DRAM I/F DRAM I/F DRAM I/F DRAM I/F DRAM I/F VDD & GND DRAM I/F DRAM I/F DRAM I/F DRAM I/F DRAM I/F VDD & GND DRAM I/F DRAM I/F DRAM I/F DRAM I/F VDD & GND DRAM I/F DRAM I/F DRAM I/F DRAM I/F DRAM I/F VDD & GND DRAM I/F DRAM I/F DRAM I/F DRAM I/F DRAM I/F DRAM I/F DRAM I/F

32

S-301

No. 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

Terminal Name RD14 RD13 RD12 RD11 RD10 RD9 DVDD18 DVDD33 RD8 TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 TEST11 TEST12 TEST13 TEST14 TEST15 MODSEL0 MODSEL1 DVSS MODSEL2 GIO0 GIO1 GIO2 GIO3 DVDD33 GIO4 GIO5 GIO6 GIO7 DVDD18 GIO8 GIO9 GIO10 GIO11 GIO12 DVSS GIO13 GIO14 GIO15 GIO16 GIO17 GIO18 GIO19 TRST TMS TDI TCK TDO VMCHG DVDD18

I/O I/O I/O I/O I/O I/O I/O P P I/O O O O O O O O O O O O O O O O O I I P I I/O I/O I/O I/O P I/O I/O I/O I/O P I/O I/O I/O I/O I/O P I/O I/O I/O I/O I/O I/O I/O I I I I O I P

A/D D D D D D D

Classification DRAM I/F DRAM I/F DRAM I/F DRAM I/F DRAM I/F DRAM I/F VDD & GND VDD & GND

Function DRAM data input/output terminal 14. DRAM data input/output terminal 13. DRAM data input/output terminal 12. DRAM data input/output terminal 11. DRAM data input/output terminal 10. DRAM data input/output terminal 9. Digital 1.8V Power. (for internal Logic system) Digital 3.3V power for I/O. DRAM data input/output terminal 8. TEST I/O 0. TEST I/O 1. TEST I/O 2. TEST I/O 3. TEST I/O 4. TEST I/O 5. TEST I/O 6. TEST I/O 7. TEST I/O 8. TEST I/O 9. TEST I/O 10. TEST I/O 11. TEST I/O 12. TEST I/O 13. TEST I/O 14. TEST I/O 15. TEST mode select 0. (GND, under normal conditions) TEST mode select 1. (GND, under normal conditions) Digital Ground. TEST mode select 2. (GND, under normal conditions) Multi-purpose port 0. Multi-purpose port 1. Multi-purpose port 2. Multi-purpose port 3. Digital 3.3V Power for I/O. Multi-purpose port 4. Multi-purpose port 5. Multi-purpose port 6. Multi-purpose port 7. Digital 1.8V Power for I/O. (for internal Logic system) Multi-purpose port 8. Multi-purpose port 9. Multi-purpose port 10. Multi-purpose port 11. Multi-purpose port 12. Digital Ground. Multi-purpose port 13. Multi-purpose port 14. Multi-purpose port 15. Multi-purpose port 16. Multi-purpose port 17. Multi-purpose port 18. Multi-purpose port 19. JTAG Reset input. JTAG Mode Select input. JTAG Data Input. JTAG Clock input. JTAG Data output. VSTEM / external MCU access selection terminal of system setting register for DSP. (L: VSTEM, H: external MCU) Digital 1.8V power for internal Logic system.

PU * * * * * *

PD

SMT

D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D

DRAM I/F TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor TEST/Monitor VDD & GND TEST/Monitor Multi-purpose Multi-purpose Multi-purpose Multi-purpose VDD & GND General Port General Port General Port General Port VDD & GND General Port General Port General Port General Port General Port VDD & GND Multi-purpose General Port General Port General Port General Port General Port General Port JTAG I/F JTAG I/F JTAG I/F JTAG I/F JTAG I/F MCU I/F VDD & GND

*

* * * * * * * * * * * * * * * * * * * * * * * * * * * * *

* * * * * * * * * * * * * * * * * * * * * * *

33

S-301

BCOIC-DM850-CQL (IC101: 1U-3693)

34

S-301

Pin1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 VSSIO

NameAV0CLK VDDIO AV0DATA[0] AV0DATA[1] AV0DATA[2] AV0DATA[3] GPIO[0] GPIO[6] GPIO[11] GPIO[10] AV2DATA[0] AV2DATA[1] AV2DATA[2] VSSIO VDDIO VSSC VDDC GPIO[9] GPIO[8] AV4DATA[0] AV4DATA[1] AV4DATA[2] AV4DATA[3] MIITXD[3] MIITXD[2] MIITXD[1] MIITXD[0] MIITXEN CLKOUT VSSIO VDDIO AV3CLK AV3CTRL[0] AV3CTRL[1] VSSC USBVBUSDRV VDDC AV3DATA[0] AV3DATA[1] MIITXCLK MIITXER VDDIO AV3DATA[2] VSSIO AV3DATA[3] VDDUSB USBD+ USBDVSSUSB USBVBUS USBID

Pin53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104

NameUSBREF VSSIOUSB VDDIOUSB VDDUSBPLL VSSUSBPLL VSSIO USBXTALI USBXTALO VDDIO GPIO[3] RXD0 GPIO[1] TXD0 GPIO[2] SYNC MIIRXER MIIRXCLK MIIRXDV VDDC VSSC MIIRXD[0] MIIRXD[1] MIIRXD[2] MIIRXD[3] VSSIO VDDIO RXD1 TXD1 MIIPHYCLK MIIDC MIIDIO TMS TCK VDDC VSSC VSSIO VDDIO NC TEST5 NC TDI TDO VDDC VSSC MIICRS MIICOL GPIO[15] GPIO[14] GPIO[13] GPIO[12] VDDIO VSSIO

Pin105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 A[19] A[20] A[21] NWE

Name

Pin157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 VSSIO VDDIO A[5] A[6]

Name

NCS[2] NCS[1] NCS[0] VSSIO VDDIO VDDC NOE VSSC MEMCKE D[0] D[1] D[2] D[3] D[4] D[5] VSSIO VDDIO D[6] D[7] VDDC VSSC D[8] D[9] D[10] D[11] D[12] MEMCLK VDDIO VSSIO D[13] D[14] D[15] SPICLK SPINCS[1] SPINCS[0] VDDC VSSC SPIMISO SPIMOSI NTEST3 NTEST4 VSSIO VDDIO A[0] A[1] A[2] A[3] A[4]

AV1DATA[0] AV1DATA[1] AV1DATA[2] AV1DATA[3] A[7] A[8] AV4CTRL[0] AV4CTRL[1] A[9] A[10] A[11] A[12] VSSC VDDC VSSIO VDDIO A[13]/RAS A[14]/CAS A[15]/BA[0] A[16]/BA[1] A[17]/DQM[0] A[18]/DQM[1] NWAIT VCO[1] PDOUT[1] TEST1 NTEST2 VSSC VDDC NRESET VSSIO VDDIO VCO[0] PDOUT[0] AV4CLK AV0CTRL[0] AV0CTRL[1] AV2CLK AV2CTRL[0] AV2CTRL[1] VDDIO VSSIO XTALI XTALO VDDPLL VSSPLL VDDDCO VSSDCO

35

S-301

CXD2753R (IC602: 1U-3692)Pin Assignment

Block Diagram

36

S-301Terminal FunctionsPin Name 1 VSC I/O I I I O O O I Ipd I O O O O O O O O O O O O I Ipu O Ipu Ipu I I I O O O O O O O O O O O It fixed to ground.( for Core) Latch input for COM serial communication. Shift clock input for COM serial communication. Data input for COM serial communication. +2.5V Power for Core. Data output for COM serial communication. Hi-Z potential except the output mode. Completion flag of output preparation for COM serial communication. L is outputted at the time of completion. Output enable pin for COM serial communication. L is outputted at the time of MSDATO mode. Reset pin. The whole IC is reset by at the time of L potential. Soft Mute. Soft mute of the audio output is carried out at the time of H potential. It releases at the time of L potential. Master Clock input. It fixed to Ground. Ground for I/O. External output Clock 1. External output Clock 2. 44.1kHz, 1Fs Clock output. Frame signal output. +3.3V Power for I/O. Monitor output. Monitor output. Monitor output. Monitor output. Output terminal for a Test. (open) Output terminal for a Test.(open) Output terminal for a Test.(open) Output terminal for a Test.(open) Clock input for a Test. It fixed to L potential. Input pin(pull-up) for a Test.(open) It fixed to Ground. Ground for CORE. Output for a Test.(open). Input pin(pull-up) for a Test.(open) Reset pin(pull-up) for a Test. Input the Power-on reset signal or fixed to L potential. Test input pin. It fixed to L potential. Test input pin. It fixed to L potential. Test input pin. It fixed to L potential. +2.5V Power for CORE. Out put for TEST. It fixed to open. DST monitor. Supplementary data output. (LSB) Supplementary data output. Supplementary data output. Supplementary data output. Ground for I/O. Supplementary data output. Supplementary data output. +3.3V Power for I/O. Supplementary data output. Supplementary data output. (MSB) Supplementary data Acknowledge output terminal. Ground for CORE. Functions

2 XMSLAT 3 MSCK

4 MSDATI 5 VDC 6 7 8 9 10 11 12 13 14 15 16 MSDATO MSREADY XMSDOE XRST SMUTE MCKI VSIO EXCKO1 EXCKO2 LRCK FRAME

17 VDIO 18 19 20 21 MNT0 MNT1 MNT2 MNT3

22 TESTO 23 24 25 TESTO TESTO TESTO

26 TCK 27 TDI 28 29 VSC TDO

30 TMS 31 32 33 34 35 36 37 38 39 40 41 42 43 44 TRST TEST1 TEST2 TEST3 VDC TESTO XBIT SUPDT0 SUPDT1 SUPDT2 SUPDT3 VSIO SUPDT4 SUPDT5

45 VDIO 46 47 48 49 SUPDT6 SUPDT7 XSUPAK VSC

37

S-301

Pin Name 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 TESTO TESTI TESTI TESTO VDC DSADML DSADMR BCKASL VSDSD BCKAI BCKAO PHREFI PHREFO ZDFL DSAL ZDFR DSAR VDDSD ZDFC DSAC ZDFLFE DSASW VSDSD ZDFLS DSALS ZDFRS DSARS VDDSD IOUT0 IOUT1 VSC IOUT2 IOUT3 VDC IOUT4 IOUT5 VSIO IANCO

I/O O I I O O O I I O I O O O O O O O O O O O O O O O O O O O O O I I O O O I Output for TEST. (open) Input for TEST. It fixed to L potential. Input for TEST. It fixed to L potential. Output for TEST. (open) +2.5V Power for CORE. DSD Data output terminal for Lch Down Mix. DSD Data output terminal for Rch Down Mix.

Functions

I/O selection terminal of the Bit clock for DSD data output. L=input (Slave), H=output (Master) Ground terminal for DSD data output. Bit clock input terminal for DSD data output. Input a Bit clock into this terminal at the time of BCKASL=L potential. Bit clock output terminal for DSD data output. Bit clock output from this terminal at the time of BCKASL=H potential. Reference phase signal input terminal for DSD output phase modulation. Reference phase signal output terminal for DSD output phase modulation. Lch zero-data detection flag (at the time of com setup). It will be set to H if non-sound data continues 300 msecs. DSD data output terminal for Lch speaker. Rch zero-data detection flag (at the time of com setup). It will be set to H if non-sound data continues 300 msecs. DSD data output terminal for Rch speaker. +3.3V Power for DSD data output. Cch zero-data detection flag (at the time of com setup). It will be set to H if non-sound data continues 300 msecs. DSD data output terminal for Cch speaker. LFEch zero-data detection flag (at the time of com setup). It will be set to H if non-sound data continues 300 msecs. DSD data output terminal for SWch speaker. Ground for DSD data output. LSch zero-data detection flag (at the time of com setup). It will be set to H if non-sound data continues 300 msecs. DSD data output terminal for LSch speaker. RSch zero-data detection flag (at the time of com setup). It will be set to H if non-sound data continues 300 msecs. DSD data output terminal for RSch speaker. +3.3V Power for DSD data output. Data output terminal 0 for IEEE1394 link chip I/F. Data output terminal 1 for IEEE1394 link chip I/F. Ground for CORE. Data output terminal 2 for IEEE1394 link chip I/F. Data output terminal 3 for IEEE1394 link chip I/F. +2.5V Power for CORE. Data output terminal 4 for IEEE1394 link chip I/F. Data output terminal 5 for IEEE1394 link chip I/F. Ground for I/O. Transmission information data output terminal for IEEE1394 link chip I/F. Data transmission hold request signal input terminal for IEEE1394 link chip I/F. High speed transmission request signal input terminal for IEEE1394 link chip I/F. +3.3V Power for I/O. Frame reference signal output terminal for IEEE1394 link chip I/F. Enable signal output terminal for IEEE1394 link chip I/F. Data transmission clock output terminal for IEEE1394 link chip I/F. Ground for CORE. TEST input terminal. It fixed to H potential.

88 IFULL 89 IEMPTY

90 VDIO 91 IFRM

92 IOUTE 93 94 95 IBCK VSC TESTI

38

S-301

Pin Name 96 97 98 99 100 101 102 103 104 105 106 107 108 109 TESTI TESTI TESTO VDC TESTI TESTI TESTI TESTI TESTI TESTI VSIO TESTI TESTI TESTI

I/O I Ipu O I I I I I I I I I I I I I I I I I I I Ai Ai I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O TEST input terminal. It fixed to L potential. TEST input terminal. It fixed to H potential. TEST output terminal. (open) +2.5V Power for CORE. TEST input terminal. It fixed to L potential. TEST input terminal. It fixed to L potential. TEST input terminal. It fixed to L potential. TEST input terminal. It fixed to L potential. TEST input terminal. It fixed to L potential. TEST input terminal. It fixed to L potential. Ground for I/O. TEST input terminal. It fixed to L potential. TEST input terminal. It fixed to L potential. TEST input terminal. It fixed to L potential. +3.3V Power for I/O.

Functions

110 VDIO 111 112 113 114 115 116 117 118 119 120 121 122 WAD0 WAD1 WAD2 WAD3 VSIO VSC WAD4 WAD5 WAD6 WAD7 VDC TESTI

External A/D data input terminal(LSB) for PSP physical disc mark detection. External A/D data input terminal for PSP physical disc mark detection. External A/D data input terminal for PSP physical disc mark detection. External A/D data input terminal for PSP physical disc mark detection. Ground for I/O. Ground for CORE. External A/D data input terminal for PSP physical disc mark detection. External A/D data input terminal for PSP physical disc mark detection. External A/D data input terminal for PSP physical disc mark detection. External A/D data input terminal(MSB) for PSP physical disc mark detection. +2.5V Powe for CORE. TEST input terminal. It fixed to L potential. Operation clock for PSP physical disc mark detection. +2.5V Power. A/D Power supply for PSP physical disc mark detection. +2.5V Power. A/D Power supply for PSP physical disc mark detection. Analog RF signal input terminal for PSP physical disc mark detection. A/D bottom reference terminal for PSP physical disc mark detection. A/D Ground terminal for PSP physical disc mark detection. A/D Ground terminal for PSP physical disc mark detection. Ground for I/O. SDRAM data input/output terminal. (MSB) SDRAM data input/output terminal. SDRAM data input/output terminal. SDRAM data input/output terminal. +3.3V Power for I/O. SDRAM data input/output terminal. SDRAM data input/output terminal. SDRAM data input/output terminal. SDRAM data input/output terminal. (LSB) Ground for I/O. Clock output terminal for SDRAM. Clock enable output terminal for SDRAM. Write enable output terminal for SDRAM. Colomn address strobe output terminal for SDRAM. Row address strobe output terminal for SDRAM. +3.3V Power for I/O. Output terminal for TEST. (open)

123 WCK 124 125 WAVDD WAVDD

126 WARFI 127 128 129 130 131 WAVRB WAVSS WAVSS VSIO DQ7

132 DQ6 133 DQ5 134 DQ4 135 VDIO 136 DQ3 137 DQ2 138 DQ1 139 140 141 142 143 144 145 DQ0 VSIO DCLK DCKE XWE XCAS XRAS

146 VDIO 147 TESTO

39

S-301

Pin Name 148 A11 149 150 151 152 153 154 155 156 157 158 159 160 161 A10 VSC A9 A8 VDC A7 A6 A5 A4 VSIO A3 A2 A1

I/O O O O O O O O O O O O O O I I I I I I I I I I I I Address output terminal for SDRAM. (MSB) Address output terminal for SDRAM. Ground for CORE. Address output terminal for SDRAM. Address output terminal for SDRAM. +2.5V Power for CORE. Address output terminal for SDRAM. Address output terminal for SDRAM. Address output terminal for SDRAM. Address output terminal for SDRAM. Ground for I/O. Address output terminal for SDRAM. Address output terminal for SDRAM. Address output terminal for SDRAM. Address output terminal for SDRAM. (LSB) +3.3V Power for I/O.

Functions

162 A0 163 VDIO 164 165 166 167 168 169 170 171 172 173 174 175 176 XSRQ XSHD SDCK XASK SDEF SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7

Output terminal of the Data Request signal inputted a front-end processor. Input terminal of the header Flag outputted from a front-end processor. Input terminal of the data conveyance Clock outputted from a front-end processor. Input terminal of the data valid Flag outputted from a front-end processor. Input terminal of the error Flag outputted from a front-end processor. Input terminal of the stream Data outputted from a front-end processor. Input terminal of the stream Data outputted from a front-end processor. Input terminal of the stream Data outputted from a front-end processor. Input terminal of the stream Data outputted from a front-end processor. Input terminal of the stream Data outputted from a front-end processor. Input terminal of the stream Data outputted from a front-end processor. Input terminal of the stream Data outputted from a front-end processor. Input terminal of the stream Data outputted from a front-end processor.

Ipu: Pull-up input

Ipd: Pull-down input

Ai: Analog input

40

S-301

ADSP-21266SKSTZ-1C (IC906: 1U-3694)

144 1

109 108

PIN 1 INDICATOR

TOP VIEW

36

73

37

72

ADSP-21266SKSTZ-1C Terminal FunctionPin Name LQFP Pin # Pin Name LQFP Pin # Pin Name LQFP Pin # Pin Name LQFP Pin #

VDDINT CLKCFG0 CLKCFG1 BOOTCFG0 BOOTCFG1 GND VDDEXT GND VDDINT GND VDDINT GND VDDINT GND FLAG0 FLAG1 AD7 GND VDDINT GND VDDEXT GND VDDINT AD6 AD5 AD4 VDDINT GND AD3 AD2 VDDEXT GND AD1 AD0 WR VDDINT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

VDDINT GND RD ALE AD15 AD14 AD13 GND VDDEXT AD12 VDDINT GND AD11 AD10 AD9 AD8 DAI_P1 (SD0A) VDDINT GND DAI_P2 (SD0B) DAI_P3 (SCLK0) GND VDDEXT VDDINT GND DAI_P4 (SFS0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) VDDINT GND VDDINT GND DAI_P8 (SFS1) DAI_P9 (SD2A) VDDINT

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

VDDEXT GND VDDINT GND DAI_P10 (SD2B) DAI_P11 (SD3A) DAI_P12 (SD3B) DAI_P13 (SCLK23) DAI_P14 (SFS23) DAI_P15 (SD4A) VDDINT GND GND DAI_P16 (SD4B) DAI_P17 (SD5A) DAI_P18 (SD5B) DAI_P19 (SCLK45) VDDINT GND GND VDDEXT DAI_P20 (SFS45) GND VDDINT FLAG2 FLAG3 VDDINT GND VDDINT GND VDDINT GND VDDINT GND VDDINT VDDINT

73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108

GND VDDINT GND VDDINT GND VDDINT GND VDDEXT GND VDDINT GND VDDINT RESET SPIDS GND VDDINT SPICLK MISO MOSI GND VDDINT VDDEXT AVDD AVSS GND CLKOUT EMU TDO TDI TRST TCK TMS GND CLKIN XTAL VDDEXT

109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

41

S-301

M30627FHPGP (IC202: 1U-3694)

PIN NO1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Port FunctionVREF AVcc SIN4 SOUT4 CLK4 P94 P93 SOUT3 SIN3 CLK3 P141 P140 BYTE CNVSS P87 P86 /RESET XOUT VSS XIN VCC1 /NMI /INT2 /INT1 /INT0 TA4IN

Port settingI I O SO SO I I SO SI O O O VREF AVcc

Port Name

ExplanationReference Voltage Input for A/D converter Positive power Chip Enable output to FLD Serial Data output to FLD Serial Clock output to FLD Interrupt request from DSP Interrupt request from DSP Serial Data output to DSP Serial Data input from DSP Serial Clock output to DSP Chip Enable output to DSP Reset output to FLD GND Select input of Flash rom write Mode

FL_CS FL_DA FL_CK BUSY1 ACK1 DSPMOSI DSPMISO DSPSPICLK DSPSPICS FL_RST

O O

3811CLK 3811DATA

Serial Clock output to BD3811 Serial Data output to BD3811 Reset input Xtal output GND Xtal input Positive power Positive power

INT INT I I

PROTECT ESS CS(OP_CE) DIR INT1 50/60

Protect Signal input Chip Enable input from ESS Interrupt request from DIR 50Hz/60Hz AC Input

42

S-301PIN NO27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Port FunctionP80 P77 P76 P75 P74 P73 P72 RXD2 TXD2 TXD1 VCC1 RXD1 VSS CLK1 P64 TXD0 RXD0 CLK0 P60 P137 P136 P135 P134 P57 P56 P55 P54 P133 P132 P131 P130 P53 P52 P51 P50 P127 P126 P125 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 P124 P123

Port settingO I O I I O I SI SO SO SI O O SO SI I I I I O O O O O O O O I O I O O O O O O O I I O O O O O O O O O O O O I I

Port NameLD_CONT USB_REQ V_CONT VOL JOG-B VOL JOG-A USB_CE USB_MODE RXD232 TXD232 USB/IPOD_TXD USB/IPOD_RXD USB_CLK USB_RST ESS DO(OP_DO) ESS DI(OP_DI) ESS CK(OP_CLK) ESS ON(BE_ON) CL_SW OP_SW CLS_DRV OPN_DRV DVD_RST /PLL_RST SELCLK DVD ON/OFF VMUTE1 VMUTE2 HP SW TRIGGER AUX IN SW EXT_CLK EXT_DATA USB_POW_ON VIDEO_A VIDEO_B VIDEO_C VIDEO_D VDET_V VDET_S BSE ERR MUTE SUB_SUM MULTI/DIR MIX/MULTI P.ON/OFF SCART MUTE IPOD_ID SP-RELAY HP-MUTE PRE_MUTE AMP_MUTE TEST MODE TEMP_DETECT

ExplanationLD power control signal output. H:DVD L:CD Interrupt Request from USB Module. DVD LOADER control signal output. (PWM) VOL encoder Pulse-B input VOL encoder Pulse-A input Chip Enable output to USB Module. Status signal input from USB Module. Serial Interface data input.(RS232C) Serial Interface data output.(RS232C) Serial Data output to USB/IPOD Positive power Serial Data input from USB/IPOD GND Serial Clock output to USB Module Reset Signal output to USB Module. Serial Data output to ESS Serial Data input from ESS Serial Clock input from ESS ESS Active Signal input. DVD LOADER CLOSE SW signal input. L: CLOSE DVD LOADER OPEN SW signal input. L: OPEN DVD LOADER CLOSE signal output. DVD LOADER OPEN signal output. Reset Signal output to DVD. L: RESET Reset Signal output to EXT PLL. L: RESET Clock select signal output for digital audio signal from DVD Drive Power ON/OFF output. H: Power ON Select signal output for COMPONENT VIDEO OUT. Mute signal output for VIDEO2. HEAD PHONE insert detect signal input. H: Detected TRIGGER OUT. H:OUT Front AUX IN insert detect signal input. H: Detected Serial Clock output to control LED. Serial Data output to control LED. Signal output to SW of USB Module. H: ON Serial Clock output to control BU2090(VIDEO CONVERT) Serial Clock output to control BU2090(VIDEO CONVERT) Serial Clock output to control BU2090(VIDEO CONVERT) Serial Clock output to control BU2090(VIDEO CONVERT) Detect Composite signal input. Detect S-VIdeo signal input. DSP Mute Output MUTE output at DSP Error. Signal output to SW summing control. Select DSP input. Select MIX/MULTI of ESS Output. H:MIX Main POWER ON/STANDBY switching output. H:ON MUTE output to SCART Audio Output. H:MUTE iPOD ID connect output SP RELAY ON/OFF output. H:ON MUTE output to HEAD PHONE output. L:MUTE MUTE output to PRE OUT. L:MUTE MUTE output to POWER AMP IC. L:MUTE For TEST MODE input. Temperature Detect signal input from posister

43

S-301PIN NO82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

Port FunctionP122 P121 P120 VCC2 P30 VSS P27 P26 P25 P24 P23 P22 P21 P20 /INT5 P16 /INT3 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 P117 P116 P115 P114 P113 P112 P111 P110 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AVSS AN0

Port settingO O O O O I I O O O O O I O I O I O O O O I O O O O I O O O O O O O I I AD AD AD AD AD AD AD AD

Port NameNot Used: N. C. DIR RST CLATCH CODEC_RST TU_POWER STEREO TUNED TMUTE SAN CE SAN DI SAN CK SAN DO DFRES REMOTE SYR DIR DOUT DIR/CODEC DIN DIR/CODEC CLK DIR CE E2P DI E2P DO E2P CK E2P CS USB/IPOD IPOD_CHARGE IPOD_CONNECT VPP R/W DSP_IO_POW DSP_CORE_POW DSP_OSC_ON ROM_RST DSP_RST BUSY EPROM FLAG3A DIMMER IN SLIDE SW1 IN SLIDE SW2 IN CONNECT IN MODE2 MODE1 KEY-0 KEY-1 Reset output to DIR Latch Output to AD1837. Positive power Reset output to AD1837 GND

Explanation

TUNER Power ON/OFF output. H: Power ON "STEREO" indicator input from FM/AM TUNER pack "TUNED" detect input from FM/AM TUNER pack MUTE output to TUNER. L:MUTE Chip Enable output to PLL/RDS/VR IC Serial Data input from PLL/RDS/VR IC Serial Clock output to PLL/RDS/VR IC Serial Data output to PLL/RDS/VR IC Reset Input from ESS. L:RESET Not Used: N. C. Remote Control signal input Reset output to RDS IC Serial Data input from DIR. Serial Data output to DIR. Serial Clock output to DIR. Chip Enable output to DIR. Serial Data output to EEPROM Serial Data input from EEPROM Serial Clock output to EEPROM Chip Enable output to EEPROM Select USB/iPOD port. H:USB iPOD Charge Power ON/OFF output. H:Charge. iPOD Connect detect signal input. L:Connected DSP rom (VPP) write Mode. L: UNLOCK(3.3V) DSP rom Write/READ. DSP IO Power Output. H:OFF DSP CORE Power Output. H:ON DSP OSC On Output. Reset output to DSP ROM. Reset output to DSP. EPROM BUSY signal input from DSP. Control signal input from DSP. Input signal from sensor of illumination Select signal input of Video Signal. H: HDMI/M: PROGRE/L: INTINTERLACE Select signal input of Aspect. H: WIDE M: LB L: PS Detect signal input with DSW-S101. H: Connected with only Satellite SP. M: OK L: Connected with only SW. Initial Setting input for Region No of DVD. Initial Setting input the destination.(E2,E3) Unit Operation Button input0 GND Unit Operation Button input1

44

S-301

HY57V6432320DTP (IC404: 1U-3692)PIN CONFIGURATIONVDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 N.C VDD DQM0 WE CAS RAS CS N.C BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD N.C DQ16 V SSQ DQ17 DQ18 VDDQ DQ19 DQ20 V SSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 N.C VSS DQM1 N.C N.C CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS N.C DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS

BLOCK DIAGRAMI/O Control LWE

Data Input Register

LDQM

Bank Select 512K x 32 Sense AMP 512K x 32 512K x 32 512K x 32 Refresh Counter

Output Buffer

Row Decoder

Row Buffer

DQi

Address Register

CLK ADD

Column Decoder Col. Buffer Latency & Burst Length

LRAS

LCBR

LCKE LRAS LCBR LWE LCAS

Programming Register LWCBR LDQM

Timing Register

CLK

CKE

CS

RAS

CAS

WE

DQM

PIN FUNCTION DESCRIPTIONPin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down mode. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, Column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No connection on the device.

CKE

Clock enable

A0 ~ A10 BA0,1 RAS CAS WE DQM0 ~ 3 DQ0 ~ 31 VDD/VSS VDDQ/VSSQ NC

Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No Connection

45

S-301

BD3811K1 (IC504: 1U-3694)

AGND10

ROUT32

ROUT31

ROUT22

ROUT21

ROUT12

ROUT11

GOUT2

AGND9

GOUT1

VIN2

80 IN31 IN32 IN41 IN42 IN51 IN52 IN61 IN62 IN71 IN72 IN81 IN82 INDVDSR INDVDSL INDVDC INDVDSW OUT2(+) OUT2(-) OUT1(+) OUT1(-) IN1DSP IN1MIX IN2DSP IN2MIX 1 2 3

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65 64 63 62 TNF2 TNF1 BNF11 BNF21 BNF12 BNF22 BBNF2 OUT2 BBNF1 OUT1 AGND8 AGND7 VCC AGND6 VEE AGND5 MUTE CL DA DGND AGND4 GOUTSR VINSR AGND3

TREBLE 4 5 BASS 6 7 8 9 10 11 12 13 14 15 16 17 LOGIC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 5.1ch Mode SW1 47 46 45 44 43 42 41 5.1ch Mode SW2 DVD BASS BOOST 59 58 57 56 55 54 53 52 51 50 49 48 61 60

5.1ch Mode SW2 DSP

GOUTSW

OUTSW

INDSPSW

INDSPSR

INDSPSL

46

GOUTSL

VINSW

GOUTC

OUTC

OUTSL

OUTSR

INDSPC

AGND1

AGND2

VINSL

VINC

VIN1

IN22

IN21

IN12

IN11

S-301

M66005-0001AHP (IC301: 1U-3681)

SEG02 SEG01 SEG00 Vcc2 DIG15/SEG39 DIG14/SEG38 DIG13/SEG37 DIG12/SEG36 DIG11 DIG10 DIG09 DIG08 DIG07 DIG06 DIG05 DIG04

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

M66005-0001AHP

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 Vp SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33

BLOCK DIAGRAMDisplay code RAMBank 1 : 8bit x 16 Bank 2 : 8bit x 64code write dot data write data

CGROM

(35bit x 160)

Segment output circuit

59 . . . . . . . . .

SEG00

33 SEG26SEG27

CGRAM(35bit x 16)

31 . . . . . . . . .

24 SEG34

CS 14 SCK 15 SDATA 16

Serial receive circuit

XIN 21 XOUT 20

Clock generator

RESET 13

timing clock

Code/ command control circuitcode select

23 SEG35

Segment/ Digit select/ output circuit

64 SEG36 63 62DIG13/ SEG37 DIG14/ SEG38 SEG39

DIG12/

61 DIG15/

Display controller

scan pulse

Digit output circuit

. . . . . . . . .

12 DIG00

1 DIG11

Vcc1 19 Vcc2 60 Vss 22 Vp 32

2

18 P0 17 P1

47

S-301

TAS5066 (IC805: 1U-3683)AVDD_OSC XTL_IN XTL_OUT AVSS_OSC DVSS PWM_AP_1 PWM_AM_1 VALID_1 PWM_AP_2 PWM_AM_2 VALID_2 PWM_AP_3 PWM_AM_3 VALID_3 NC NC64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

NC MCLK_IN AVDD_PLL PLL_FLT_OUT PLL_FLT_RET AVSS_PLL NC DVSS1 RST ERR_RCVRY MUTE PDN SDA SCL CS0 DVSS1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

DVDD_RCL DVSS_RCL NC DVDD_PWM DVSS_PWM PWM_AP_4 PWM_AM_4 VALID_4 PWM_AP_5 PWM_AM_5 VALID_5 PWM_AP_6 PWM_AM_6 VALID_6 NC NC

1.2

Functional Block DiagramVREGA_CAP VREGB_CAP VREGC_CAP DVDD_PWM DVSS_PWM DVDD_RCL DVSS_RCL AVDD_PLL AVSS_PLL

MCLK_IN XTAL_OUT XTAL_IN DBSPD M_S PLL_FLT_OUT PLL_FLT_RET SCLK LRCLK MCLKOUT SDIN1 SDIN2 SDIN3 DM_SEL1 DM_SEL2 Clock, PLL and Serial Data I/F Signal Processing PWM Ch. PWM Ch. PWM_AP_1 PWM_AM_1 VALID_1 PWM_AP_2 PWM_AM_2 VALID_2

DBSPD CLIP SDIN1 SDIN2 SDIN3 MCLK_OUT SCLK LRCLK DVDD DVSS1 NC DEM_SEL2 DEM_SEL1 M_S DVSS1 DVSS1Power Supply PWM Section

Output Control

PWM AP_3 PWM AM_3 VALID_3 PWM_AP_4 PWM_AM_4 VALID_4

SDA SCL CSO

Serial Control I/F

Auto Mute De-Emphasis Soft Volume Error Recovery Soft Mute Clip Detect

PWM Ch.

PWM Ch.

PWM_AP_5 PWM_AM_5 PWM Ch. VALID_5

RESET PDN

Reset, Pwr Dwn and Status

CLIP MUTE ERR_RCVRY

PWM Ch.

PWM_AP_6 PWM_AM_6 VALID_6

48

S-301

ADV7310 (IC302, 501: 1U-3692)GND_IO CLKIN_B S9 S8 S7 S6 S5 DGND VDD S4 S3 S2 S1 S0 S_HSYNC S_VSYNC

ADV7300 (MA: IC706)

VDD_IO Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 VDD DGND Y8 Y9 C0 C1 C2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

TOP VIEW

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

S_BLANK R SET 1 VREF COMP1 DAC A DAC B DAC C VAA AGND DAC D DAC E DAC F COMP2 R SET 2 EXT_LF RESET

ADV7310 Terminal FunctionPin No. 1 2~9, 12, 13 10, 56 11, 57 14~18, 26~30 19 20 21 22 23 24 25 31 32 33 34 35, 47 36,45 37 38 39 40 41 42 43 44 46 48 49 50 51~55, 58~62 63 64 Pin Name VDD_IO Y9-0 VDD DGND C9-0 SPI/I2C ALSB_SO SDA_CLKSP SCLK_SI P_HSYNC P_VSYNC P_BLANK RTC_SCR_TR CLKIN_A RESET EXT_LF RSET1,2 COMP DAC F DAC E DAC D AGND VAA DAC C DAC B DAC A VREF S_BLANK S_VSYNC S_HSYNC S9-S0 CLKIN_B GND_IO I/O P I P G I I I/O I/O I I I I I I I I I O O O O G P O O O I/O I/O I/O I/O I I G

C3 C4 SPI/I2C ALSB_SO SDA_CLKSP SCLK_SI P_HSYNC P_VSYNC P_BLANK C5 C6 C7 C8 C9 RTC_SCR_TR CLKIN_A

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Function Digital power supply. 10-Bit Progressive scan/ HDTV input port for Y data. Digital power supply. Digital Ground 10-Bit Progressive scan/ HDTV input port for CrCb color data in 4:2:2 input mode. When this input pin is brought low, the ADV7300 interfaces over the SPI port and uses this input as part of the 4 wire SPI interface. When this input pin is tied high [VDD_IO], the ADV7300 interfaces over the I2C port. Multifunctional pin. Multifunctional pin. Multifunctional input. Video Horizontal Sync Control Signal for HD sync in simultaneous SD/HD mode and HD only mode. Video Vertical Sync Control Signal for HD sync in simultaneous SD/HD mode and HD only mode. Video Blanking Control Signal for HD sync in simultaneous SD/HD mode and HD only mode. Multifunctional input. Pixel Clock Input for HD only or SD only modes. This input resets the on-chip timing generator and sets the ADV7300 into Default Register setting. Reset is an active low signal. External Loop filter for the internal PLL. A1520 Ohms resistor must be connected from this pin to AGND and is used to control the amplitudes of the DAC outputs. Compensation Pin for DACs. In SD only mode: Chroma/RED/V analog output. In HD only mode and simultaneus HD/SD: Pb/ BLUE (HD) analog output. In SD only mode: Luma/BLUE/U analog output. In HD only mode and simultaneus HD/SD: Pr/ RED (HD) analog output. In SD only mode: CVBS/GREEN/Y analog output. In HD only mode and simultaneus HD/SD: Y/ GREEN (HD) analog output. Analog Ground Analog power supply. Chroma/ RED/ V SD analog output. Luma/ BLUE/ U SD analog output. CVBS/ GREEN/ Y SD analog output. Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235V). Video Blanking Control Signal for SD. Video Vertical Sync Control Signal for SD. Video Horizontal Control Signal for SD. 10-Bit Standard Definition input port. Or Progressive Scan/ HDTV input port for Cr [Red/V] color data in 4:4:4 input mode. Pixel Clock Input. Digital Ground

49

S-301

CXD1881AR (IC802: 1U-3692)

SDATA

MNTR

SDEN

SCLK

V125

48 RX 49 MEV 50 VNA 51 FNN 52 FNP 53 DIP 54 DIN 55 BYP 56 RFAC 57 VPA 58 AIP 59 AIN 60 ATON 61 ATOP 62 RFSIN 63 RFDC 64

47

46

45

44

43

42

41

40

39

38

37

36

35

34

LINK 33 32 31 30 29 28 27 26 MEVO MIN MLPF MB MP MIRR LDON VNB CDPD DVDPD COLD DVDLD VC VPB CD_E CD_F 25 24 23 22 21 20 19 18 17 16 CD_A

LCN

TPH 14 CD_C

LCP

CXD1881AR

1DVDRFP

2DVDRFN

3A2

4B2

5C2

6D2

7CP

8CN

9D

10 C

11 B

12 A

13 CD_D

50

CD_B

DFT 15

V33

V25

CE

FE

TE

PI

S-301

Block DiagramATON RFAC ATOP FNN FNP

DIN

62

61

60

59 FCCR b7-0 FBCR b6-0 AGC

53

52

55

54

DIP

AIN

AIP

57 AGC HOLD RFCR b3 CGR b1 OUTPUT INHIBIT HOLDEN CDR b6

DVDRFP DVDRFN

1ATT

2

MUX 4 2 SIGR b3 INPUT SEL SIGR b7-4 ATT

INPUT BIAS 2 RFCR b5-4 INPUT IMP SEL SSOUT

PROGRAMMABLE EQUALIZER FILTER DIFFERENTIATOR

FULL WAVE RECTIFIER

AGC CHARGE PUMP 56 BYP

RFSIN 63

RFCR b7-6 INPUT IMP SEL

AGCO Clamp & Env 2 CAR b3-2 SIGDET Level DAC

49 RX

2 CAR b1-0 Env/Clamp TENV A A 12 B CD_A 16 C B 11 D CD_B 15 MUX C 10 CD_C 14 DW/LPF GCA W/LPF GCA W/LPF GCA W/LPF GCA SIGR b2-0 12dB is added @ high gain mode (CDR b5=1) GCA

B+DSUM Amp.

CCR b4-0 FE offset 5 70kHz +/-6dB, 4bit Offset cancel GCA 4 FOCR b3-0 FO Gain 40 FE LPF PIOR b4-0 5 PI offset Offset cancel CTCR b7 BCA DET TOPHLD DAC 2 CBR b1-0 SEL 2 CAR b7-4 41 CE TE MASK SEL PI FE TE CE V25 V125 V25/3 PIOR b7-5 3 44 LCP 43 LCN COMP SEL CBR b3-2Buff

A+C

GCA +/-4dB 4 FOCR b7-4 FS Gain 70kHz LPF

Pll 38 PI 35 TPH 34 DFT 61 RFDC

A+DGCA GCA

2

9

CGR b0 OUTPUT INHIBIT

B+C CD_D 13GCA

3 PDCR b3 CD/DVD

CTCR b3-0 4 CO Gain TOPHLD TOPHLD Offset cancel 4 CER b4-0 CE offset RESUM GCA 0-+8dB, 4bit

4D SUM

SIGR b2-0 12dB is added @ high gain mode (CDR b5=1)

42 MNTR MON SEL

6dB is added @ high gain mode (CDR b5=1)

CD_E 18

GCA

+/-4dB CD_F 17GCA

+3dB

GCA 3 4

CFR b2-0 CE-ATT CFR b3 CEPOL

3

LPF ATT Pol sel. buff (12dB)

RFCR b2-012dB is added @ high gain mode (CDR b5=1)

TRCR2 b3-0 3B

CDR b5 High Gain

7 CP 8 CN

Comp.

A2 B2 C2 D2

3 4 5 6

GCA GCA GCA GCA

EQ EQ EQ EQVC

PHASE DETECTOR

MUX LPF

SUB

Offset cancel 6

GCA 3

TE RST

39 TE

PHASE DETECTOR

PDCR b3 CD/DVD

TRCR2 b7 CP/CN Low lmp

CEFDB

TRCR b5-0TR offset

CFR b7-5 TR Gainfor TE, FE & CE output ref.

3 3 RFCR b2-0 TRCR2 b6-4 DPD EQ

for PI output ref.

V25/3 V25/2 CDR b2 VCI for servo input VC CDR b3

TRCR b6 DPD COMP HYS ON CHR b7-6 Mirr Defect Comp ATT AGCO MRCR b6-4 MRCR b7-0 Mirr Comp droop rate ATT Level control CTCR b5-4 MEVO SEL 3 2BENV Pll

36 V125 37 V25 20 VC

CCR b5 APC SEL DVD/CD CDR b4 LD H/L

CONTROL Signals 2 To each block SERIAL PORT REGISTER

48 SDEN 47 SDATA 46 SCLK

Btm EnvAGC BTM ENV

TOP HLD TOP ENV BTM HLD

ATT ATT MUX MUX OffsetGCA

DVDPD 23 Dual APC CDPD 24

MUX

V33 for output buff 45 V33

MUX

Btm clamp & clip

Vref BTM ENV MUX CGR b5-4 Gain CDR b7 LINKEN MUX 33LINK

CCR b7 DISK DET 58VPA

26LDON

22CDLD

21DVDLD

50MEV

32MEVO

31MIN

28MP

29MB

30MLPF

27MIRR

19VPB

51VNA

25VNB

51

S-301

Power Supply PinsNameVPA VPB VNA VNB V33 V25

I/OPower for RF and serial port Power for servo GND for RF and serial port GND for servo Power for output buffer Reference Power for servo output

Function

Input PinsNameDVDRFP,DVDRFN RFSIN AIP,AIN DIP,DIN A,B,C,D A2,B2,C2,D2 CD_A,B,C,D CD_E,F MIN DVDPD CDPD LDON LINK

I/OI I I I I I I I I I I I I O RF signal input RF signal input AGC amp. input Analog input for RF single buffer Photo detector interface input Photo detector interface input CD photo detector interface input CD photo detector interface input RF signal input for mirror APC input APC input APC input ON/OFF (L:Open) Link signal input (L:Open) Mirror monitor output

Function

Output PinsNameATOP,ATON FNP,FNN RFAC RFDC FE TE CE MEVO DFT MIRR PI DVDLD CDLD MNTR

I/OO O O O O O O O O O O O O O Differential attenuator output Differential normal output Single end normal output RF signal output Focus error signal output Tracking error signal output Center error signal output RFDDC bottom envelope output Defect output Mirror detected output Pull-in signal output APC output APC output Monitor output

Function

52

S-301

Analog PinsNameBYP CP CN LCP LCN MP MB MEV MLPF TPH VC V125 RX

I/O-

FunctionRF AGC integration capacitor connecting terminal Differential phase tracking LPF terminal Differential phase tracking LPF terminal Lens shift offset cancel LPF terminal Lens shift offset cancel LPF terminal MIRR top hold terminal MIRR bottom hold terminal RFDC bottom envelope terminal Mirror LPF terminal PI top hold terminal Reference voltage output Reference voltage output Reference resistor input

Serial Port PinsNameSDEN SDATA SCLK

I/OI I/O I Serial data enable Serial data Serial clock

Function

53

S-301

M12L64164A (IC103: 1U-3692)W986416DH (MA: IC103)

VCC 1 DQ0 2 VCCQ 3 DQ1 4 DQ2