des03-comseq.reduce to 150 dpi average quality - standard
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Bräunl 2021
CHAPTER 3 Combinatorial and Sequential Circuits
Combinatorial Circuits• Only logic gates, no
feedback, no memory• No states• Equivalent to
mathematical function
Sequential Circuits• Logic gates with
feedback and memory• States• Equivalent to
computer program
Which one would you need for implementing:• Game show buzzer ?• Traffic Light ?• Washing machine ?
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Building Blocks
• Combinational Circuits• Flip-Flops• Register• Decoder• Multiplexer / Demultiplexer• Adder• Comparator
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1. Combinational Circuits• Everything is a combination of AND, OR, NOT gates
(or just NAND gates, or just NOR gates)• There are no feedback loops!• There is no memory,
every output line is a simple function of its inputs
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Gates
AND
OR
NOT
a b a AND b a OR b NOT a
0 0 0 0 1
0 1 0 1 1
1 0 0 1 0
1 1 1 1 0
a
b
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Gates
NAND
NOR
XOR
a b a NAND b a NOR b a XOR b 0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 0 0 0
a
b
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De Morgan’s Law
a b a NOR b a’ AND b’ 0 0
0 1
1 0
1 1
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ab
ab
Are theseidentical ?
Check withtruth table
A OR B = A AND B
A AND B = A OR B
De Morgan’s Law
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Combinatorial Circuits
• Arbitrarily complex circuits can be built fromAND/OR/NOT gates
• The output will only depend on the input lines(after some propagation delay)
• There is no memory.
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2. Decoder
“set corresponding Yi to ‘1’,all others to ‘0’ “
X0 Y0
Y1X1
Y3
Y2
X0X1
Y0Y1Y2Y3
0123
D
8
1
0
1
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Encoder
Y0
Y1
X0X1X2X3
Note: X0 is not used!
Y0
Y1
X0X1X2X3
0123
E
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“set Y to the binary equivalentto the Xi input line “
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Encoder and Decoder
0123
D0123
EY0
Y1
X0X1X2X3
X0X1X2X3
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3. Multiplexer
A
B
Z
S
Z : = (A AND S�) OR (B AND S)= A · S’ + B · S
1
0 A
S
B Z
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0/ 1
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Multiplexer (4-way)
Z
S1 S0
0123
A
D
BC
A
B
C
D
Z
S1 S0
0 1 2 3
D
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Multiplexer with multiple lines
Z
S1 S0
0123
A
D
BC
4
4
4
4
4
S1 S0
Z3
0123
A3
D3
B3
C3
Z2
A2
D2
B2
C2
Z1
A1
D1
B1
C1
Z0
A0
D0
B0
C0
0123
0123 0
123
130 1
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Demultiplexer
0
1
XA
B
“if S = 1 then B := Xelse A := X “
X
S
A
BS
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S1 S0
Demultiplexer (4 way)
0123
XA
D
X
S1 S0
0 1 2 3
D
C
B
A
BCD
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4. Half Adder
Y
XH
sum
carry
X Y carry sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
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Adding 2 input bits (X, Y)resulting in 2 output bits (sum, carry)
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Half Adder Implementation
Y
XH
sum
carry
XOR
sum
carry X
Y
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X Y carry sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
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Full-Adder (1 stage)
AC out C in
sum
X Y
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Adding 3 input bits (X, Y, Cin)resulting in 2 output bits (sum, Cout)
X Y Cin Cout sum
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
0 0 0 1 0 1 1 1
0 1 1 0 1 0 0 1
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Full-Adder Implementation (1 stage)
AC out C in
sum
X Y
H
H
X
Y
C in
sumC out
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Full Adder (n stages)4-bit adder
This is called a ripple carry adder – note propagation delay.Faster: “carry look-ahead“ adder.
C-1A A A AC3
S3 S2 S1 S0
X3 Y3 X2 Y2 X1 Y1 X0 Y0
C0C1 0C2
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5. Tri-Stateenable
X Y
En X Y
0 0 *
0 1 *
1 0 0
1 1 1
If enable is 0, output is �high-ohm� (not connected)If enable is 1, output equals input
21Diagram: electronics-tutorials.ws
Extension ofbinary logic
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Tri-State Implementation
enable
X
Y
En X Y
0 0 *
0 1 *
1 0 0
1 1 1
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Vcc
Gnd
Note: Never link two outputs together without tri-state !!
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6. Latches, Flip-Flops, Memory
• We now introduce a feedback loop• This will allow to “trap” a single bit of information• It is the smallest instance of a memory cell• Required functions:
– Change the bit (set to 1 or reset to 0)– Read the current bit value
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Memory
If the first input is 0, a 0 gets fed back into it
If the first input is 1, a 1 gets fed back into it
0 0
01 1
1
This circuit will hold its state forever - stable
24Source: Boussaid
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Memory
25Source: Boussaid Bräunl 2021
Memory
26Source: Boussaid, Bräunl
Qnew = NOR(R, NOR(Qold, S))
Consider all cases:R S Qnext0 0 __0 1 __1 0 __1 1 not allowed
unchanged10
S
R
Q
Q�
t
S
R
Q
Q�
t
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Memory
27Graph: Boussaid
What happens if R,S are both set to 1, then reset to 0?•Uncontrolled oscillation•That’s is why this state is illegal
R
SQQ’
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Memory
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Note:•This circuit’s output Qnext (aka Q+) does depend not only on its inputs R, S – but also on its previous state Q.•This means we have built a sequential circuit. This is nolonger a combinatorial circuit.•We achieved this by using a feedback connection.•We built the smallest instance of a memory cell (1 bit).•The desired initial state (after power-on) is Q=0.However, depending on used chip, initial state may be random.
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Memory
29Source: Fairchild Bräunl 2021
7. Level-Triggered Latches (Flip-Flops)
R
S
Q
RS LatchHow to use: How to build:
Q'
S Q
R Q'
S and R must not be 1 at the same time!30
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Level-Triggered Latches (Flip-Flops)
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D-Latch with EnableHow to use: How to build:
D Q
En
R
S
Q
QD
En
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8. Edge-Triggered Flip-Flops
Q+ = DD Q
clk
D–Flip-Flop
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trigger on rising edge
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Edge-Triggered Flip-Flops
Trigger on rising clock edge
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D Q
clk
Clock
Q
D
Graph: Boussaid Bräunl 2021
Edge-Triggered Flip-Flops
QD
clk
Q+ = D
trigger on falling edge
D–Flip-Flop
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Q
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Edge-Triggered Flip-Flops
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D Q
clk
Trigger on falling clock edge
D
Q
Clock
Graph: Boussaid Bräunl 2021
Implement Edge-Triggering Flip-Flop
Master-Slave Method:• clk 0: Slave changes• clk 1: Master changes
Overall:• Rising edge triggered
D QMaster
En
D QSlave
En
clk
D Q
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JK-Flip-Flop
JK
QQ+ = J · Q� + K’ · Q
Edge triggered, similar to RS-FF, but it flips its state when both J=K=1
clk
J K Q(t+1) Operation0 0 Q(t) No change0 1 0 Reset1 0 1 Set1 1 Q’(t) Complement
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JK-Flip-FlopQ+ = J · Q� + K’ · QHow to build
R
S
Q
QJ
KQ
Qclk
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9. Registers• Several flip-flops can be combined into one register.• An n-bit register is a group of n binary storage cells (flip-flops).
• Registers are classified according to the number of bits of storage and operating mode:
– parallel in – parallel out (PIPO) ç standard, this is what we’ll use– parallel in – serial out (PISO)– serial in – parallel out (SIPO)– serial in – serial out (SISO)– universal (control signals for either serial or parallel op.)
• Registers are commonly used as temporary storage in a processor.– They are faster and more convenient than main memory.– More registers can help speed up complex calculations.
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Register Example
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• Basic registers are easy to build. We can store multiple bits just
by putting a bunch of flip-flops together!
• 4-bit register is (right), and its internal implementation (below).
– All the flip-flops share a common CLK (clock) and CLR
(clear) signal.
40Source: Boussaid
• A shift register �shifts� its output once every clock cycle.• SI is an input that supplies a new bit to shift �into� the register.• E.g., on some positive clock edge we have: SI = 1
Q0-Q3 = 0110
then the next state will be: Q0-Q3 = 1011• The current Q3 (0 in this example) will be lost on the next cycle.• The circuit and example make it look like the register shifts �right�,
but it depends on your interpretation of the bits. If you consider Q3 to be the most significant bit instead, then the register is shifting in the “left”!
Q0(t+1) = SIQ1(t+1) = Q0(t)Q2(t+1) = Q1(t)Q3(t+1) = Q2(t)
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Shift Registers
41Source: Boussaid Bräunl 2021
Registers
Trigger e.g. rising edge
Register00
clock
A
Z
Equivalent to:Bank of D Flip-Flops
D Q D Q D Q D Q
clock
A
Z42
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10. Clock
43Source: electronics-tutorials.ws
Symbol
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11. Real Hardware
For experimenting use a breadboard (proto-board)Connections
LEDs and Resistors
Note: LEDs have polarity. The longer pin is “+”
+ – BlackBrownRed
OrangeYellowGreenBluePurpleGrayWhite
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Data-sheets
Source: National Semiconductor
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NOR Chip CD4001See http://robotics.ee.uwa.edu.au/courses/des/labs/datasheets/
Source: National Semiconductor Bräunl 2021 48
NOR Chip CD4001• Place chip over middle row on proto-board
(so no pins are connected with each other)• Make sure to connect power and ground!
+ 3.3Vor 5V
–
+ –
330 Ohm
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NAND Chip CD4011See http://robotics.ee.uwa.edu.au/courses/des/labs/datasheets/
Source: National Semiconductor Bräunl 2021 50
Flip-Flop Chip CD4013Note: Some FF have a random initial state.These FF require a power-up reset circuitusing a capacitor to Vcc and a resistor to Gnd.
Source: National Semiconductor
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Hardware Simulators for Testing
• Fritzinghttp://fritzing.org/home/
• Retrohttp://robotics.ee.uwa.edu.au/retro/
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QUIZ
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ABC
A. A·B·C
B. A·B + C
C. A·B + C’
D. A+B · C’
http://robotics.ee.uwa.edu.au/quiz/
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A. 8
B. 12
C. 16
D. 20
http://robotics.ee.uwa.edu.au/quiz/
Delaysteps
C-1A A A AC3
S3 S2 S1 S0
X3 Y3
X2 Y2 X1 Y1 X0
Y0
C0C1 0C2
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A. 9
B. 10
C. 11
D. 12
http://robotics.ee.uwa.edu.au/quiz/
Delaysteps
A A A HC3
S3 S2 S1 S0
X3 Y3 X2 Y2 X1 Y1 X0 Y0
C0C1C2
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A. 0, 1, 0, 1, 0, 1
B. 1, 0, 0, 0, 1
C. 1, 0, 1
D. 0, 0
http://robotics.ee.uwa.edu.au/quiz/
D Q
clk
clock
D
Q ??
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