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Description and implementation of a single boardcomputer for industrial controlPiecha, J.

Published: 01/01/1981

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Citation for published version (APA):Piecha, J. (1981). Description and implementation of a single board computer for industrial control. (EUT report.E, Fac. of Electrical Engineering; Vol. 81-E-120). Eindhoven: Technische Hogeschool Eindhoven.

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Description and Implementation of a Single Board Computer for Industrial Control

by

J. Piecha

Eindhoven University of Technology Research Reports

EINDHOVEN UNIVERSITY OF TECHNOLOGY

Department of Electrical Engineering

Eindhoven The Netherlands

DESCRIPTION AND IMPLEMENTATION

OF A SINGLE BOARD COMPUTER FOR

INDUSTRIAL CONTROL

By

J. Piecha

EUT Report 81-E-120

ISBN 90-6144-120-X

Eindhoven

June 1981

- i -

Piecha, J.

DESCRIPTION AND IMPLEMENTATION OF A SINGLE BOARD COMPUTER FOR INDUSTRIAL CONTROL. Department of Electrical Engineering, Eindhoven University of Technology, 1981. EUT Report 81-E-IZO

Abstract.

The report contains a description of a single board computer based on the Intel 8085 microprocessor. It includes the features: 4K bytes uv erasable programmable read-only-memory, which can be extended to 8K bytes, 8K bytes of random-access-memory, two full duplex serial interfaces, parallel interface (48 lines), programmable timers, programmable interrupt controller and keyboard/display controller. The debug monitor program was also elaborated and a short description of this program is presented in this report.

Present address of the author:

Jan Piecha, Uniwersytet Sl.ski, Katowice, Poland

- ii -

Acknowledgements

The author would like to thank the members of the Digital Systems

Division of the Electrical Engineering Department of Eindhoven Univer

sity of Technology for their kind help in realisation of this project,

especially Ir M.P.J. Stevens, Ir H. Kemper and lng. C.H. Van Hooidonk.

The help of Professor A. Heetman in organizing the autor& study is also

greatly appreciated.

- iii -

Table of contents

1. Introduction

2. General description of the computer

2.1 The block diagram comments

2.2 Memory and I/O addressing

2.3 Components specification

3. Specifications of single board computer

3.1 Serial communication

3.2 I/O addressing

3.3 Interface compatibility

3.4 Connector assignment

3.5 Jumpers configuration

4. Description of the debug monitor program

4.1 Capabilities of the program

4.2 Monitor commands

4.3 I/O devices, drivers

4.4 System initialisation

4.5 The RAM storage and interrupts location

4.6 Specifications of routines accessible for the

5. Conclusion

6. References

Page

1

2

2

4

7

10

10

11

11

11

13

18

18

18

19

19

20

user 21

25

26

Single Board Computer Jan Piecha 1.

1. Introduction

The single board computer described in this report has been built and

tested by the author during his SmIs.%arl.~. in the Electrical Engineering

Department of T.R. Eindhoven.The configuration and main set of components

have been defined in the Digital Systems Division. This computer vas pla

ced on a single printed circuit assambly with an optional Keyboard/Dis -

play board. The board of the computer includes a 8085 processor (CPU),

4K bytes (2716) or 8K bytes (2732) EPROMs, two serial (8251) and six pa

rallel (2x 8255) I/O ports, a Programmable Timer (8253), a Programmable

Interrupt Controller (8259) and a Keyboard/Display Controller (8279).The

debug monitor program, which can be placed in 2K bytes of EPROM, vas

elaborated for this system. The block diagram of this computer was presented in Fig.1 •

Single Board Computer Jan Piecha

2. General description of the computer

2.1 The block diagram comments

The microcomputer mentioned in Fig.1 is composed of the folloving

main parts :

- 8085 microprocessor (CPU),

- ROM 2716 or 2732 and RAM 8185,

- serial I/O interface 8251,

- parallel I/O interface 8255,

- programmable timer 8253,

- programmable interrupt controller 8259,

- keyboard/display controller 8279.

The control, data and address lines are connected as follovs:

- RD and WR lines of the processor are connected with every compo

nent via line drivers,

2.

- data bus of the computer is driven by the drivers 8286, the trans

mission direction of 8286 is controlled by the data bus drive 10 -

gic,

- lover bus address of the processor is externally latched in the

8282 Ie,

- interrupt inputs : TRAP, RST 7.5, RST 6.5, RST 5.5 of the processor

are connected vith jumpers in interrupt matrix,

- interrupt input INTR of processor is connected vith interrupt con

troller 8259,

- the address lines are used to select a cell of the memory or I/O

interface (memory mapped I/O),

- address lines AO,A1 are also used as control lines for every pro

grammable block,

- the standard clock cristal 6.144 MHz vas applicated in this system.

The chip select block is controlled by A15~ ~ and A6

,A5

,A4

address

lines.Fulldeecription of this selection is presented in the next chapter.

The ROM block contains tvo 2716 (4K bytes) or tvo 2732 (8K bytes)

chips. Tvo different capacities of the ROM are available by the jumpers

used in this computer (compare Table 12). The RAM block hae the capacity


of 8K bytes and is composed of eight 8185 chips. Both ROM and RAM chips

are selected by CS and R/w lines.

3.

The Programmable Timer 8253 can be software programmed to a fev modes

[2) • Its three otputs (02,01,00) of three counters can be used as a clock

control lines for TxC and RxC inputs of 8251 and to generate the one-shot

pulse for a single step procedure. The jumpens installed on the board give

the possibility to choose the most convenient version of these controls.

Tvo 8255 IC allov the user to connect to the computer 48 parallel I/O

lines, which can be individually software programmed (2)'. Lines PCO and

PC3

of both 8255 can be programmed to interrupt the work of the computer.

The interrupt version can be chosen by the set of jumpers installed on the

board (compare tables 13, 14 and 18). Lines PCi of the 8255-0 can be used

as a programmable clock for the timer and as a programmable gate enable

signals for GO and G1 of the timer. The ring indicator and data carry de

tect can be detected on the PCi lines of the 8255-1.

The serial I/O communication can be done by two 8251 chips. The jum -

pars installed on the board and the timer allow the user to choose the

most covenient version of the serial I/O communication. The frequencies

of RxC and TxC of both serial I/O interfaces can be different and can be

programmed by the timer or forced externally. Lines RxRDY and TxRDY of both

8251 can be used to provide the interrupt signal to the interrupt control-

ler.

The computer contains Keyboard/Display controller 8279 which allows

the user to connect the Keyboard/Display board. This board allows simple

commands and datas to be entered in the computer, to test the resuls of

the computer work, etc.

Multi-level priority interrupts are available in this computer not

only by the facilities of the TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR of

the 8085 3 but due to Programmable Interrupt Controller which is also

installed on the board (2) •

-------------

Single Board Computer \

Jan Piecha

2.2 Memory and I/O addressing

The presented computer is designed to satisfy a variety of applioa

tions.Therefore the user needs to install only those components which

4.

are necessery in his particullar configuration. The address of the system

vas devided into three parts: ROM, RAM and I/O interfaces. The space

OOOOH to OFFFH vas reserved for EPROM, 2000H to 3FFFH for RAM and 400xH

to 407xH for I/O interfaces. The last part of the address space is unused.

Each of these blocks is., divided into a few integrated circuits. As it

is shown in Table 1. EVe~ Input/Output data transfer is realised by a memory Read/Write command (memory-mapped I/O).

Each chip is selected as follows:

a) Group Selection (GS)

A14 A13 GS

0 0 ROM

0 1 RAM

1 0 I/O

1 1 free space

b) ROM address space

4K blocks (2732) , CS - chip select

A12= 0 , CSO= 0 (active)

(active)

o - lov level (positive logic) , 1 - high level

vhere:

CSO= A14v A13 v A12 - lover 4K

CS1= A14 v A13 v A12 - higher 4K

2K blocks (2716) ,

Single Board Computer

Table 1 Address Assignments

Memory,Interface

EPRCM

2716 - 0

2716 - 1

EPRCM

2732 - 0

2732 - 1

RAM

8185 - 0

8185 - 1

8185 - 2

8185 - 3

8185 - 4 to 7

8251 - 0

- 1

8255 - 0

- 1

8259

8253 8279

n.e.

Jan Piecha

Address Space

,

000 0

o 7 F F 080 0

OFFF

0000

OFFF 1 000

1 F F F

20 0 0

23F1 240 0

2 7 F F

2 80 0

25FF 2 COO

2 F F F

3 0 0 0

3 F F F

400 x

401 x

402 x

403 x

4 0 4 x 40 5 x 406x

407 x

5.

Single BOard Computer Jan Piecha 6.

vhere:

CSO = A'4 v An v A" - lover 2K

CS,= A'4 v An v A;, - higher 2K

c) RAM address space

A12A11A10 CS - 8,85

0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 each chip lK byte (~.;. Aa) 1 0 1 5 1 1 0 6 1 1 1 7

d) 1/0 space

~ A5 A4 CS for interface

0 0 0 8251 - 0 0 0 1 8251 - 1 0 1 0 8255 - 0 0 1 1 8255 - 1 1 0 0 8259 1 0 1 8253 1 1 0 8279 1 1 1

Full address of interface device is Bupplemented by AO,A1

address line va

lues, vhere:

8251 - 0 is addressed: 4000 - Data 4001 - status, Control

8251 - 1 4010 - Data 4011 - StatuB, Control

8255 - 0 4020 - Port A (1) 4021 - Port B (2) 4022 - Port C (3)

8255 - 1 4030 - " (4) 4031 - II· (5) 4032 - II (6)

8259 4040 4041

8253 4050 - Counter 0 4051 - 1 4052 - 2 4053 - Mode


8279 is addressed 4060 - Data 4061 - Command/Status

These section blocks have been built on OR gates (chip A9) and de

multiplexers 8205 (chips A15 and A16) and are mentioned on sheet No.2

of Fig.2 • The complete schematic diagram of the computer is presented

on five sheets of Fig.2 and includes:

- Central Processor Unit,

- Memory and Chip Select,

- Serial Interface, Timer and Interrupt Controller,

- Parallel Interfaoe,

- Keyboard/Display Controller.

Sixth sheet contains scme of external board - Keyboard/Display Unit

( Fig • .3 ).

Grid references to each part of diagram consist of four alphanume

ric characters. For example 2ZB1 signifies sheet 2 zone B1.

2 • .3 Components specification

• ••

All the components used in the computer are listed in Tables: 2, .3,

, 7 mentioned below •

Table 2 Parts list for CPU block (sheet 1)

Chip Assignment Function Type No.of campon.

1 2 .3 4

A 0 microprocessor 8285 1

A 7 address bus latch 8282 1

A 8 system clock drive 7474 1

A .39 driver 7404 4/6

A 47 driver 7408 .3/4 A 48 data bus driver 8286 1

- cristal 6.144 1

- capacitor 4.7 uF/50V 1

- " 20 pF/25V 2

- resistor 2.2k/0.1W 4

- " 470 ohm/ 1/4 W 1

7.


Table 2 Continued

1 2 3 4

- diode (LED) MV5153 1

- diode 1N914 1

Table 3 Parts list for memory, Chip select block (sheet 2)

1 2 3 4

A 1, A 2 EPROM 2716 or 2732 2

A 3, A 4, •• .. , A 7 RAM 8185 8

A 15, A 16 Demultiplexers 8205 2

A9 OR gate 741S32 3/4

A 39 Invertor 7404 1/6

B 1 Jumper - 1

Table 4 Parts list for Serial I/O, Timer, Interrupt Controller (sheet 3)

1 2 3 4

A10,A11 Serial I/O 8251 2

A 12 Programmable Timer 8253 1

A 19 Programmable Inter-

rupt Controller 8259 1

A 20, A 21,

A 23, A 24 Data Receiver 1489 4

A 22, A 25 Data Tranemitter 1488 2

- NOise Capacitor 390 pF 6

A 38 OR gate 7432 1/2

- NOise Capacitor 220 pF S

B 2, B 3, Jumper -B 6, B 7 4

A 39 driver 7404 1/6


Table 5 Parts list for Parallel r/o block (sheet 4)

1 2 3

A 13, A 14 Parallel r/o 8255 14 pin 80C- undefi-kets for inter- ned dri-face driver vers

B 4, B 5 Jumper -- Resistor 2.2kjO.1W

Table 6 Parts list for Keyboard/Display block (sheet 5)

1 2

A 17 Keyboard/Display

A 40, A 41 Driver

A42

The jumpers are installed to allow.the user:

- to select 2716 or 2732 EPROMs,

3

8279

7407

- to choose a covenient configuration of interrupts,

- to select a suitable baud rate, aerial clock

2

4

2

12

2

1

4

1

1/6

-to select an actual combination of serial and parallel r/o ports

- to select timer/counter functions.

A fuJldescription of the jumpers is presented in the next chapter of this

manual.

9.

Single Board Computer Jan Piecba

3.Specifications of single board computer

3.1 Serial communication

Two serial I/O devices can be connected with the computer. The I/O

devices can work in two different modes :

- synchronous : 5,6,7 or 8 bit characters,

1 or 2 SYNS characters ,

automatic SYNS insertion ,

- asynchronous :5,6,7 or 8 bit characters,

brake character generation ,

1,11/2,2 stop bits,

false start bit detection.

Different frequencies of the serial transmission are programmed with

the interval timer l8253). Sample baud rates for synchronous and asyn

chronous tr8.B8ll1sPOIl are presented in 1:able 8. The system clock fr_

quency is equal to 3.072 MHz while the input frequency of the interval

timer is 1.536 MHz.

Table 8 Sample Baud Rates for serial transmission

Frequency kHz Baud Rate [Hz]

(software selectable) Asynchronous Synchronous

Frequency factor

16 x 64 x

153.6 - 9600 2400

76.8 - 4800 1200

38.4 ·38400 2400 600

19.2 19200 1200 300

9.6 9600 600 150

4.8 4800 300 75

2.4 2400 150 -1.76 1760 110 -

10.

Single Board Computer Jan Pieoha

3.2 I/O addressing

Communication with Parallel and Serial Ports, Timer, Interrupt Controller and Keyboard/Display Controller is via memory read/write

commands ( Mn.lR, Mn.lW ) !'rom the CPU.

3.3 Interface compatibility

Parallel 48 programmable lines (6 ports), IC sockets included for

user instalation; as port interfaces.

Serial I/O: serial ports, EIA standard RS232C signals provided and supported:Receive Clock, Transmit Clock, Receive Data,

Transmit Data, Request to Send, Clear to Send, Data Set

ieady, Data Terminal Ready, Cl!rier Detect, Ring Indicator.

3.4 Connector assignment

The PC board of the computer is connected with external devices

by connectors mentioned in table 9.

Table 9 Connectors"

*

. Function No. of Inches Connector Assignment

Pairs/Pins type

Parallel 25/50 0.1 Flat J1,J2

I/O Connector Crimp

Serial :0/26 0.1 Flat J3,J4

I/O Connector Crimp

Keyboard/ 25/50 0.1 Flat J5

Display Crimp

Power supply 4 - Mollex P1

The transmition path !'rom SBC to the I/O source is limited to 3 meters (1)

11.


Connector.T1 ( and J2 ), parallel I/O

Pin numbers :

2,4, ••• , 16 are connected to the 8255 18,20, ••• ,32 n

34,36, ••• ,48 "

Jan Piecha

port 2 (5); pins 3 (6)* 1(4)

7,6, ••• , 0

All Odd-numbered pins are on the component side of the board and are

grounded. Pin 1 is the right most pin, seen from the computer side of

the board with the connectors at the top.

12.

The description of connectors J3 ( J4 ) and J5 is presented in Ta

bles 10 and 11 respectively. Pins 2 of J3 (.T4 ) and 1 of.T5 are the right most pins seen from the components side of the board, with connectors J1

and J2 at the top - compare assignment on layout mentioned in Pig.4.

Table 10 Connectors J3 ( and J4 ) assignment, serial I/O

Pin No. Assignment Pin No. Assignment

- - - -4 Transmitted Data 3 Trans.Sig.Ele.Timing 6 Received Data 5 Sec. Rec.Data 8 Request To Send 7 Rec.Sig.Ele.Timing

10 Clear To Send - -12 Data Set Ready - -14 GND 13 Data Terminal RDY 16 Reg. Line Sig.Dat. - -- - 17 Ring Indicator

- - - -• • • • • • • • • • • • - - - -

.. The port 3 and 6 can be rearanged using jumpers 52 and B3

•


Table 11 Connector J5 assignment, Keyboard/Display

Pin No. Assignment Pin No. Assignment

1 RLO 37 A2

3 RL1 39 A3

5 RL2 41 RESET IN

7 RL3 43 READY

9 RL4 45 -11 RL5 47 -13 RL6 49 -15 RL7 2 SHIFT

17 S10 4 CNTL

19 SL1 6 , TEST IN

21 SL2 8 BD

23 313 10 GND

25 BO 12 GND

27 B1 • •

29 B2 • • 31 B3 • •

33 AD

35 A1 50 GND

Connector P1 , Mollex

Power supplies : + 12 V, - 12 V and + 5 V DC voltage are connected \lith

the board using a connector, the Mollex type, as follows :

pin numbers - 1 2 3 4 voltage - +5V,+12V,-12V, GND

Pin number 1 of P1 is the right most seen from the components side of the

board, \lith the connector J1 and J2 at the top.

3.5 Jumpers configuration

The jumpers installed on the board allo\l the user to choose the most

convenient configuration of baud rates , interrupts, serial and parallel

13.


rio. The main set of jumper connections is presented in tables 12 to 18.

Other possibilities are also available.

Table 12 Jumpers B1

Numbers of Function

shorted pins

1 3 Selected EPR<J.I

4 6 2716

2 3 Selected EPROM

4 5 2732

Table 13 Jumpers B2

Numbers of Function

shorted pins

9 10

11 12 Parallel I/O port 3

· • • • • •

23 24

26(28) 25 Gate G1 (Go) of 8253 one of the wires

26(28) of PC of 8255-0

27 Interrupt Request of 8255-0

7 Count 55 for CLKo of 8253

14.


Table 14 Jumpers B3

Shorted pin Function numbers

31 32

33 34 Parallel I/O port 6 • • • • • •

45 46

29(47) Data Carry Detect on

J3 (J4) pins 16

30(48) Ring Indicator on

J3 (J4) pins 17

Table 15 Jumpers B4

Shorted pin Function numbers

49 $J Receiver Block (RxC) for 8251-0

53 54 'lransmitterClock ('!'xC) for 8251-0 51 50 External RxC for 8251-0 55 54 External '!'xC for 8251-0 57 56 Receiver Clock (RxC) for 8251-1 61 60 'lransmitterClock ('!'xC) for 8251-1 59 56 External RxC for 8251-1 63 60 External '!'xC for 8251-1 65 66 CLK1 from 1/2 System Clock 69 70 CLKa from 1/2 System Clock 67 66 Double Time Clock (from O2 to 8253) 71 70 8255-0 Count Clock for 8253

Single Board Computer Jan Pieoha

Table 16 Jumpers B5

Shorted pin Functioll

numbers

73 74 Request fo Send

75 76 Data Terminal Ready External from

77 78 Clear To, Send 8251-0

79 80 Data Set RDY

73 74 Request fo Send

75 76 Data Terminal Ready External from

77 78 Clear To Send 8251-1

79 80 Data Set RDY

89(91) 90 RxC and TxC for 8251-0 from

O2 (01) of Timer

Table 17 Jumpers B6

Pin No. Function

93 TRAP .,

95 7.5 8085 Interrupts

97 6.5

99 5.5 : 101 0

103 1

• • ~ 8259 Interrupts

• • • •

115 7

94 Extentlon of interrupt inputs 96 number

98 100 102

104

Single Board Computer Jan Piecba 17.

Table 18 Jumpers B7

Pin No. Interrupt Request Assignments

106 8255-0, Port C bit 3 IRQ 55";0/3 108 8253 output 01 IRQ 53/1 110 8253 output 00 IRQ 53/0 112 8279 IRQ IRQ 79 114 8255-0,Selected bit of IRQ 55/P

port C 116 8255-0, Port C bit ° IRQ 55-0/0 118 8255_1, Port C bit ° IRQ 55-1/0 120 8255-1, Port C bit 3 IRQ 55-1/3 117 8251-1, Transmitter RDY IRQ 51-1/T 119 8251-1, Receiver RDY IRQ 51-1/R 121 8251-0, Transmitter RDY IRQ 51-0/T 123 8251-0, Receiver ROY IRQ 51-0/R 125 External interrupt IRQ Extern.


4.Desoription of the debug monitor program

4.1 Capabilities of the program

A oomprehensive monitor program'was elaborated for this system to

faoilitate starting the system, program loading and exeoution.The soft

ware provides the oapability to monitor and oontrol multiple external

events and is useful for produoer and user in the testing prooesSof the

board. Monitor oommands inolude reading and writing hexadeoimal oharao

ters from and into paper carrier, and can be initiated and results dis

played by teletype writer or CRT terminal. The monitor uses seven bit

ASCII code without parity; addresses are stated in hexadecimal notation.

The monitor begins the dialogue by transmiiting and displaying sign-on

message " .... II.

The monitor program provides the following faoilities:

- display seleoted processor registers and areas of memory,

- modify contens of processors registers and memory,

- insert instruotions into memory,

- initiate execution of user program,

- execute single step instruotion,

- provide program brake oapability,

_ input hexadecimal file from paper type reader,

- output hexadecimal file to paper punch.

4.2 Monitor commands

Commands are entered as a list of numerio hexadecimal or alphabetic

parameters. The monitor program under discussion respects the same set

of commands as the Intel§ system iSBC 80/30 :

- D, display memory,

- G, program execute,

- N, single step,

- I, insert into memory,

- M, move memory,

- S, substitute memory,

- W, write hexadecimal file from memory to the paper tape punch on

the teletype writer,

- X, examine and modify CPU registers,

- R, read hexadecimal file from the paper tape reader.

A full description of those commands is presented in the manual [1) •


4.3 I/O devices ,drivers

The monitor allows the user to read and write from and to the console

device, and read or punch paper type on teletypewriter, for this purpose

the following commands are used [1J: - CI, console input,

- CO, console output,

- RI, reader input,

- PO, punch output.

4.4 System initialisation

Pushing RESET button or by power on, the monitor program begins exe

cuting on location OOOOR.

Next following initialisation steps are performed:

- the Timer 1 of the 8253 is set to MODE 2, and can be used for single

step function,

- the Timer 2 of the 8253 is set to MODE 3, as can be used as a clock

for the 8251 USART,

- the Programmable Interrupt Controller 8259 is set into the 48 byte jump table starting at 2FDOH RAM location. The interrupt priorities

are fixed with TRAP as a highest then 7.5, 6.5, 5.5 and 0 - 7 all

unmasked.

The USART clock is initialised for 9600 Baud. Two U charachters are used to

check up the baud rate. The first U character is used for checking the 960~

4800,2400 and 1200 baud rate. When a match is found then this baud rate is

set into the counter. The second II charaeter has to be entered for 600,

300, 150 and 110 baud rates. When the baud rate is determined the sign-on

messege " .. " will be displayed on the console.

The debug monitor program demands to use the configuration of jumpers

presented in Table 19.


Table 19 The jumpers configuration for debug monitor program

Jumpers Numbers of

assignment shorted pins

B 1 1-3, 4-6

B 2 25-26

B 4 49-50,53-54 56-57,60-61

B 5 73-77,81-85

75-79,83.$7

89-90

B 6, B 7 97 - 108

Comments

selected EPROM 2716

gate G1 of Timer on high level

clock fer trimimitt~ and receiver

of 8251 -0 and 8251 -1

reqest to send

data terminal ready

output O2 of 8253 on RxC and TxC

single step; one shot on output

01 of Timer to interrupt re

quest 7.5

4.5 The RAM storage and interrupts location

20.

The RAM space 2FB7H to 3000H is reserved for the monitor stack, inter

rupt jump table and register save area. The interrupts are serviced by a

jump table stored in RAM at locations:

Hexadecimal Address Interrupt

2 F D 0 TRAP

2 F D 4 7.5 2 F D 8 6.5 2 F D C 5.5 2 F EO 0

2 F E 4 1

2 F E 8 2


2 F E C

2 F F 0

2 F F 4

2 F F 8

2 F F C

3

4 5 6

7

Jan Piecha

4.6 Specifications of routines accessible for the user

21.

This monitor program can also be applied h1 the user as a source of typical routines. Very short descriptions of those routines are presented

belovo

LABEL: INUST

COMMENTS

ADDRESS: 0051H

Outputs to the USART the command word, the stack pointer is initialised. The

Interval Timer and Interrupt Controller are initialised. Inputs:None.

Outputs: None. Calls: Nothing. Destroys: A,H,L,SP. Full initialisation

of the USART - for 9600, 4800, 2400, 1200, 600, 300, 150 and 110 Baud.

Each of the command contains explenation about Inputs, Outputs and

used subroutines. When the information is not valid (like Input: None)

then this comment viII be suppressed.

LABEL: GETCM ADDRESS: 015CH Receives an input character from the user and attempts to locate this

character in the command character table.

Calls: GETCH, ECHO, ERROR. Destroys: A, B, C, H, L, F/Fi •

LABEL: DCMD ADDRESS: 01B3H

Implements G command to transfer CPU control from the system monitor to a user program. If one hexadecimal parameter is entered it is inter

preted as the entry point of the user program and a transfer to his

location is executed.

Calls: ERROR, GETHX, RSTTF. Destroys: A, B, C, D, E, H, L, F/F's

LABEL: ICMD ADDRESS: 0227H

Implements the Inserd Codd Into Memory (I) command.

Calls: ERROR, ECHO, GETCR, VALDL, VALDG, CNVBN, STHLF, GETNM, CROUT.

Destroys: A, B, C, D, E, H, L, FIr's.

LABEL: MCMD ADDRESS: 026DH Implements the Move Data In Memory (M) command.

Calls: GETCM, HILO, GETNM, Destroys: A,B,C,D,E,H,L,F/F's.


LABEL: NCMD Implements the Single Step (N) Command.

Calls: CROUT. Destroys: A

LABEL: RCMD Implements the Read Hexadecimal Tape (R) command

LABEL: SCMD

Jan Piecha

ADDRESS: 028DH

ADDRESS: 0295H

ADDRESS: 0200B

Implements the Substitute Into Memory (S) command.

Calls: GETHX, GETCM, NMOUT, ECHO. Destroys: A,B,C,D,E,H,L,F/F's.

LABEL: WCMD ADDRESS: 031 DH Implements the Write Hexadecimal Tape (W) command.

Calls: GETNM, LEAD, PO, PBYTE, PADR, PEOL, PEOF. Destroys: A,B,C,D,E,

H,L,F/F's.

LABEL: XCMD ADDRESS: 0373H Implements Examine Registers and Change (X) command.

Calls: GETCR, ECHO, REeDS, GETCM, ERROR,RGADR, NMOUT, CROUT, GETHX.

Destroys: A,B,C,D,E,L,F/F's.

LABEL: INT 85 ADRESS: 03E8H Handles interrupts caused by active levels on TRAP, RST 6.5, RST 5.5

if they are not handled by the user.

Calls: RmSV, RIDDS, NXTIN. Destroys: A, F/F' s

LABEL: STEPIN Outputs data after single step time iterrupt.

Calls: R]X;SV, RmDS,NXTIN • Destroys: A,F/F's

LABEL: ADRD

ADDRESS: 0464H

ADDRESS: 049EH

Outputs to the console the address contained in the H,L register.

Interrupts: H,L - address to be displayed. Calls: NMOUT. Destroys: A

LABEL: ADROUT ADDRESS: 04A7B Outputs the user the contents of the PC to the console after an RST 1

instruction.

Calls: ECHO, ADRD. Destroys: A,B,C,D,E,H,L,F/F's

22.


LABEL: BREAK ADDRES: 04B5H Is used to sense an escape character from the user .If the pending

character is not the escape then the failure return is taken.

Outputs: CARRY, -1 or - O. Calls: Nothing.

LABEL: BYTE ADDRESS: 04CAH Reads two ASCII characters from the teletypewriter and converts these

to the hexadecimal character •

Inputs: D - current value of check sum. Outputs: A - hexadecimal cha

racter. Calls: RICH, CHVBN • Destroys: A, B, C, D, F/F'.s

LABEL: CI ADDRESS: 04E5H

Waits until a character has been entered at the console and then

returns the character • This routine is called via a jump table in

RAM - by the user.

Outputs: Character from console via A. Destroys: A, F/F's

LABEL: CNVBN ADDRESS: 04F1 H

Converts the ASCII representation of a hex character into its corres

ponding b!nary value.

Inputs: C - ASCII characters 0 to 9 or A to F. Outputs: via A to F Hex.

Calls: nothing. Destroys: A, F/F's •

LABEL: PO (=CO) ADDRESS: 04FAH

Punches the character supplied in the C register to the user teletype

writer. Calls: CO

LABEL: CO ADDRESS: 04FAH

Waits until the console is ready to accept a character and then sends

the input argument to the console.

Inputs: Character for console C register. Outputs: Character to console via G • Galls: nothing

LABEL: DELAY ADDRESS: 050DH

Provides 1 millisecond time delay.

Destroys: F/F's

LABEL: ECHO ADDRESS: 0518H

Takes a single character as input and sends that character to the user

terminal , via the monitor.

23.


Inputs: C - character to echo to terminal • Output: C - character echoed

to terminal. Calls: CO • Destroys: A, B, F/F's •

LABEL: ERROR ADDRESS: 0536H

Prints the error character.

Calls: ECHO, CROUT, GETCM .Destroys: A, B, c, F/F's

LABEL: NMOUT ADDRESS: 05E5H

24.

Converts the 8 bit integer in the A register into two ASCII characters

Inputs: A - 8 bit integer. Calls: ECHO, PRVAL. Destroys: A, B, C, F/F's

LABEL: PADR ADDRESS: 061EH

Punches on the teletypewriter the address contained in the H,L registers

Iputs : H,L address to be punched. Calls: PBYTE. Destroys: A

LABEL: PBYTE ADDRESS: 0627H

Converts the hexadecimal value in the register into two ASCII characters

and punches these characters on paper tspe.

Inputs: A - character to be punched, B - current value of checksum. Out

puts: D - update value of checksum. Calls: PRVAL, PO. Destroys: A, F/F's

LABEL: PRVAL ADDRESS: 0667H

Converts a number of in range 0 to F hexadecimal to the corresponding

ASCII character, 0 to 9 and A to F •

Inputs: A - integer, range 0 to F • Outputs A - ASCII character

LEBEL: RI ADDRESS: 06D2H

Reads a character from the TTY tape reader

Outputs: A - zero, CARRY - 1 if and of file. Calls: DELAY. Destroys: A, F/ts

LABEL: RSTTF ADDRESS: 0712H

Restores all CPU registers , Flip-Flops, Stack pointer and Program coun

ter from their location in memory.

Destroys: A,B,C,D,E,H,L,F/F's.


5. Conclusion

The testing process mentioned in chapter 1 was limited to the problem

of finding the lines (address, data, control) where drivers should be pla

ced. The drivers were only placed where it was necessery rorusing the full

set of components. The over~oaded lines were a cause of time delays in the

commununication process between the processor, memory and peripherals. In

the testing procedures a special short programs and debug monitor program

described in chapter 4 were used. As a result of testing process, time de

lays and project faults were eliminated. The computer was built for indus

trial control purpose and will be used for this goal by the Mechanical De

partment of T.H. Eindhoven. An external memory wasn't included, what was

not necessery in this type of application.

-------~ --- ---


6. Ref'erences

1. Intel Corporation. System 80/30 Microcomputer User's Guide .Order

number 9800710A

2. Intel Corporation. Peripheral Design Handbook. Intel Corp.,1980

3. Intel Corporation. MSC 85 User's Manual. Intel Corp., 1980

4. Intel Corporation. Components Data Catalog. Intel Corp.,1980

5. Appendix. A single board computer debug monitor program-listing.

Internal materials of' Digital Systems Division of' Electrical Engi

neering Dpt. T.H. Eindhoven, 1981

26.

IC SOC

,----,.-V--V--lr-

KETS

rO~ ROM 2716 or27~Z RAM 8185 "', "'.

TRAP R$T 7.:$

8 RST 6.e 'RSoT 5.15

INTR

8085 8282 LATCH

2 8 CPU 1

C5 ALE 8 LOGIC f-

RD WR

R/W DATA BUS 82B6 r--- 2 DRIVER DRIVE LOG. BUS DRIVER 7

I I ~

C5 DATA 1\/W CS DATA 1\/101 C5 DATA 11./101 CS DATA 1\/W

8255-0 8255-1 82~-O RxD T",D lI .. e/A.e

825H bli TiD RJ<CIT.J:

f-<>INT /;--oINT 8 8 a 8 , 8 8

y.,T".'A. INT !'-o'NT !'-oINT 4.T.R INT

L.R<RINT L...,..bllNT

I J1 I I J2 J r ;]3 I . I "

A'DORE&$ BUS. A1S~ A.

AOD'Re!>S SUfi A 1 -:- Ao

r- TRAP ~ 'EXT. INTER. RST 7.' rr-INTI!:R.~1,T)I,R ,Rll'R

'RST 6.' ~ INTeA..I),

FIST ts.5 ~ INTER·!Sl

I-- I>lT,0..78 INTER1WPT

~ MATRIX

e /

INT

B

-

PyW CO NTROL BUS

NTRDL DATA C5 CO

I C5 DATA 1\/W CS DATA R/fJ CS DATA R/W

8253 INT" 8259 INn: 8279 CTR2 GTRO GTR. IRQ

I

~ ~ INT INT INT

DRIVE~ JDRIVER

I J5 ]

FIG.1 SCHEMATIC BLOCK DIAGRAM

f--ltaSBT OUT 'ZC4 I--INT~ OZA2

~+-INT" ~ZA&

7408 r----------I

>++-_-,i'--rl' a I ..&.lJ J I

TeST POINTS

L-r-~~-4-4-+------------------------~~-t-t~~+-+-t-----------~TAD7 L-t-t-r-~~------------------------+-r+-'-+-t-t~~~-----------oTAD. L-r-~~-T------------------------t-rt-+-t-t-r~~+------------oTAD5 L;~-+-+---------------+-~-t-+~+-+-t-r--------oTA~ .' ......... 1: U~ ,..til )/-S=----r----il- AD 2283

'-I '-iL-iT-11---=----------=--=--------=-----------------tl--f+...;1---t+--11--f+_+~-11-++--1_-----=----------=-----o-oTA D. L-r-____________ _+~+_+_~_+_+~_f_---------~TADI

• 'V 8 I I I , ' I ..., i

Uk ~ j I .w' A47,

.IV '- -1.tiN'D-41W.;; -=-". .SV

6

. TAD • ~-------------------_+~+_+_~_+_+~~---------oTADo

WR 2Z113 ~----------CLK OUT UC4

r ----rs----l : I i,l, i , ~ 0 Qpll't-...iL--------<"CLKOUT nce : I~LS74 : I 1.,v,8 I liND , ...... c 4~ I7:l-

~ __ ~t---k~'v +BV

5 4 2

FIG.2

CPU- SHEET1

1

o

c

B

A

1ZOIt 1ZD4

1ZOIt

6 5

1ZD2 AD, 1ZD2 AD.

ADa • AOt . ~g.

AD~ 1ZD2. AD.

L- Ao 01----....... ----- CS 8201-0 )lC~ r

A, 1 CS 8201 -1 3ZC't L-----lA. 2 CS 8200 - 0 ~ZC6

820~-1 ~ CS 510'-1 ~ZA6 L-----dE, ~ os 82'9 'ZA8

Lt===:jE& A 16 0 cs 82!)~ !ZB8

Es' CS 1279 OZII6 7~---~~~~~~

6 T81-0 III-<\) Ilt ~ 79

&'1-1 5$-, " * OPTIONA L

4 3 2.

D

c

B

-61--

A

FIG.2

"~"ORY - SH~e:T a.

1

IZA~ ~1

~

1ZA2 D. D. D. D. D.

1W 0. n~RD.::;!~~~t++4=========-______________ ~~ ______ ___ 2ZB~ WR

+%%C

..

.I.. '1 • ..,

D

c

B

A

F16.2

6ERIAL I/O. TlM.~ • IlITEllRUPT COHT1tOLUR

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COlIN I

~ . III

0 II 1;:7 A 4 .. ~. T

I~: " 1..., I~'

~! ~&

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A13 l.. • • .:E~T ,..--! ~;,

D. I:' 0

~ ~ "~

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o • 0

8255-1 R & T 4

8 A14 c • 9 I~:

~ 7

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0' R

2%"'2- T

I GND v""~ ~ HI,

5V

1.&

Al6

Al?

~7-t'COUNT

~,= A2B ;; ;; A29

, • .sk~., A30

A 211

A~2

A~~

~!' ~ .. ' A~4

.. ' A~5

~.,

A?>6

A37

-t Prlilloc«.n PIN"7eND

t "" " Pi

RT1

l~o.OII-ol' UM Ii IS-O/O 'UA.

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BIT ()

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I BIT7

BITO

I I 8 .. 'ZC5 RQS5'/P 3ZAIt

""OZC5

PORT2

I BIT7

BIT 0

I PORT

I BIT 7

BITO

I PORT I

81T 7

BITO

I PORT

I 81T 7

DATA CA •. Rei IRQ Sf-otIS ,ZAlt IRQ "-410 ,2.44 ~TA C'-'Ro. 3ZA'"

'RING INDfCAT ~ZC1

RING INDICitT. nt',,1

5

ALL 0 00 PIN NUMBERS

o

c

B

A

FIG.Z

PARALLEL I/O ~"EET"

4 . I~ ~~!

I~, 1% _v

1$ ~: 1< 15

_J! l>t Rii I. "

D1 D4

., 1

11 I;' "'7

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D,

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CUt fJI &. f7

NJ t.. w. A1 I.

t.I At •• ,---' eo AS

V" ~.

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6 5

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~ ItlO 1'6 11-

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~

4 i

& Re7 I"r-• It ~LO t--& 14 1 t--5 I- ~ 2.

9 7407 LI

i~ KEVl:>OARD/ ..

Alo0 ~- IDI&PLAY .. 14 t 2. - (E.t."~ .. l !>OClr<J.) 4 &

s 7MJl ~' f! 2.

a 6H~41 v •. ~ ~ t::I _.IN Ir.I ~ ~15V EI .ltOAl>!' -fi-

P.."I SHIFT 74(11 ,.-- CNTL t--

• ,'i IV TaT IN t--:lI ~D

Mt. I'

L..L.C)-' J6

~£VE.ftN' 5Kc.LUDINI TESTI~

1.-4-6-8 .,. Vc!'.5V PINS

~()-< '15-47-'t9 RES.'&.TI

--'" , ~ 0-. • RaAt1<

~

4 2

FIS.2

KEYBOIIRD/DISl'LAY - SHEET 5

1

D

c

B

A

P5 1 a , 7 9 ff

45

iP

" Ii I!!I • i -..... -I

READY 4Q A52 ~+5V

TE&T IN REUTIIil M---' _),RL'Nrr---.... ,..----,

161 8 2Y. Vee

~'. ~'. f ~. f f' ~. f 10 2.Y •. A50

74156

~ A r-f! 8 1G ~

Ka ~K' ~. ~~ [~ ,;Ko 't ... ~Ke 1 e 26 ~

~ 2C GNO J Kl

~

J. J~ 111'18 , 18 2G GND 0:' 2

1

• A49 • , , 3 . '::'":: 74159 • , 7404 • 7

9 e e 1<0

~~ 8 " <0

7404 :::; .. 4'0

J. C .. , 4' 20

0 •• ~ ~ 22., ... Vee

24L +5 +5V

Vee i\ '" L

" L r L

I' L I.

Tl"\. I.

'" BC160

+5V

.

22 ohm

• A51 '" ~1! .. 74122 JV 74279 2.2k

-~ ~.'T c':i 'oR ,I n.. .~~ '.. ~ !. ., ..tI '''r:r- ,,,'u " ~.

+5V +SV

1.2k .

g~ B I,

B 120 ohm BC160

. . NAN 7 1A

I,

~ B H FED C

'IT

FIG.~

KEYBOARD/DISPLAY BOARD

A1 2716/2732.

J1 02

§§§~""'I B~B"BGGBBBBGB [ AO.oS , [ A~ 8255 " [ '~" ':" "

A2 2716/2732

§BBB~B§i ~§~ [Ai"'" 'E] § II

[ A17 8279 I II

J5 04

FIG.4

NICROCOMPUT~R LAYOUT

EINDHOVEN UNIVERSITY OF TECHNOLOGY THE NETHERLANDS DEPARTMENT OF ELECTRICAL ENGINEERING

Reports:

105) Videc, M. F. STRALINGSVERSCHIJNSELEN IN PLASMA'S EN BEWEGENDE MEDIA: Een geometrischoptische en een golfzonebenadering. TH-Report 80-E-I05. 1980. ISBN 90-6144-105-6

106) Hajdasinski, A.K. LINEAR MULTIVARIABLE SYSTEMS: Preliminary problems in mathematical description, modelling and identification. TH-Report 80-E-I06. 1980. ISBN 90-6144-106-4

107) Heuvel, W.M.C. van den CURRENT CHOPPING IN SF6' TH-Report BO-E-107. 19BO. ISBN 90-6144-107-2

lOB) Etten, W.C. van and T.M. Lammers TRANSMISSION OF FM-MODULATED AUDIOSIGNALS IN THE B7.5 - 108 MHz BROADCAST BAND OVER A FIBER OPTIC SYSTEM. TH-Report BO-E-10B. 19BO. ISBN 90-6144-10B-0

109) Krause, J.C. SHORT-CURRENT LIMITERS: Literature survey 1973-1979. TH-Report 80-E-109. 19BO. ISBN 90-6144-109-9

110) Matacz, J.S. UNTERSUCHUNGEN AN GYRATORFILTERSCHALTUNGEN. TH-Report BO-E-110. 1980. ISBN 90-6144-110-2

111) Otten, R.H.J.M. STRUCTURED LAYOUT DESIGN. TH-Report BO-E-111. 19BO. ISBN 90-6144-111-0 (in preparation)

112) Worm, S.C.J. OPTIMIZATION OF SOME APERTURE ANTENNA PERFORMANCE INDICES WITH AND WITHOUT PATTERN CONSTRAINTS. TH-Report BO-E-112. 19BO. ISBN 90-6144-112-9

113) Theeuwen, J.F.M. en J.A.G. Jess EEN INTERACTIEF FUNCTIONEEL ONTWERPSYSTEEM VOOR ELEKTRONISCHE SCHAKELINGEN. TH-Report BO-E-113. 19BO. ISBN 90-6144-113-7

114) Lammers, T.M. en J.L. Manders EEN DIGITAAL AUDIO-DISTRIBUTIESYSTEEM VOOR 31 STEREOKANALEN VIA GLASVEZEL. TH-Report BO-E-114. 19BO. ISBN 90-6144-114-5

115) Vinck, A.J., A.C.M. Oerlemans and T.G.J.A. Martens TWO APPLICATIONS OF A CLASS OF CONVOLUTIONAL CODES WITH REDUCED DECODER COMPLEXITY. TH-Report 80-E-115. 1980. ISBN 90-6144-115-3

EINDHOVEN UNIVERSITY OF TECHNOLOGY THE NETHERLANDS DEPARTMENT OF ELECTRICAL ENGINEERING

Reports: EUT Reports are a continuation of TH-Reports.

116) Versnel, W.

THE CIRCULAR HALL PLATE: Approximation of the geometrical correction factor for small contacts. TH-Report 81-E-116. 1981. ISBN 90-6144-116-1

117) Fabian, K. DESIGN AND IMPLEMENTATION OF A CENTRAL INSTRUCTION PROCESSOR WITH A MULTIMASTER BUS INTERFACE. TH-Report 81-E-117. 1981. ISBN 90-6144-117-X

118) Wang Yen Ping ENCODING MOVING PICTURE BY USING ADAPTIVE STRAIGHT LINE APPROXIMATION. EUT ·Report 81-E-118. 1981. ISBN 90-6144-118-8

119) Heijnen, C.J.H., H.A. Jansen, J.F.G.J. Olijslagers and W. Versnel FABRICATION OF PLANAR SEMICONDUCTOR DIODES, AN EDUCATIONAL LABORATORY EXPERIMENT. EUT Report 81-E-l 19. 1981. ISBN 90-6144-119-6.

120) Piecha, J. DESCRIPTION AND IMPLEMENTATION OF A SINGLE BOARD COMPUTER FOR INDUSTRIAL CONTROL. EUT Report 81-E-120. 1981. ISBN 90-6144-120-X

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