Autors de la pràctica adaptada al mètode científic: Josep Jordana, Francesc J. Sànchez

Desenvolupament de l'experiment:

Designing VHDL-based IP (intellectual property) combinational modules using industry EDA (Electronic Design Automation) tools

Context of the subject: Bachelor in Telematics Engineering and Telecommunications Systems, term 2A. (EPSC)

Time devoted to this exercise: 2 weeks (10 h of study time)

Weeks during the term that the exercise will be done: W4 – W5

Main objectives of this practice: Designing programmable digital systems using modern PLD’s chips and software tools.

Methodology: Cooperative work (groups of 3 persons)

Material and information sources: Subject’s web of resources (http://epsc.upc.edu/projectes/ed/), books form the list of references, tutorials, web seminars and other learning materials form the hardware and software vendors.

Escenificació

We are interested in designing an Arithmetic Logic Unit (ALU), which as shown in Fig. 1, is one of the main components of the datapath block of any microprocessor. Essentially, the datapath consist of the combinational circuit ALU combined with data registers to store operands and results and also to generate some operation status signals.

The main idea is to design a top-down structural architecture for the ALU entity based on a network of elemental blocks and signals, using modern industry-standard tools for all phases in the design flow (VHDL design entry, simulation, implementation and prototyping using training boards).

The final circuit will be implemented into a complex programmable logic device (CPLD) or a field programmable gate array (FPGA).

Fig. 1 Internal structure of a microprocessor1

Considering the entity to be designed and its specifications in Fig. 2, the objective of this exercise is to invent a block diagram for the ALU, based on a top down and hierarchical design. Vector S(2..0) has to be used to select the operation to be performed. Indication flags: Z stands for zero result; OV is signed overflow detection, and C is a carry overflow in unsigned operations. Check your ALU diagram testing some operation examples.

ALU

A(7..0)

B(7..0)

R(7..0)

S(2..0)

Z

C

OV

S(2..0) code  Operation  Flags affected 

000 R = A + B (signed, unsigned) Z, C, OV

001 R = A − B (signed) Z, OV

010 R = A(3..0) × B(3..0) (unsigned)

Z

011 R = shift left A with carry Z, C

100 R = A xor B Z

101 R = A or B Z

110 R = A and B Z

111 R = shift right B Z

Fig. 2 ALU symbol and specifications

1 Enoch O. Hwang, E. O., Digital Logic and Microprocessor Design with VHDL, Thomson, 2006,

http://faculty.lasierra.edu/~ehwang/digitaldesign/

a. Treball pre-laboratori One of the main characteristics of the proposed design is that it has to be carefully planned (structured) due the large number of blocks involved. Essentially, the project will consist in many VHDL source files to define components to be afterwards instantiated following a hierarchical top-down design approach.

P1. Search information about the main characteristics and utility of an arithmetic logic

unit (ALU) block. Summarise them through a concept map. P2. Choose and install one of these EDA environments.

1 ‐ Development environment: and synthesis: Quartus II web edition, Altera;  

‐ VHDL Simulator: ModelSim student edition,  Mentor Graphics;  

‐ Training boards: Altera University program UP2/UP3  ‐ Target programmable devices: MAX7000, FLEX10k, or 

Cyclone II EP2C35F672C6 FPGA  

2 ‐ Development environment: and synthesis: ispLEVER Starter, Lattice Semiconductor, and Synplify Synopsys  

‐ VHDL Simulator: Active HDL, ALDEC  ‐ Training boards: MachXO USB Starter Evaluation Board  ‐ Target programmable devices: LCMXO256C‐4T100C 

MachXO FPGA 

Follow instructions in Unit 1.11 (see the web) to install either Altera (1) or Lattice (2) software tools environments. Check the software by running the proposed sample design uploaded in the web. Print the RTL view as a picture and explain its main parts. Follow instructions in Unit 1.13 (see the web) to install either ModelSim (1) or ActiveHDL (2). Check the simulation software running the functional simulation of a simple sample example to get used and learn about the tool’s simulation workbench. P3. Planning the ALU. There are several circuits to be designed with different levels of complexity. Thus, start with the top and go into every single component trying to design it structurally as a network of simpler components interconnected by signals.

Be neat and organised. Firstly, draw by hand a sketch or a logic schematic to represent the block been designed for documentation and clarification purposes when discussing the architectures with your team mates. The idea is very simple: never write VHDL code without having a graphical representation of the circuit been designed. Remember

to name all the circuit or schematic signals and ports before attempting to code in VHDL. Once you already have a circuit structure, start coding it from bottom to top implementing useful blocks or components with the aim to be used later on in new and more complex designs.

Informe Pre‐ laboratori 

Mesurar/Adquirir  Apartat  de l’experiment                                                  Check if the installation of the software environment works correctly by means of running sample examples. 

P2  Prelab 

     Experimentar   Run software tools and browse the web of EDA software vendors 

P2  Prelab 

     Modelitzar   

P3  Prelab Define circuit structures by hand    

     Projectar/Predir   

P1, P3  Prelab Sketch or logic diagram to represent the entity to be designed.          DDecidir   Choose from different structures which ones have to be included into the final ALU implementation.  

P3  Prelab 

     

b. Treball al laboratori

In order to validate every one of the ALU subsystems designed using VHDL, the code has to be simulated. To do this job, there are several options depending on the tools. For instance, Altera Quartus II (or Xilinx ISE) has their own embedded simulator tools, but ispLEVER Starter do not have it. Therefore, to make your design more compatible and vendor independent, you may decide not to use the integrated simulators and instead install independent professional simulation tools, like Mentor Graphics ModelSim or Aldec Active HDL, which both have student editions.

L1. Start a ModelSim/ActiveHDL VHDL-project for every single block in your ALU design, starting with the smaller ones and going from bottom to top. Simulate every project before attempting to use them as elemental component for bigger entities. Document the simulation process, from the input vector generation (do files) to the final timing diagrams demonstrating that input and output activity corresponds with what is specified.

L2. Once the code has been functionally verified using simulator tools, start the design flow for a Quartus-II /Lattice ispLEVER in order to implement the ALU design into a CPLD or a FPGA chip:

(1) Design entry (the already verified VHDL source files)

(2) Pin assignment according to the training board in which the target chip is placed.

(3) Project compilation and logic circuit synthesis and routing.

(4) Visualisation and verification of the RTL netlist diagram.

(5) Timing analysis. Determining the maximum frequency of operation for the implemented circuit

(6) Downloading the programmable device configuration file onto the training board to check the prototype

In order to learn the whole design process you do not need to have the ALU design completed, because a final prototype can be also generated even for a single ALU section, for example for the unsigned adder. Thus, start with a very simple design and complicate it step by step while you are getting used to the tools and you are gaining confidence in the results.

Document the implementation process, from the VHDL source files to the final step of prototyping, demonstrating that your circuit behaves accordingly to the initial specifications.

c. Treball post-laboratori

Writing quality reports and preparing oral presentations.

PL1. Using the documents generated through the pre and laboratory sections do an electronic document to report very carefully all your design steps paying attention in the text, figures, tables and references. Using materials from the written report, construct a poster or a ten minutes oral presentation based on Power Point slides. Use the document template and take into account the recommendations which can be found in the e-portfolio and problems sections of the course web pages2. Remember to indicate the main conclusions of your design and reflect about the whole experience of working in cooperative groups for designing real hardware using industry-standard tools. Explain what parts of your design have worked correctly and try to predict alternative designs that could work properly, taking into account the experience that you have obtained. PL2. Would you recommend the use of your designed ALU to be used as an example or a learning material for future students of the same subject?

Informe de  laboratori  i post‐laboratori:  (útil  tant per el professorat quan planifica o dissenya  la 

2 http://epsc.upc.edu/projectes/ed/E1/prob/E1problems.html,

http://epsc.upc.edu/projectes/ed/E1/eportfolio/E1portfolio.html

activitat al  laboratori  com per  l’avaluació, amb  la  rubrica del nivell  competència, així  com per a 

l’estudiantat com a autoavaluació)  

Mesurar/Adquirir  Apartat  de l’experiment  Momento Characterise the circuit behaviour through simulations using signal stimulus and timing diagrams  

L1  LAB 

Characterise the circuit realisation prototyping real hardware and using laboratory instruments (maximum frequency of operation, voltage levels, power dissipation, etc.)   

L2  LAB 

     Experimentar   Interacting with the software tools through all the design flow  

L1, L2  LAB 

Operating laboratory equipment, training boards and electronic instrumentation  

L2  LAB 

     Modelitzar   

L1  LAB  

Designing combinational circuits using VHDL language 

        Projectar/Predir   

L1,L2  LAB Plan a complex circuit structuring a top‐down hierarchical design based on simple components and networks.  

   

Obtain conclusions about the design (ALU) 

PL1  POST 

     Decidir   Which is the best structure to implement a circuit considering advantages and drawbacks of each circuit realization? 

L1,L2  POST 

Would the designed ALU be useful to future students as a learning material? 

PL2  POST