design and analysis of svpwm scheme for two and three...
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ISSN 2348–2370
Vol.08,Issue.07,
July-2016,
Pages:1385-1391
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Design and Analysis of SVPWM Scheme for Two and Three Level Inverters M. HARI
1, RAMESH R HALAKURKI
2
1PG Scholar, Dept of EEE, SITAMS College, Chitoor, AP, India, E-mail: [email protected].
2Professor & HOD, Dept of EEE, SITAMS College, Chitoor, AP, India, E-mail: [email protected].
Abstract: Multilevel Inverters are the most popular Inverters
in the medium-voltage high-power range. Inside this family of
Inverters, the three-level Diode clamped inverter (DCMLI)
has its own importance. The main control methods associated
with this Inverter are the carrier-based PWM with added DC
components (SPWM) and the space vector PWM (SVPWM or
SVM). The main advantage added to DCMLI is when it‟s
neutral point is clamped so that it made as Neutral Point
Clamped Converters (NPC). The features of NPC are good
output voltage spectrum, half of the voltage to be switched.
Both control methods efficiently manage the two
characteristics. This paper presents the methodology to
produce switching patterns of SVM for 2-level and 3-level
NPC inverter and the SPWM technique is compared with
SVM in both the levels by using MATLAB&SIMULINK
software. THD was analyzed through FFT (Fast Fourier
Transformation) analysis for the 50Hz fundamental frequency
and 3 KHZ switching frequency. Simulation results were
shown and compared in the view of THD for both the
techniques. The result shows that the SVPWM is better for
two level and three level NPC inverter in THD point of view.
Keywords: DCMLI, FFT, NPC, SPWM, SVM, THD, VSI.
I. INTRODUCTION
Multilevel inverters are widely used in high-power high-
voltage applications due to their advantageous performance
compared to two-level inverters, including reduced voltage
stress on the power devices, lower harmonics, lower
instantaneous rate of voltage change (dv/dt), and lower
common mode voltage[1].There are four types of MLIs are
present namely, Diode Clamped, Flying Capacitor, Cascaded
[2] and Modular multilevel Inverters. Fig.1 represent a block
diagram for a MLI. Neutral point converter which was
proposed by Nabae, Takahashi and Akagi in 1981. Some
features of the NPC inverter are better dc voltage utilization,
good output voltage spectrum and less output voltage transient
etc. Comparing with two level inverter, 3-level NPC inverters
have more economic advantages. Few more features of NPC
inverters are all phases share a common dc bus voltage which
minimizes capacitance requirements of the converter,
converter efficiency is high if it operates at fundamental
switching frequency and simple in control. So to switch over
the various switches at the high switching frequency range in
NPC inverter we have two most popular modulation schemes
namely PWM and SVPWM are available. In this paper we
were implemented the SVM scheme for two level and three
level NPC inverters. The simulation results of SVM
scheme employed circuit are compared with the SPWM
scheme employed circuit in THD perspective. And it
shows that the SVM is better compared to the SPWM
scheme employed circuit in terms of THD.
Fig. 1. Block diagram of a Multilevel inverter.
II. SVPWM SCHEME FOR A SIMPLE TWO LEVEL
INVERTER
In the SVM method a-b-c to d-q transformation is done
by Clarke‟s transformation which shown below; to produce
space vectors in which both magnitude and phase of the d-
q signals are used. The sector in the Space Vector diagram
is selected based on the value of magnitude and angle in
the space plane. There will be Active and zero vectors
present in the SVM method. The Active Vectors alter the
Phase angle of the output AC and Zero vectors are used to
make the magnitude variation of the output AC sinusoidal.
The duty cycles being calculated based on volt-time
balance and the space vectors are acted in corresponds with
the duty cycles by which the switching sequence is
generated. The various equations used in the SVM for
simple 2-level NPC Inverter is given below.
(1)
M. HARI, RAMESH R HALAKURKI
International Journal of Advanced Technology and Innovative Research
Volume.08, IssueNo.07, July-2016, Pages: 1385-1391
Which are the three phase AC voltage; that is used to generate
switching patterns. The Clarke‟s Transformation used to
transform from a-b-c to d-q is given below [3]:
(2)
The local angle:
And magnitude:
The duty cycles are based on the timing values below:
(3)
Where,T1 , T2 , TZ , Tsare the timings that are the times till which
each space vector i.e; active V1,V2, .which will vary according
to the sector and zero vectors V0,V7, .which are „000‟ and
„111‟ acting respectively and sampling time,Vdc is the dc
voltage to which the invertor is operated at, and„k‟ is the
sector number as shown in Fig.2.
Fig.2. Simple 2-level inverter switching and the State
Vectors.
The space vector diagram shown in Fig. 3 below in which 6-
sectors, each divided of 60 degree correspondingly.
Fig. 3. Space vector diagram for 2-level inverter.
III. PRINCIPLE OF SVPWM SCHEME FOR THREE
LEVEL DCMLI
Three level SVM Space vector diagram shown[5] in Fig4.
A. Timing Calculations
Similar to the two-level SV-PWM, in a three-level
inverter, the reference voltage vector is generated with a
combination of the available switching states of that sector.
From Fig. 5, it can be seen that when the reference voltage
vector is placed in subsector three, it can be represented by
the available three voltage vectors POO/ONN (V1), PNN
(V3), and PON (V2).
Fig.4. Sectors and their Regions for Three-level
Inverter.
TABLE I: Different Switching States [8]
TABLE II: Differents Witching Combinations [8]
Hence,Vref can be represented as (by means of Volt-time
balance) [5],[6],[8].
(4)
(5)
Design and Analysis of SVPWM Scheme for Two and Three Level Inverters
International Journal of Advanced Technology and Innovative Research
Volume.08, IssueNo.07, July-2016, Pages: 1385-1391
In Table-III „m‟ is the modulation index,
(6)
Fig.5. First sextant of three-level space vector.
The timings in Table-III are same in all sectors according to
the region in which the reference vector is present as shown in
Fig. 6 to Fig. 13.
TABLE III: Switching States for Three-Level Inverter in
Sector 1[9]
Fig.6. Switching Sequence for Three-level SVPWM
Inverter.
Fig. 7 Simulink block of SPWM scheme for Three level
NPC Inverter.
Fig. 8. Simulink block diagram of SVM scheme to
produce gate signals for three level NPC inverter.
Fig. 9. Sector selector and local theta calculator.
M. HARI, RAMESH R HALAKURKI
International Journal of Advanced Technology and Innovative Research
Volume.08, IssueNo.07, July-2016, Pages: 1385-1391
Fig.10. Triangle selector in each sector.
Fig.11. Vector selector in Region-1in first sector.
Fig.12. Gate signal selector.
Fig.13. Three level IGBT based NPC inverter to which
the SVM scheme is employed.
IV. SIMULATION RESULTS
Simulation was implemented in MATLAB/Simulink for
a three-phase two and three-level NPC inverters by
employing both the SPWM and SVM [9]-[10]. The THD
was calculated for each voltage waveform in both the
schemes. They were compared in terms of THD and its
performance. In the simulation, the switching frequency is
3 KHz (fundamental frequency is 50 Hz), the modulation
index is 0.85, and the duty cycles of the first and the last
switching states in each switching sequence are equal for
SVM. The simulation results were shown in Fig. 14 to Fig.
29 for line voltage and phase voltage for Two level
inverter, Three level NPC inverter with SPWM and SVM
schemes.
Fig.14 FFT analysis window for line voltage in a simple
two level NPC inverter with SPWM scheme.
Fig.15 FFT analysis at the 50Hz of fundamental
frequency for the line voltage and calculation of THD
for Two level NPC inverter with SPWM scheme.
Design and Analysis of SVPWM Scheme for Two and Three Level Inverters
International Journal of Advanced Technology and Innovative Research
Volume.08, IssueNo.07, July-2016, Pages: 1385-1391
Fig16. FFT analysis window for phase voltage in a simple
two level NPC inverter with SPWM scheme.
Fig17. FFT analysis at the 50Hz of fundamental frequency
for the phase voltage and calculation of THD for Two level
NPC inverter with SPWM scheme.
Fig18.FFT analysis window for line voltage in a three level
NPC inverter with SPWM scheme.
Fig19. FFT analysis at the 50Hz of fundamental frequency
for the line voltage and calculation of THD for Three level
NPC inverter with SPWM scheme.
Fig20. FFT analysis window for phase voltage in a three
level NPC inverter with SPWM scheme.
Fig21. FFT analysis at the 50Hz of fundamental
frequency for the phase voltage and calculation of THD
for Three level NPC inverter with SPWM scheme.
Fig22. FFT analysis window for line voltage in a simple
two level NPC inverter with SVM scheme.
Fig.23 FFT analysis at the 50Hz of fundamental
frequency for the line voltage and calculation of THD
for Two level NPC inverter with SVM scheme.
M. HARI, RAMESH R HALAKURKI
International Journal of Advanced Technology and Innovative Research
Volume.08, IssueNo.07, July-2016, Pages: 1385-1391
Fig.24 FFT analysis window for phase voltage in a simple
two level NPC inverter with SVM scheme.
Fig. 25 FFT analysis at the 50Hz of fundamental
frequency for the phase voltage and calculation of THD
for Two level NPC inverter with SVM scheme.
Fig.26 FFT analysis window for line voltage in three level
NPC inverter with SVM scheme.
Fig.27 FFT analysis at the 50Hz of fundamental frequency
for the line voltage and calculation of THD in Three level
NPC inverter with SVM scheme.
Fig.28 FFT analysis window for phase voltage in a
simple three level NPC inverter with SVM scheme.
Fig.29 FFT analysis at the 50Hz of fundamental
frequency for the phase voltage and calculation of THD
in Three level NPC inverter with SVM scheme.
The THD and FFT analysis with the fundamental output
frequency of 50Hz was done for atwo level inverter and
three level IGBT based NPC inverter for both line voltages
and phase voltages were shown in the figures and it shows
that THD value is lesser in SVM employed circuit when
compared to the corresponding SPWM scheme employed
circuit both in two level and three level NPC inverters.
V. CONCLUSION AND FUTURE SCOPE
A. Conclusion
In this paper simulation for Two level and Three level
NPC inverters employing with both the SPWM and SVM
schemes. The Table-IV and V shows the %THD in the line
voltage, and phase voltages when both the schemes are
employed. Table-IV and V showing the comparison of
SPWM and SVM schemes for two level and three level
NPC inverters. The results showing that
The %THD value was lesser in line voltage when
compared to the Phase voltage corresponding value.
The %THD value is lesser in SVM scheme employed
circuit compared to SPWM scheme employed circuit.
As the level increase the %THD value is reducing.
TABLE IV: %THD in line and phase voltages
comparison for two level NPC inverter with SPWM and
SVM schemes
Design and Analysis of SVPWM Scheme for Two and Three Level Inverters
International Journal of Advanced Technology and Innovative Research
Volume.08, IssueNo.07, July-2016, Pages: 1385-1391
TABLE V: %THD in line and phase voltages comparison
for three level NPC inverter with SPWM and SVM
schemes
B. Future Scope
This paper can be extended to the following things
To solve common mode voltage problem by suitable
redundancies and switching calculations.
To the other Multi level inverters.
VI. REFERENCES
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Author’s Profile: Prof. Ramesh R. Halakurki: He has
received his M.Tech in Industrial Electronics
from NIT Surat in 2000. He has a teaching
experience of 16 years. He is currently
working as a Professor and HOD, Dept of
EEE in SITAMS (Autonomous) College,
Chittoor.
Mr. M.Hari: He has received his Bachelor
degree in Electrical&Electronics Engineering
from MITS College, Madanapalle in 2013,
and currently pursuing his Postgraduate in
Power Electronics in SITAMS (Autonomous)
College, Chittoor.