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2-1
Design And Application Guide for High SpeedMOSFET Gate Drive Circuits
By Laszlo Balogh
ABSTRACT
The main purpose of this paper is to demonstrate a systematic approach to design high performancegate drive circuits for high speed switching applications. It is an informative collection of topics offeringa “one-stop-shopping” to solve the most common design challenges. Thus it should be of interest topower electronics engineers at all levels of experience.The most popular circuit solutions and their performance are analyzed, including the effect of parasiticcomponents, transient and extreme operating conditions. The discussion builds from simple to morecomplex problems starting with an overview of MOSFET technology and switching operation. Designprocedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolatedsolutions are described in great details. A special chapter deals with the gate drive requirements of theMOSFETs in synchronous rectifier applications.Several, step-by-step numerical design examples complement the paper.
I. INTRODUCTION
MOSFET – is an acronym for Metal OxideSemiconductor Field Effect Transistor and it isthe key component in high frequency, highefficiency switching applications across theelectronics industry. It might be surprising, butFET technology was invented in 1930, some 20years before the bipolar transistor. The firstsignal level FET transistors were built in the late1950’s while power MOSFETs have beenavailable from the mid 1970’s. Today, millionsof MOSFET transistors are integrated in modernelectronic components, from microprocessors,through “discrete” power transistors.
The focus of this topic is the gate driverequirements of the power MOSFET in variousswitch mode power conversion applications.
II. MOSFET TECHNOLOGY
The bipolar and the MOSFET transistorsexploit the same operating principle.Fundamentally, both type of transistors arecharge controlled devices which means that theiroutput current is proportional to the chargeestablished in the semiconductor by the control
electrode. When these devices are used asswitches, both must be driven from a lowimpedance source capable of sourcing andsinking sufficient current to provide for fastinsertion and extraction of the controlling charge.From this point of view, the MOSFETs have tobe driven just as “hard” during turn-on and turn-off as a bipolar transistor to achieve comparableswitching speeds. Theoretically, the switchingspeeds of the bipolar and MOSFET devices areclose to identical, determined by the timerequired for the charge carriers to travel acrossthe semiconductor region. Typical values inpower devices are approximately 20 to 200picoseconds depending on the size of the device.
The popularity and proliferation of MOSFETtechnology for digital and power applications isdriven by two of their major advantages over thebipolar junction transistors. One of these benefitsis the ease of use of the MOSFET devices inhigh frequency switching applications. TheMOSFET transistors are simpler to drive becausetheir control electrode is isolated from thecurrent conducting silicon, therefore acontinuous ON current is not required. Once theMOSFET transistors are turned-on, their drive
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current is practically zero. Also, the controllingcharge and accordingly the storage time in theMOSFET transistors is greatly reduced. Thisbasically eliminates the design trade-off betweenon state voltage drop – which is inverselyproportional to excess control charge – and turn-off time. As a result, MOSFET technologypromises to use much simpler and more efficientdrive circuits with significant economic benefitscompared to bipolar devices.
Furthermore, it is important to highlightespecially for power applications, thatMOSFETs have a resistive nature. The voltagedrop across the drain source terminals of aMOSFET is a linear function of the currentflowing in the semiconductor. This linearrelationship is characterized by the RDS(on) of theMOSFET and known as the on-resistance. On-resistance is constant for a given gate-to-sourcevoltage and temperature of the device. Asopposed to the -2.2mV/°C temperaturecoefficient of a p-n junction, the MOSFETsexhibit a positive temperature coefficient ofapproximately 0.7%/°C to 1%/°C. This positivetemperature coefficient of the MOSFET makes itan ideal candidate for parallel operation in higherpower applications where using a single devicewould not be practical or possible. Due to thepositive TC of the channel resistance, parallelconnected MOSFETs tend to share the currentevenly among themselves. This current sharingworks automatically in MOSFETs since thepositive TC acts as a slow negative feedbacksystem. The device carrying a higher current willheat up more – don’t forget that the drain tosource voltages are equal – and the highertemperature will increase its RDS(on) value. Theincreasing resistance will cause the current todecrease, therefore the temperature to drop.Eventually, an equilibrium is reached where theparallel connected devices carry similar currentlevels. Initial tolerance in RDS(on) values anddifferent junction to ambient thermal resistancescan cause significant – up to 30% – error incurrent distribution.
A. Device TypesAlmost all manufacturers have got their
unique twist on how to manufacture the bestpower MOSFETs, but all of these devices on themarket can be categorized into three basic devicetypes. These are illustrated in Fig. 1.
n+n+
n+ Substrate
n- EPI layer
GATE
SOURCE
DRAIN
p p
n+n+
n+ Substrate
n- EPI layer
GATE
SOURCE
DRAIN
p+ p+
(a)
(b)
n+n+
Substratep
GATE
SOURCE
DRAIN
p n
(c)
OXIDE
Fig. 1. Power MOSFET device types.Double-diffused MOS transistors were
introduced in the 1970’s for power applicationsand evolved continuously during the years.Using polycrystalline silicon gate structures andself-aligning processes, higher densityintegration and rapid reduction in capacitancesbecame possible.
The next significant advancement wasoffered by the V-groove or trench technology tofurther increase cell density in power MOSFETdevices. The better performance and denserintegration don’t come free however, as trenchMOS devices are more difficult to manufacture.
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The third device type to be mentioned here isthe lateral power MOSFETs. This device type isconstrained in voltage and current rating due toits inefficient utilization of the chip geometry.Nevertheless, they can provide significantbenefits in low voltage applications, like inmicroprocessor power supplies or assynchronous rectifiers in isolated converters.
The lateral power MOSFETs havesignificantly lower capacitances, therefore theycan switch much faster and they require muchless gate drive power.
B. MOSFET ModelsThere are numerous models available to
illustrate how the MOSFET works, neverthelessfinding the right representation might bedifficult. Most of the MOSFET manufacturersprovide Spice and/or Saber models for theirdevices, but these models say very little aboutthe application traps designers have to face inpractice. They provide even fewer clues how tosolve the most common design challenges.
A really useful MOSFET model whichwould describe all important properties of thedevice from an application point of view wouldbe very complicated. On the other hand, verysimple and meaningful models can be derived ofthe MOSFET transistor if we limit theapplicability of the model to certain problemareas.
The first model in Fig. 2 is based on theactual structure of the MOSFET device and canbe used mainly for DC analysis. The MOSFETsymbol in Fig. 2a represents the channelresistance and the JFET corresponds to theresistance of the epitaxial layer. The length, thusthe resistance of the epi layer is a function of thevoltage rating of the device as high voltageMOSFETs require thicker epitaxial layer.
Fig. 2b can be used very effectively to modelthe dv/dt induced breakdown characteristic of aMOSFET. It shows both main breakdownmechanisms, namely the dv/dt induced turn-onof the parasitic bipolar transistor - present in allpower MOSFETs - and the dv/dt induced turn-onof the channel as a function of the gateterminating impedance. Modern powerMOSFETs are practically immune to dv/dt
triggering of the parasitic npn transistor due tomanufacturing improvements to reduce theresistance between the base and emitter regions.
D
S
G
D
S
G
D
S
G
(a)
(b)
(c)
Fig. 2. Power MOSFET models.
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It must be mentioned also that the parasiticbipolar transistor plays another important role.Its base – collector junction is the famous bodydiode of the MOSFET.
Fig. 2c is the switching model of theMOSFET. The most important parasiticcomponents influencing switching performanceare shown in this model. Their respective roleswill be discussed in the next chapter which isdedicated to the switching procedure of thedevice.
C. MOSFET Critical ParametersWhen switch mode operation of the
MOSFET is considered, the goal is to switchbetween the lowest and highest resistance statesof the device in the shortest possible time. Sincethe practical switching times of the MOSFETs(~10ns to 60ns) is at least two to three orders ofmagnitude longer than the theoretical switchingtime (~20ps to 200ps), it seems important tounderstand the discrepancy. Referring back tothe MOSFET models in Fig. 2, note that allmodels include three capacitors connectedbetween the three terminals of the device.Ultimately, the switching performance of theMOSFET transistor is determined by howquickly the voltages can be changed across thesecapacitors.
Therefore, in high speed switchingapplications, the most important parameters arethe parasitic capacitances of the device. Two ofthese capacitors, the CGS and CGD capacitorscorrespond to the actual geometry of the devicewhile the CDS capacitor is the capacitance of thebase-collector diode of the parasitic bipolartransistor (body diode).
The CGS capacitor is formed by the overlapof the source and channel region by the gateelectrode. Its value is defined by the actualgeometry of the regions and stays constant(linear) under different operating conditions.
The CGD capacitor is the result of two effects.Part of it is the overlap of the JFET region andthe gate electrode in addition to the capacitanceof the depletion region which is non-linear. Theequivalent CGD capacitance is a function of thedrain source voltage of the device approximatedby the following formula:
DS1
GD,0GD VK1
CC
⋅+≈
The CDS capacitor is also non-linear since itis the junction capacitance of the body diode. Itsvoltage dependence can be described as:
DS2
DS,0DS VK
CC
⋅≈
Unfortunately, none of the above mentionedcapacitance values are defined directly in thetransistor data sheets. Their values are givenindirectly by the CISS, CRSS, and COSS capacitorvalues and must be calculated as:
RSSOSSDS
RSSISSGS
RSSGD
CCCCCC
CC
−=−=
=
Further complication is caused by the CGDcapacitor in switching applications because it isplaced in the feedback path between the inputand output of the device. Accordingly, itseffective value in switching applications can bemuch larger depending on the drain sourcevoltage of the MOSFET. This phenomenon iscalled the “Miller” effect and it can be expressedas:
( ) GDLfseqvGD, CRg1C ⋅⋅+=Since the CGD and CDS capacitors are voltage
dependent, the data sheet numbers are valid onlyat the test conditions listed. The relevant averagecapacitances for a certain application have to becalculated based on the required charge toestablish the actual voltage change across thecapacitors. For most power MOSFETs thefollowing approximations can be useful:
offDS,
specDS,specOSS,aveOSS,
offDS,
specDS,specRSS,aveGD,
VV
C2C
VV
C2C
⋅⋅=
⋅⋅=
The next important parameter to mention isthe gate mesh resistance, RG,I. This parasiticresistance describes the resistance associated bythe gate signal distribution within the device. Itsimportance is very significant in high speedswitching applications because it is in betweenthe driver and the input capacitor of the device,
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directly impeding the switching times and thedv/dt immunity of the MOSFET. This effect isrecognized in the industry, where real high speeddevices like RF MOSFET transistors use metalgate electrodes instead of the higher resistancepolysilicon gate mesh for gate signaldistribution. The RG,I resistance is not specifiedin the data sheets, but in certain applications itcan be a very important characteristic of thedevice. In the back of this paper, Appendix A4discusses a typical measurement setup todetermine the internal gate resistor value with animpedance bridge.
Obviously, the gate threshold voltage is alsoa critical characteristic. It is important to notethat the data sheet VTH value is defined at 25°Cand at a very low current, typically at 250µA.Therefore, it is not equal to the Miller plateauregion of the commonly known gate switchingwaveform. Another rarely mentioned fact aboutVTH is its approximately –7mV/°C temperaturecoefficient. It has particular significance in gatedrive circuits designed for logic level MOSFETwhere VTH is already low under the usual testconditions. Since MOSFETs usually operate atelevated temperatures, proper gate drive designmust account for the lower VTH when turn-offtime, and dv/dt immunity is calculated as shownin Appendix A and F.
The transconductance of the MOSFET is itssmall signal gain in the linear region of itsoperation. It is important to point out that everytime the MOSFET is turned-on or turned-off, itmust go through its linear operating mode wherethe current is determined by the gate-to-sourcevoltage. The transconductance, gfs, is the smallsignal relationship between drain current andgate-to-source voltage:
GS
Dfs dV
dIg =
Accordingly, the maximum current of theMOSFET in the linear region is given by:
( ) fsthGSD gVVI ⋅−=Rearranging this equation for VGS yields the
approximate value of the Miller plateau as afunction of the drain current.
fs
DthMillerGS, g
IVV +=
Other important parameters like the sourceinductance (LS) and drain inductance (LD)exhibit significant restrictions in switchingperformance. Typical LS and LD values are listedin the data sheets, and they are mainly dependanton the package type of the transistor. Theireffects can be investigated together with theexternal parasitic components usually associatedwith layout and with accompanying externalcircuit elements like leakage inductance, acurrent sense resistor, etc.
For completeness, the external series gateresistor and the MOSFET driver’s outputimpedance must be mentioned as determiningfactors in high performance gate drive designs asthey have a profound effect on switching speedsand consequently on switching losses.
III. SWITCHING APPLICATIONS
Now, that all the players are identified, let’sinvestigate the actual switching behavior of theMOSFET transistors. To gain a betterunderstanding of the fundamental procedure, theparasitic inductances of the circuit will beneglected. Later their respective effects on thebasic operation will be analyzed individually.Furthermore, the following descriptions relate toclamped inductive switching because mostMOSFET transistors and high speed gate drivecircuits used in switch mode power supplieswork in that operating mode.
VOUT
RGATE
IDC
VDRV
Fig. 3. Simplified clamped inductive switchingmodel.
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The simplest model of clamped inductiveswitching is shown in Fig. 3, where the DCcurrent source represents the inductor. Its currentcan be considered constant during the shortswitching interval. The diode provides a path forthe current during the off time of the MOSFETand clamps the drain terminal of the device to theoutput voltage symbolized by the battery.
A. Turn-On ProcedureThe turn-on event of the MOSFET transistor
can be divided into four intervals as depicted inFig. 4.
VDRV
D
S
GRHI
RGATE RG,I
CGD
CGS
CDS
IG
ID
ID
VDS
IG
VGS
VTH
3 421
Fig. 4. MOSFET turn-on time intervals.
In the first step the input capacitance of thedevice is charged from 0V to VTH. During thisinterval most of the gate current is charging theCGS capacitor. A small current is flowing throughthe CGD capacitor too. As the voltage increases atthe gate terminal and the CGD capacitor’s voltagehas to be slightly reduced.
This period is called the turn-on delay,because both the drain current and the drainvoltage of the device remain unchanged.
Once the gate is charged to the thresholdlevel, the MOSFET is ready to carry current. Inthe second interval the gate is rising from VTH tothe Miller plateau level, VGS,Miller. This is thelinear operation of the device when current isproportional to the gate voltage. On the gate side,current is flowing into the CGS and CGDcapacitors just like in the first time interval andthe VGS voltage is increasing. On the output sideof the device, the drain current is increasing,while the drain-to-source voltage stays at theprevious level (VDS,OFF). This can be understoodlooking at the schematic in Fig. 3. Until all thecurrent is transferred into the MOSFET and thediode is turned-off completely to be able to blockreverse voltage across its pn junction, the drainvoltage must stay at the output voltage level.
Entering into the third period of the turn-onprocedure the gate is already charged to thesufficient voltage (VGS,Miller) to carry the entireload current and the rectifier diode is turned off.That now allows the drain voltage to fall. Whilethe drain voltage falls across the device, the gate-to-source voltage stays steady. This is the Millerplateau region in the gate voltage waveform. Allthe gate current available from the driver isdiverted to discharge the CGD capacitor tofacilitate the rapid voltage change across thedrain-to-source terminals. The drain current ofthe device stays constant since it is now limitedby the external circuitry, i.e. the DC currentsource.
The last step of the turn-on is to fullyenhance the conducting channel of the MOSFETby applying a higher gate drive voltage. The finalamplitude of VGS determines the ultimate on-resistance of the device during its on-time.Therefore, in this fourth interval, VGS isincreased from VGS,Miller to its final value, VDRV.
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This is accomplished by charging the CGS andCGD capacitors, thus gate current is now splitbetween the two components. While thesecapacitors are being charged, the drain current isstill constant, and the drain-to-source voltage isslightly decreasing as the on-resistance of thedevice is being reduced.
B. Turn-Off ProcedureThe description of the turn-off procedure for
the MOSFET transistor is basically back trackingthe turn-on steps from the previous section. Startwith VGS being equal to VDRV and the current inthe device is the full load current represented byIDC in Fig. 3. The drain-to-source voltage isbeing defined by IDC and the RDS(on) of theMOSFET. The four turn-off steps are shown inFig. 5. for completeness.
VDRV
D
S
GRLO
RGATE RG,I
CGD
CGS
CDS
ID
IG
ID
VDS
IG
VGS
VTH
3 421
Fig. 5. MOSFET turn-off time intervals
The first time interval is the turn-off delaywhich is required to discharge the CISScapacitance from its initial value to the Millerplateau level. During this time the gate current issupplied by the CISS capacitor itself and it isflowing through the CGS and CGD capacitors ofthe MOSFET. The drain voltage of the device isslightly increasing as the overdrive voltage isdiminishing. The current in the drain isunchanged.
In the second period, the drain-to-sourcevoltage of the MOSFET rises from ID⋅RDS(on) tothe final VDS(off) level, where it is clamped to theoutput voltage by the rectifier diode according tothe simplified schematic of Fig. 3. During thistime period – which corresponds to the Millerplateau in the gate voltage waveform - the gatecurrent is strictly the charging current of the CGDcapacitor because the gate-to-source voltage isconstant. This current is provided by the bypasscapacitor of the power stage and it is subtractedfrom the drain current. The total drain currentstill equals the load current, i.e. the inductorcurrent represented by the DC current source inFig. 3.
The beginning of the third time interval issignified by the turn-on of the diode, thusproviding an alternative route to the load current.The gate voltage resumes falling from VGS,Millerto VTH. The majority of the gate current iscoming out of the CGS capacitor, because the CGDcapacitor is virtually fully charged from theprevious time interval. The MOSFET is in linearoperation and the declining gate-to-sourcevoltage causes the drain current to decrease andreach near zero by the end of this interval.Meanwhile the drain voltage is steady at VDS(off)due to the forward biased rectifier diode.
The last step of the turn-off procedure is tofully discharge the input capacitors of the device.VGS is further reduced until it reaches 0V. Thebigger portion of the gate current, similarly to thethird turn-off time interval, supplied by the CGScapacitor. The drain current and the drain voltagein the device are unchanged.
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Summarizing the results, it can be concludedthat the MOSFET transistor can be switchedbetween its highest and lowest impedance states(either turn-on or turn-off) in four time intervals.The lengths of all four time intervals are afunction of the parasitic capacitance values, therequired voltage change across them and theavailable gate drive current. This emphasizes theimportance of the proper component selectionand optimum gate drive design for high speed,high frequency switching applications.
Characteristic numbers for turn-on, turn-offdelays, rise and fall times of the MOSFETswitching waveforms are listed in the transistordata sheets. Unfortunately, these numberscorrespond to the specific test conditions and toresistive load, making the comparison ofdifferent manufacturers’ products difficult. Also,switching performance in practical applicationswith clamped inductive load is significantlydifferent from the numbers given in the datasheets.
C. Power LossesThe switching action in the MOSFET
transistor in power applications will result insome unavoidable losses, which can be dividedinto two categories.
The simpler of the two loss mechanisms isthe gate drive loss of the device. As describedbefore, turning-on or off the MOSFET involvescharging or discharging the CISS capacitor. Whenthe voltage across a capacitor is changing, acertain amount of charge has to be transferred.The amount of charge required to change thegate voltage between 0V and the actual gatedrive voltage VDRV, is characterized by thetypical gate charge vs. gate-to-source voltagecurve in the MOSFET datasheet. An example isshown in Fig. 6.
This graph gives a relatively accurate worstcase estimate of the gate charge as a function ofthe gate drive voltage. The parameter used togenerate the individual curves is the drain-to-source off state voltage of the device. VDS(off)influences the Miller charge – the area below theflat portion of the curves – thus also, the totalgate charge required in a switching cycle. Once
the total gate charge is obtained from Fig. 6, thegate charge losses can be calculated as:
DRVGDRVGATE fQVP ⋅⋅=where VDRV is the amplitude of the gate drivewaveform and fDRV is the gate drive frequency –which is in most cases equal to the switchingfrequency. It is interesting to notice that theQG⋅fDRV term in the previous equation gives theaverage bias current required to drive the gate.
The power lost to drive the gate of theMOSFET transistor is dissipated in the gatedrive circuitry. Referring back to Figures 4 and5, the dissipating components can be identifiedas the combination of the series ohmicimpedances in the gate drive path. In everyswitching cycle the required gate charge has topass through the driver output impedances, theexternal gate resistor, and the internal gate meshresistance. As it turns out, the power dissipationis independent of how quickly the charge isdelivered through the resistors. Using the resistordesignators from Figures 4 and 5, the driverpower dissipation can be expressed as:
OFFDRV,ONDRV,DRV
IG,GATELO
DRVGDRVLOOFFDRV,
IG,GATEHI
DRVGDRVHIONDRV,
PPPRRRfQVR
21P
RRRfQVR
21P
+=++
⋅⋅⋅⋅=
++⋅⋅⋅⋅=
Vgs,
Gat
e-to
-Sou
rce
Volta
ge (V
)
Qg, Total Gate Charge (nC)
VDS
VDRV
QG
Fig. 6. Typical gate charge vs. gate-to-sourcevoltage.
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In the previous equations, the gate drivecircuit is represented by a resistive outputimpedance and this assumption is valid for MOSbased gate drivers. When bipolar transistors areutilized in the gate drive circuit, the outputimpedance becomes non-linear and the equationsdo not yield the correct answers. It is safe toassume that with low value gate resistors (<5Ω)most gate drive losses are dissipated in thedriver. If RGATE is sufficiently large to limit IGbelow the output current capability of the bipolardriver, the majority of the gate drive power lossis then dissipated in RGATE.
In addition to the gate drive power loss, thetransistors accrue switching losses in thetraditional sense due to high current and highvoltage being present in the devicesimultaneously for a short period. In order toensure the least amount of switching losses, theduration of this time interval must be minimized.Looking at the turn-on and turn-off procedures ofthe MOSFET, this condition is limited tointervals 2 and 3 of the switching transitions inboth turn-on and turn-off operation. These timeintervals correspond to the linear operation of thedevice when the gate voltage is between VTH andVGS,Miller, causing changes in the current of thedevice and to the Miller plateau region when thedrain voltage goes through its switchingtransition.
This is a very important realization toproperly design high speed gate drive circuits. Ithighlights the fact that the most importantcharacteristic of the gate driver is its source-sinkcurrent capability around the Miller plateauvoltage level. Peak current capability, which ismeasured at full VDRV across the driver’s outputimpedance, has very little relevance to the actualswitching performance of the MOSFET. Whatreally determines the switching times of thedevice is the gate drive current capability whenthe gate-to-source voltage, i.e. the output of thedriver is at ~5V (~2.5V for logic levelMOSFETs).
A crude estimate of the MOSFET switchinglosses can be calculated using simplified linearapproximations of the gate drive current, draincurrent and drain voltage waveforms duringperiods 2 and 3 of the switching transitions. First
the gate drive currents must be determined forthe second and third time intervals respectively:
( )
G.IGATEHI
MillerGS,DRVG3
G.IGATEHI
THMillerGS,DRVG2
RRRVV
I
RRRVV0.5V
I
++−
=
+++⋅−
=
Assuming that IG2 charges the input capacitorof the device from VTH to VGS,Miller and IG3 is thedischarge current of the CRSS capacitor while thedrain voltage changes from VDS(off) to 0V, theapproximate switching times are given as:
G3
offDS,RSS
G2
THMillerGS,ISS
IV
Ct3
IVV
Ct2
⋅=
−⋅=
During t2 the drain voltage is VDS(off) and thecurrent is ramping from 0A to the load current, ILwhile in t3 time interval the drain voltage isfalling from VDS(off) to near 0V. Again, usinglinear approximations of the waveforms, thepower loss components for the respective timeintervals can be estimated:
LoffDS,
LoffDS,
I2
VTt3P3
2IV
Tt2P2
⋅⋅=
⋅⋅=
where T is the switching period. The totalswitching loss is the sum of the two losscomponents, which yields the followingsimplifed expression:
Tt3t2
2IV
P LDS(off)SW
+⋅⋅
=
Even though the switching transitions arewell understood, calculating the exact switchinglosses is almost impossible. The reason is theeffect of the parasitic inductive componentswhich will significantly alter the current andvoltage waveforms, as well as the switchingtimes during the switching procedures. Takinginto account the effect of the different source anddrain inductances of a real circuit would result insecond order differential equations to describethe actual waveforms of the circuit. Since thevariables, including gate threshold voltage,MOSFET capacitor values, driver outputimpedances, etc. have a very wide tolerance, the
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above described linear approximation seems tobe a reasonable enough compromise to estimateswitching losses in the MOSFET.
D. Effects of Parasitic ComponentsThe most profound effect on switching
performance is exhibited by the sourceinductance. There are two sources for parasiticsource inductance in a typical circuit, the sourcebond wire neatly integrated into the MOSFETpackage and the printed circuit board wiringinductance between the source lead and thecommon ground. This is usually referenced asthe negative electrode of the high frequency filtercapacitor around the power stage and the bypasscapacitor of the gate driver. Current senseresistors in series with the source can addadditional inductance to the previous twocomponents.
There are two mechanisms in the switchingprocedure which involve the source inductor. Atthe beginning of the switching transitions thegate current is increasing very rapidly asillustrated in Figures 4 and 5. This current mustflow through the source inductance and will beslowed down based on the inductor value.Consequently, the time required tocharge/discharge the input capacitance of theMOSFET gets longer, mainly influencing theturn-on and turn-off delays (step 1).Furthermore, the source inductor and the CISScapacitor form a resonant circuit as shown inFig. 7.
VDRV
RGLS
CISS
Fig. 7. Gate drive resonant circuit components.
The resonant circuit is exited by the steepedges of the gate drive voltage waveform and itis the fundamental reason for the oscillatoryspikes observed in most gate drive circuits.Fortunately, the otherwise very high Q resonancebetween CISS and LS is damped or can bedamped by the series resistive components of theloop which include the driver output impedance,the external gate resistor, and the internal gatemesh resistor. The only user adjustable value,RGATE, can be calculated for optimumperformance by:
( )IG,DRVISS
SOPTGATE, RR
CL2R +−⋅=
Smaller resistor values will result anovershoot in the gate drive voltage waveform,but also result in faster turn-on speed. Higherresistor values will underdamp the oscillationand extend the switching times without offeringany benefit for the gate drive design.
The second effect of the source inductance isa negative feedback whenever the drain currentof the device is changing rapidly. This effect ispresent in the second time interval of the turn-onand in the third time interval of the turn-offprocedure. During these periods the gate voltageis between VTH and VGS,Miller, and the gatecurrent is defined by the voltage across the driveimpedance, VDRV-VGS. In order to increase thedrain current quickly, significant voltage has tobe applied across the source inductance. Thisvoltage reduces the available voltage across thedrive impedance, thus reduces the rate of changein the gate drive voltage which will result in alower di/dt of the drain current. The lower di/dtrequires less voltage across the sourceinductance. A delicate balance of gate currentand drain di/dt is established through thenegative feedback by the source inductor.
The other parasitic inductance of theswitching network is the drain inductance whichis again composed of several components. Theyare the packaging inductance inside the transistorpackage, all the inductances associated withinterconnection and the leakage inductance of atransformer in isolated power supplies. Theireffect can be lumped together since they are inseries with each other. They act as a turn-on
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snubber for the MOSFET. During turn-on theylimit the di/dt of the drain current and reduce thedrain-to-source voltage across the device by thefactor of LD⋅di/dt. In fact, LD can reduce the turn-on switching losses significantly. While higherLD values seem beneficial at turn-on, they causeconsiderable problems at turn-off when the draincurrent must ramp down quickly. To support therapid reduction in drain current due to the turn-off of the MOSFET, a voltage in the oppositedirection with respect to turn-on must be acrossLD. This voltage is above the theoretical VDS(off)level, producing an overshoot in the drain-to-source voltage and an increase in turn-offswitching losses.
Accurate mathematical analysis of thecomplete switching transitions including theeffects of parasitic inductances are available inthe literature but points beyond the scope of thispaper.
IV. GROUND REFERENCED GATE DRIVE
A. PWM Direct DriveIn power supply applications, the simplest
way of driving the gate of the main switchingtransistor is to utilize the gate drive output of thePWM controller as shown in Fig. 8.
RGATE
VCC
OUT
GND
VDRV (VBIAS)
distance!
PWMcontroller
Fig. 8. Direct gate drive circuit.
The most difficult task in direct gate drives isto optimize the circuit layout. As indicated inFig. 8, there might be considerable distancebetween the PWM controller and the MOSFET.
This distance introduces a parasiticinductance due to the loop formed by the gatedrive and ground return traces which can slowdown the switching speed and can cause ringingin the gate drive waveform. Even with a groundplane, the inductance can not be completelyeliminated since the ground plane provides a lowinductance path for the ground return currentonly. To reduce the inductance linked to the gatedrive connection, a wider PCB trace is desirable.Another problem in direct gate drive is thelimited drive current capability of the PWMcontrollers. Very few integrated circuits offermore than 1A peak gate drive capability. Thiswill limit the maximum die size which can bedriven at a reasonable speed by the controller.Another limiting factor for MOSFET die sizewith direct gate drive is the power dissipation ofthe driver within the controller. An external gateresistor can mitigate this problem as discussedbefore. When direct gate drive is absolutelynecessary for space and/or cost savings, specialconsiderations are required to provideappropriate bypassing for the controller. Thehigh current spikes driving the gate of theMOSFET can disrupt the sensitive analogcircuitry inside the PWM controller. AsMOSFET die size increases, so too does gatecharge required. The selection of the properbypass capacitor calls for a little bit morescientific approach than picking the usual 0.1µFor 1µF bypass capacitor.
1. Sizing the bypass capacitor.In this chapter the calculation of the
MOSFET gate driver’s bypass capacitor isdemonstrated. This capacitor is the same as thePWM controller’s bypass capacitor in direct gatedrive application because that is the capacitorwhich provides the gate drive current at turn-on.In case of a separate driver circuit, whether agate drive IC or discrete solution, this capacitormust be placed close, preferably directly acrossthe bias and ground connection of the driver.
2-12
There are two current components toconsider. One is the quiescent current which canchange by a 10x factor based on the input stateof some integrated drivers. This itself will causea duty cycle dependent ripple across the bypasscapacitor which can be calculated as:
DRVDRV
MAXHIQ,Q fC
DI∆V
⋅⋅
=
where it is assumed that the driver’squiescent current is higher when its input isdriven high.
The other ripple component is the gatecurrent. Although the actual current amplitude isnot know in most cases, the voltage ripple acrossthe bypass capacitor can be determined based onthe value of the gate charge. At turn-on, thischarge is taken out of the bypass capacitor andtransferred to the MOSFET input capacitor.Accordingly the ripple is given by:
DRV
GQG C
Q∆V =
Using the principle of superposition andsolving the equations for CDRV, the bypasscapacitor value for a tolerable ripple voltage(∆V) can be found:
∆V
QfDI
CG
DRV
MAXHIQ,
DRV
+⋅=
where IQ,HI is the quiescent current of thedriver when its input is driven high, DMAX is themaximum duty cycle of the driver while theinput can stay high, fDRV is the operatingfrequency of the driver, and QG is the total gatecharge based on the amplitude of the gate driveand drain-to-source off state voltages.
2. Driver protection.Another must-do with direct drive and with
gate drive ICs using bipolar output stage is toprovide suitable protection for the output bipolartransistors against reverse currents. As indicatedin the simplified diagram in Fig. 9, the outputstage of the integrated bipolar drivers is builtfrom npn transistors due to their more efficientarea utilization and better performance.
RGATE
VCC
OUT
GND
VDRV
PWM orDriver IC
Fig. 9. Gate drive with integrated bipolartransistors.
The npn transistors can handle currents inone direction only. The high side npn can sourcebut can not sink current while the low side isexactly the opposite. Unavoidable oscillationsbetween the source inductor and the inputcapacitor of the MOSFET during turn-on andturn-off necessitate that current should be able toflow in both directions at the output of the driver.To provide a path for reverse currents, lowforward voltage drop Schottky diodes aregenerally needed to protect the outputs. Thediodes must be placed very close to the outputpin and to the bypass capacitor of the driver. It isimportant to point out also, that the diodesprotect the driver only, they are not clamping thegate-to-source voltage against excessive ringingespecially with direct drive where the control ICmight be far away from the gate-source terminalsof the MOSFET.
B. Bipolar Totem-Pole DriverOne of the most popular and cost effective
drive circuit for driving MOSFETs is a bipolar,non-inverting totem-pole driver as shown inFig. 10.
Like all external drivers, this circuit handlesthe current spikes and power losses making theoperating conditions for the PWM controllermore favorable. Of course, they can be andshould be placed right next to the powerMOSFET they are driving. That way the highcurrent transients of driving the gate arelocalized in a very small loop area, reducing thevalue of parasitic inductances.
2-13
RGATE
VCC
OUT
GND
VBIAS VDRV
distance!
PWMcontroller
RB
R
Fig. 10. Bipolar totem-pole MOSFET driver.Even though the driver is built from discrete
components, it needs its own bypass capacitorplaced across the collectors of the upper npn andthe lower pnp transistors. Ideally there is asmoothing resistor or inductor between thebypass capacitor of the driver and the bypasscapacitor of the PWM controller for increasednoise immunity. The RGATE resistor of Fig. 10 isoptional and RB can be sized to provide therequired gate impedance based on the largesignal beta of the driver transistors.
An interesting property of the bipolar totem-pole driver that the two base-emitter junctionsprotect each other against reverse breakdown.Furthermore, assuming that the loop area isreally small and RGATE is negligible, they canclamp the gate voltage between VBIAS+VBE andGND-VBE using the base-emitter diodes of thetransistors. Another benefit of this solution,based on the same clamp mechanism, is that thenpn-pnp totem-pole driver does not require anySchottky diode for reverse current protection.
C. MOSFET Totem-Pole DriverThe MOSFET equivalent of the bipolar
totem-pole driver is pictured in Fig. 11. All thebenefits mentioned about the bipolar totem-poledriver are equally applicable to thisimplementation.
Unfortunately, this circuit has severaldrawbacks compared to the bipolar versionwhich explain that it is very rarely implementeddiscretely. The circuit of Fig. 11 is an invertingdriver, therefore the PWM output signal must beinverted. In addition, the suitable MOSFET
RGATE
VCC
OUT
GND
VBIAS VDRV
distance!
PWMcontroller
R
Fig. 11. MOSFET based totem-pole driver.transistors are more expensive than the bipolarones and they will have a large shoot throughcurrent when their common gate voltage is intransition. This problem can be circumvented byadditional logic or timing components whichtechnique is extensively used in ICimplementations.
D. Speed Enhancement CircuitsWhen speed enhancement circuits are
mentioned designers exclusively considercircuits which speed-up the turn-off process ofthe MOSFET. The reason is that the turn-onspeed is usually limited by the turn-off, orreverse recovery speed of the rectifiercomponent in the power supply. As discussedwith respect to the inductive clamped model inFig. 3, the turn-on of the MOSFET coincideswith the turn-off of the rectifier diode. Therefore,the fastest switching action is determined by thereverse recovery characteristic of the diode, notby the strength of the gate drive circuit. In anoptimum design the gate drive speed at turn-on ismatched to the diode switching characteristic.Considering also that the Miller region is closerto GND than to the final gate drive voltage VDRV,a higher voltage can be applied across the driveroutput impedance and the gate resistor. Usuallythe obtained turn-on speed is sufficient to drivethe MOSFET.
The situation is vastly different at turn-off. Intheory, the turn-off speed of the MOSFETdepends only on the gate drive circuit. A highercurrent turn-off circuit can discharge the inputcapacitors quicker, providing shorter switching
2-14
times and consequently lower switching losses.The higher discharge current can be achieved bya lower output impedance MOSFET driverand/or a negative turn-off voltage in case of thecommon N-channel device. While fasterswitching can potentially lower the switchinglosses, the turn-off speed-up circuits increase theringing in the waveforms due to the higher turn-off di/dt and dv/dt of the MOSFET. This issomething to consider in selecting the propervoltage rating and EMI containment for thepower device.
1. Turn-off diode.The following examples of turn-off circuits
are demonstrated on simple ground referencedgate drive circuits, but are equally applicable toother implementations discussed later in thepaper. The simplest technique is the anti-paralleldiode, as shown in Fig. 12.
RGATE
VCC
OUT
GND
VDRV
Driver
DOFF
Fig. 12. Simple turn-off speed enhancementcircuit.
In this circuit RGATE allows adjustment of theMOSFET turn-on speed. During turn-off theanti-parallel diode shunts out the resistor. DOFFworks only when the gate current is higher than:
GATE
FWDD,G R
VI >
typically around 150mA using a 1N4148 andaround 300mA with a BAS40 Schottky anti-parallel diode. Consequently, as the gate-to-source voltage approaches 0V the diode helpsless and less. As a result, this circuit will providea significant reduction in turn-off delay time, butonly incremental improvement on switchingtimes and dv/dt immunity. Another disadvantage
is that the gate turn-off current still must flowthrough the driver’s output impedance.
2. PNP turn-off circuit.Undoubtedly the most popular arrangement
for fast turn-off is the local pnp turn-off circuit ofFig. 13. With the help of QOFF, the gate and thesource are shorted locally at the MOSFETterminals during turn-off. RGATE limits the turn-on speed, and DON provides the path for the turn-on current. Also, DON protects the base-emitterjunction of QOFF against reverse breakdown atthe beginning of the turn-on procedure.
The most important advantage of thissolution is that the high peak discharge current ofthe MOSFET input capacitance is confined inthe smallest possible loop between the gate,source and collector, emitter connections of thetwo transistors.
RGATE
VCC
OUT
GND
VDRV
DriverDON
QOFF
Fig. 13. Local pnp turn-off circuit.The turn-off current does not go back to the
driver, it does not cause ground bounce problemsand the power dissipation of the driver is reducedby a factor of two. The turn-off transistor shuntsout the gate drive loop inductance, the potentialcurrent sense resistor, and the output impedanceof the driver. Furthermore, QOFF never saturateswhich is important to be able to turn it on and offquickly. Taking a closer look at the circuitreveals that this solution is a simplified bipolartotem-pole driver, where the npn pull-uptransistor is replaced by a diode. Similarly to thetotem-pole driver, the MOSFET gate is clampedby the turn-off circuit between GND-0.7V andVDRV+0.7V approximately, eliminating the riskof excessive voltage stress at the gate. The onlyknown shortcoming of the circuit is that it can
2-15
not pull the gate all the way to 0V because of thevoltage drop across the base-emitter junction ofQOFF.
3. NPN turn-off circuit.The next circuit to examine is the local npn
turn-off circuit, illustrated in Fig. 14. Similarly tothe pnp solution, the gate discharge current iswell localized. The npn transistor holds the gatecloser to GND than its pnp counterpart. Also,this implementation provides a self biasingmechanism to keep the MOSFET off duringpower up.
Unfortunately, this circuit has somesignificant drawbacks. The npn turn-offtransistor, QOFF is an inverting stage, it requiresan inverted PWM signal provided by QINV.
RGATE
VCC
OUT
GND
VDRV
Driver
DON
QOFF
QINV
Fig. 14. Local npn self biasing turn-off circuit.The inverter draws current from the driver
during the on time of the MOSFET, lowering theefficiency of the circuit. Furthermore, QINVsaturates during the on-time which can prolongturn-off delay in the gate drive.
4. NMOS turn-off circuit.An improved, lower parts count
implementation of this principle is offered inFig. 15, using a dual driver to provide theinverted PWM signal for a small N-channeldischarge transistor.
This circuit offers very fast switching andcomplete discharge of the MOSFET gate to 0V.RGATE sets the turn-on speed like before, but isalso utilized to prevent any shoot throughcurrents between the two outputs of the driver incase of imperfect timing of the drive signals.Another important fact to consider is that the
COSS capacitance of QOFF is connected in parallelto the CISS capacitance of the main powerMOSFET. This will increase the effective “TotalGate Charge” the driver has to provide. Also toconsider, the gate of the main MOSFET isfloating before the outputs of the driver ICbecomes intelligent during power up.
RGATE
VCC
OUT
GND
VDRV
DriverQOFFOUT
Fig. 15. Improved N-channel MOS-based turn-off circuit.
E. dv/dt ProtectionThere are two situations when the MOSFET
has to be protected against dv/dt triggered turn-on. One is during power up where protection canusually be provided by a resistor between thegate and source terminals of the device. The pulldown resistor value depends on the worst casedv/dt of the power rail during power upaccording to:
ONTURNGD
THGS dv
dtCVR
−
⋅<
In this calculation the biggest challenge is tofind the highest dv/dt which can occur duringpower up and provide sufficient protection forthat particular dv/dt.
The second situation is in normal operationwhen turn-off dv/dt is forced across the drain-to-source terminals of the power switch while it isoff. This situation is more common than one mayoriginally anticipate. All synchronous rectifierswitches are operated in this mode as will bediscussed later. Most resonant and soft switchingconverters can force a dv/dt across the mainswitch right after its turn-off instance, driven bythe resonant components of the power stage.
2-16
Since these dv/dt’s are significantly higher thanduring power up and VTH is usually lower due tothe higher operating junction temperature,protection must be provided by the low outputimpedance of the gate drive circuit.
The first task is to determine the maximumdv/dt which can occur under worst caseconditions. The next step in evaluating thesuitability of a particular device to theapplication is to calculate its natural dv/dt limit,imposed by the internal gate resistance and theCGD capacitance of the MOSFET. Assumingideal (zero Ohm) external drive impedance thenatural dv/dt limit is:
( )GDIG,
JTH
LIMIT CR25T0.007V
dtdv
⋅−⋅−=
where VTH is the gate threshold at 25°C, -0.007is the temperature coefficient of VTH, RG,I is theinternal gate mesh resistance and CGD is the gate-to-drain capacitor. If the natural dv/dt limit of theMOSFET is lower than the maximum dv/dt ofthe resonant circuit, either a different MOSFETor a negative gate bias voltage must beconsidered. If the result is favorable for thedevice, the maximum gate drive impedance canbe calculated by rearranging and solving theprevious equation according to:
( )MAXGD
JTHMAX dv
dtC
25T0.007VR
⋅−⋅−=
where RMAX=RLO+RGATE+RG,I.Once the maximum pull down resistor value
is given, the gate drive design can be executed. Itshould be taken into account that the driver’spull down impedance is also temperaturedependent. At elevated junction temperature theMOSFET based gate drive ICs exhibit higheroutput resistance than at 25°C where they areusually characterized.
Turn-off speed enhancement circuits can alsobe used to meet dv/dt immunity for the MOSFETsince they can shunt out RGATE at turn-off andduring the off state of the device. For instance,the simple pnp turn-off circuit of Fig. 13 canboost the maximum dv/dt of the MOSFET. Theequation modified by the effect of the beta of thepnp transistor yields the increased dv/dt ratingof:
( )
GDLOGATE
IG,
JTH
Cβ
RRR
25T0.007Vdtdv
⋅
++
−⋅−=
In the dv/dt calculations a returning factor isthe internal gate resistance of the MOSFET,which is not defined in any data sheet. Aspointed out earlier, this resistance depends on thematerial properties used to distribute the gatesignal, the cell density, and the cell design withinthe semiconductor.
V. SYNCHRONOUS RECTIFIER DRIVE
The MOSFET synchronous rectifier is aspecial case of ground referenced switches.These devices are the same N-channelMOSFETs used in traditional applications, butapplied in low voltage outputs of the powersupplies instead of rectifier diodes. They usuallywork with a very limited drain-to-source voltageswing, therefore, their CDS and CGD capacitorsexhibit relatively large capacitance values.Moreover, their application is unique becausethese devices are operated in the fourth quadrantof their V-I plane. The current is flowing fromthe source toward the drain terminal. That makesthe gate drive signal kind of irrelevant. If thecircumstances, other components around thesynchronous switch require, current will flow inthe device, either through the resistive channel orthrough the parasitic body diode of theMOSFET. The easiest model to examine theswitching behavior of the MOSFET synchronousrectifier is a simplified buck power stage wherethe rectifier diode is replaced by the QSRtransistor as shown in Fig. 16.
ILVQFW
QSR
Fig. 16. Simplified synchronous rectificationmodel.
2-17
The first thing to recognize in this circuit isthat the operation of the synchronous rectifierMOSFET depends on the operation of anothercontrolled switch in the circuit, namely theforward switch, QFW. The two gate drivewaveforms are not independent and specifictiming criteria must be met. Overlapping gatedrive signals would be fatal because the twoMOSFETs would short circuit the voltage sourcewithout any significant current limitingcomponent in the loop. Ideally, the two switcheswould turn-on and off simultaneously to preventthe body diode of the QSR MOSFET to turn-on.Unfortunately, the window of opportunity toavoid body diode conduction is very narrow.Very accurate, adaptive timing and fastswitching speeds are required, which are usuallyout of reach with traditional design techniques.
Consequently, in most cases a brief period –from 20ns to 80ns – of body diode conductionprecedes the turn-on and follows the turn-off ofthe synchronous MOSFET switch.
A. Gate ChargeDuring the body diode conduction period the
full load current is established in the device andthe drain-to-source voltage equals the body diodeforward voltage drop. Under these conditions therequired gate charge to turn the device on or offis different from the gate charge needed intraditional first quadrant operation. When thegate is turned-on, the drain-to-source voltage ispractically zero and the CGD and CDS capacitorsare discharged. Also, the Miller effect is notpresent, there is no feedback between the drainand gate terminals. Therefore, the required gatecharge equals the charge needed to raise thevoltage across the gate-to-source and gate-to-drain capacitors from 0V to the final VDRV level.For an accurate estimate, the low voltage averagevalue of the CGD capacitor between 0V and VDRVhas to be determined according to:
DRV
SPECDS,RSS.SPECSRGD, V0.5
VC2C
⋅⋅⋅=
The following equation can then be used toestimate the total gate charge of the synchronousMOSFET rectifier:
( ) DRVSRGD,GSSRQ, VCCQ ⋅+=This value is appreciably lower than the total
gate charge listed in the MOSFET data sheets.The same MOSFET with an identical drivercircuit used for synchronous rectification can beturned on or off quicker than if it would bedriven in its first quadrant operation.Unfortunately, this advantage can not be realizedsince the low RDS(on) devices, applicable forsynchronous rectification, usually have prettylarge input and output capacitances due to theirlarge die size.
Another important note from driver powerdissipation point of view is that the total gatecharge value from the data sheet should beconsidered. Although the gate charge deliveredby the driver during turn-on is less than thetypical number listed in the data sheet, thatcovers a portion of the total charge passingthrough the driver output impedance. Beforeturn-on, while the drain-to-source voltagechanges across the device, the Miller chargeprovided by the power stage must flow throughthe driver of the synchronous MOSFET causingadditional power dissipation. This phenomenoncan be seen in Fig. 17, which is part of the nextdiscussion on dv/dt considerations.
The turn-off procedure of the synchronousMOSFET obeys the same rules as the turn-onprocedure, therefore all the previousconsiderations with respect to gate charge areapplicable.
B. dv/dt ConsiderationsFig. 17 shows the most important circuit and
current components during the turn-on and turn-off procedures of QSR. Actually, it is moreaccurate to say that the switching actions takingplace in QFW forces QSR to turn-on or offindependently of its own gate drive signal.
The turn-on of QSR starts with the turn-off ofQFW. When the gate drive signal of QFWtransitions from high to low, the switching nodetransitions from the input voltage level to GND.The current stays in the forward switch until theCRSS capacitor is discharged and the body diode
2-18
of QSR is forward biased. At that instant thesynchronous MOSFET takes over the currentflow and QFW turns off completely. After a shortdelay dominated by the capabilities of thecontroller, the gate drive signal of QSR is appliedand the MOSFET is turned on. At that time thecurrent transfers from the body diode to thechannel of the device.
ILV
ILV
QFW
QFW
QSR
QSR
RLO,SR
RLO,SR +
+-
-
Fig. 17. Synchronous switching model.At the end of the conduction period of QSR
the MOSFET must be turned off. This procedureis initiated by removing the drive signal from thegate of the synchronous switch. This event itselfwill not cause the turn-off of the device. Instead,it will force the current to flow in the body diodeinstead of the channel. The operation of thecircuit is indifferent to this change. Current startsto shift from QSR to QFW when the gate of theforward switch transitions from low to high.Once the full load current is taken over by QFWand the body diode is fully recovered, theswitching node transitions from GND to theinput voltage level. During this transition theCRSS capacitor of QSR is charged and thesynchronous MOSFET is susceptible to dv/dtinduced turn-on.
Summarizing this unique operation of thesynchronous MOSFET and its gate drive, themost important conclusion is to recognize thatboth turn-on and turn-off dv/dt of thesynchronous MOSFET is forced on the deviceby the gate drive characteristics (i.e. theswitching speed) of the forward switch.Therefore, the two gate drive circuits should bedesigned together to ensure that their respectivespeed and dv/dt limit matches under all operatingconditions. This can be ensured by adhering tothe steps of the following simple calculations:
( )
( )
MAX(SR)ON(FW)TURN
RSS(SR)I(SR)G,GATE(SR)LO(SR)
TH(SR)
MAX(SR)
RSS(FW)I(FW)G,GATE(FW)HI(FW)
) PLATEAU(FWGS,DRV
ON(FW)TURN
dtdv
dtdv
CRRRV
dtdv
CRRRVV
dtdv
<
⋅++=
⋅++−
=
−
−
Assuming the same devices for QSR and QFW,no external gate resistors, and that the internalgate resistance is negligible compared to thedrivers output impedance, the ratio of the driveroutput impedances can be approximated by:
) PLATEAU(FWGS,DRV
TH(SR)
HI(FW)
LO(SR)
VVV
RR
−≤
A typical example with logic levelMOSFETs driven by a 10V drive signal wouldyield a ratio of 0.417, which means that the pulldown drive impedance of QSR must be less than42% of the pull up drive impedance of QFW.When carrying out these calculations, rememberthat every parameter except VDRV is temperaturedependent and their values might have to beadjusted to reflect the worst case operatingconditions of the design.
2-19
VI. HIGH SIDE NON-ISOLATED GATE DRIVES
High side non-isolated gate drive circuits canbe classified by the device type they are drivingor by the type of drive circuit involved.Accordingly, they are differentiated whether P-channel or N-channel devices are used orwhether they implement direct drive, levelshifted drive, or bootstrap technique. Which everway, the design of high side drivers need moreattention and the following checklist might beuseful to cover all aspects of the design:• Efficiency• Bias / power requirements• Speed limitations• Maximum duty-cycle limit• dv/dt implications• Start-up conditions• Transient operation• Bypass capacitor size• Layout, grounding considerations
A. High Side Drivers for P-channel DevicesIn this group of circuits the source terminal
of the P-channel MOSFET switch is connectedto the positive input rail. The driver applies anegative amplitude turn-on signal to the gatewith respect to the source of the device. Thismeans that the output of the PWM controller hasto be inverted and referenced to the positiveinput rail. Because the input voltage can beconsidered as a DC voltage source, high side P-channel drivers do not have to swing betweenlarge potential differences on the switchingfrequency basis, but they must work over theentire input voltage range. Moreover, the driveris referenced to an AC ground potential due tothe low AC impedance of the input voltagesource.
1. P-channel direct drive.The easiest case of P-channel high side
drivers is direct drive, which can be implementedif the maximum input voltage is less then thegate-to-source breakdown voltage of the device.A typical application area is 12V input DC/DCconverters using a P-channel MOSFET, similarto the schematic in Fig. 18. Note the inverted
PWM output signal is readily available in somededicated controllers for P-channel devices.
RGATE
VCC
OUT
GND
VDRV=VIN
PWMcontroller
Fig. 18. Direct drive for P-channel MOSFET.The operation of the circuit is similar to the
ground referenced direct driver for N-channeldevices. The significant difference is the path ofthe gate drive current, which never flows in theground connections. Instead, the high charge anddischarge currents of the gate are conducted bythe positive rail interconnection. Consequently,to minimize the loop inductance in the gatedrive, wide traces or a plane is desirable for thepositive input.
2. P-channel level shifted drive.For input voltages exceeding the gate-to-
source voltage limit of the MOSFET, levelshifted gate drive circuits are necessary. Thesimplest level shift technique is using an opencollector driver as shown in Fig. 19.Unfortunately, open collector level shifters arenot suitable for driving MOSFETs directly in ahigh speed application.
VCC
OUT
GND
VDRV
Driver
VIN
OC
RGATE
ROFF
Fig. 19. Open collector drive for PMOS device.
2-20
Problems are numerous with thisimplementation starting with the limited inputvoltage range due to the voltage rating of theopen collector transistor. But the most inhibitingobstacle is the high drive impedance. Bothresistors, ROFF and RGATE must be a high valueresistor to limit the continuous current in thedriver during the conduction period of theswitch. Furthermore, the gate drive amplitudedepends on the resistor divider ratio and theinput voltage level. Switching speed and dv/dtimmunity are severely limited which excludesthis circuit from switching applications.Nevertheless, this very simple level shiftinterface can be used for driving switches ininrush current limiters or similar applicationswhere speed is not an important consideration.
Fig. 20 shows a level shifted gate drivecircuit which is suitable for high speedapplications and works seamlessly with regularPWM controllers. The open collector level shiftprinciple can be easily recognized at the input ofa bipolar totem-pole driver stage. The levelshifter serves two purposes in thisimplementation; it inverts the PWM output andreferences the PWM signal to the input rail.
The turn-on speed is fast, defined by RGATEand R2. During the on-time of the switch a smallDC current flows in the level shifter keeping thedriver biased in the right state. Both the gatedrive power and the level shift current areprovided by the positive input of the power stagewhich is usually well bypassed.
VCC
OUT
GND
VBIAS
PWMcontroller
VIN
RGATE
R1
R2
QINVRB
Fig. 20. Level shifted P-channel MOSFETdriver.
The power consumption of the driver has afrequency dependent portion based on the gatecharge of the main switch and a duty-cycle andinput voltage dependent portion due to thecurrent flowing in the level shifter.
R2R1DVfVQP MAXIN
DRVDRVGDRIVE +⋅+⋅⋅=
One of the drawbacks of this circuit is thatVDRV is still a function of the input voltage dueto the R1, R2 divider. In most cases protectioncircuits might be needed to prevent excessivevoltage across the gate-to-source terminals.Another potential difficulty is the saturation ofthe npn level shift transistor, which can extendthe turn-off time otherwise defined by R1 andRGATE. Fortunately both of these shortcomingscan be addressed by moving R2 between theemitter of QINV and GND. The resulting circuitprovides constant gate drive amplitude and fast,symmetrical switching speed during turn-on andturn-off. The dv/dt immunity of the driverscheme is primarily set by the R1 resistor. Alower value resistor will improve the immunityagainst dv/dt induced turn-on but also increasesthe power losses of the level shifter. Also, noticethat this solution has a built in self-biasingmechanism during power up. While the PWMcontroller is still inactive, QINV is off and the gateof the main MOSFET is held below its thresholdby R1 and the upper npn transistor of the totem-pole driver. Pay specific attention to rapid inputvoltage transients though as they could causedv/dt induced turn-on during the off state of theP-channel MOSFET transistor.
In general, the DC level shift drivers haverelatively low efficiency and are powerdissipation limited above a certain input voltagelevel. The fundamental trade-off is to balance theswitching speed and the power consumption ofthe level shifter to meet all requirements underthe entire input voltage range.
B. High Side Direct Drivers for N-channelDevices
The majority of power supply applicationsutilize N-channel MOSFETs as the main powerswitch because of their lower price, higher speedand lower on-resistance. Using N-channeldevices as a high side switch necessitates a gate
2-21
drive circuit which is referenced to the source ofthe MOSFET. The driver must tolerate theviolent voltage swings occurring during theswitching transitions and drive the gate of theMOSFET above the positive supply rail of thepower supply. In most cases, the gate drivevoltage must be above the highest DC potentialavailable in the circuit. All these difficultiesmake the high side driver design a challengingtask.
1. High-side direct drive for N-channelMOSFET.
In the easiest high side applications theMOSFET can be driven directly by the PWMcontroller or by a ground referenced driver. Twoconditions must be met for this application:
MillerGS,DRVIN
MAXGS,DRV
VVVVV
−<<
A typical application schematic is illustratedin Fig. 21 with an optional pnp turn-off circuit.
VCC
OUT
GND
VDRV
PWMcontroller
VIN
RGATE
Optional
Fig. 21. Direct drive of N-channel MOSFET.Looking at the basic operation of the circuit –
neglect the pnp turn-off transistor for now –there are two major differences with thisconfiguration compared to the ground referenceddrive scheme. Since the drain is connected to thepositive DC input rail, the switching action takesplace at the source terminal of the device. It isstill the same clamped inductive switching withidentical turn-on and turn-off intervals. But fromgate drive design point of view this is acompletely different circuit. Notice that the gatedrive current can not return to ground at thesource terminal. Instead it must go through theload, connected to the source of the device. Indiscontinuous inductor current mode the gate
charge current must go through the outputinductor and the load. In continuous inductorcurrent mode, however, the loop can be closedthrough the conducting pn junction of therectifier diode. At turn-off, the gate dischargecurrent comes through the rectifier diodeconnected between ground and the source of theMOSFET. In all operating modes, both thecharge and discharge currents of the CGDcapacitor flow through the high frequencybypass capacitor of the power stage.
The net result of all these differences is theincreased parasitic source inductance due tomore components and larger loop area involvedin the gate drive circuitry. As presented earlier,the source inductance has a negative feedbackeffect on the gate drive and slows down theswitching actions in the circuit.
The other significant difference in high sidedirect drive is the behavior of the source – theswitching node of the circuit. Paying closeattention to the source waveform of theMOSFET during turn-off, a large negativevoltage can be observed. Fig. 22 illustrates thisrather complex switching action.
As the turn-off is initiated by pulling the gateterminal toward ground, the input capacitancesof the MOSFET are quickly discharged to theMiller plateau voltage. The device is still fullyon, the entire load current is flowing through thedrain to the source and the voltage drop is small.Next, in the Miller region, the MOSFET worksas a source follower.
The source falls together with the gate, andwhile the voltage across the drain-to-sourceincreases, the gate-to-source voltage remainsconstant at the VGS,Miller level. The dv/dt islimited by the gate drive impedance and the CGDcapacitor of the device. Once the source falls0.7V or so below ground, the rectifier diode issupposed to clamp the switching node to ground.
Actually, the source can fall way belowground for a short period of time until therectifier diode gets through its forward recoveryprocess and the current overcomes the effect ofthe parasitic inductances. After the load currentis completely transferred from the MOSFET to
2-22
VIN
RGATE
LS
LD
VOUT
2
-VGS=
VDRV
VIN+VGS,Miller
VIN
FWD recovery &Current transfer
1
3
1
2
3
2 3
Fig. 22. Turn-off of high side N-channelMOSFET.the diode, the switching node can return to itsfinal voltage, a diode drop below ground.
This negative excursion of the source voltagerepresents a significant problem for the gatedrive circuit. Slow diodes, high parasiticinductance values can cause excessive negativevoltage at the source of the MOSFET, and canpull the output pin of the driver below ground.
To protect the driver, a low forward voltage dropSchottky diode might be connected between theoutput pin and ground as indicated in Fig. 21.Another aspect to consider is when the gateterminal reaches 0V, the gate discharge currentwould become zero. Further negative pull on thegate terminal and the MOSFET starts turningback on. Ultimately the system finds a verydelicate equilibrium where the gate dischargecurrent and the voltage drop across the parasiticinductances result the same di/dt in the devicecurrent.
Even the optional turn-off speed-up circuitshown in Fig. 21 can not help during thenegative voltage spike of the switching junction.The pnp transistor will turn-off when the gatefalls to a VBE above ground and the MOSFET isleft on its own during the negative voltagetransient. Also, pay attention to the reducednoise tolerance during the off state of the mainswitch. The source is several hundred millivoltsbelow ground and the gate is held atapproximately 0.7V above ground. This positivevoltage across the gate with respect to the sourceis dangerously close to the threshold voltageespecially for logic level devices and at elevatedtemperatures.
C. Bootstrap Gate Drive TechniqueWhere input voltage levels prohibit the use
of direct gate drive circuits for high side N-channel MOSFETs, the principle of bootstrapgate drive technique can be considered. Thismethod utilizes a gate drive and accompanyingbias circuit, both referenced to the source of themain MOSFET transistor. Both the driver andthe bias circuit swing between the two inputvoltage rails together with the source of thedevice. However, the driver and its floating biascan be implemented by low voltage circuitelements since the input voltage is never appliedacross their components. The driver and theground referenced control signal are linked by alevel shift circuit which must tolerate the highvoltage difference and considerable capacitiveswitching currents between the floating high sideand ground referenced low side circuits.
2-23
1. Discrete high performance floating driver.A typical implementation representing the
bootstrap principle is displayed in Fig. 23. Theground referenced PWM controller or MOSFETdriver is represented by its local bypass capacitorand the output pin. The basic building blocks ofthe bootstrap gate drive circuit can be easilyrecognized. The level-shift circuit is comprisedof the bootstrap diode QBST, R1, R2 and the levelshift transistor, QLS. The bootstrap capacitor,CBST, a totem-pole bipolar driver and the usualgate resistor are the floating, source referencedpart of the bootstrap solution.
This particular implementation can be usedvery effectively in 12V to approximately 24Vsystems with simple low cost PWM controllerswhich have no floating driver on board. It isbeneficial that the IC voltage rating does notlimit the input voltage level. Furthermore, thelevel shift circuit is a source switched small NMOStransistor which does not draw any currentduring the on time of the main MOSFET fromthe bootstrap capacitor. It is an important featureto maintain high efficiency in the level shifter,and to extend the maximum on-time of the mainswitch. The operation can be summarized as
follows: when the PWM output goes high to turnon the main MOSFET, the level shift transistorturns off. R1 supports the base current to theupper npn transistor in the totem-pole driver andthe main MOSFET turns on. The gate charge istaken from the bootstrap capacitor, CBST. As theswitch turns on, its source swings to the positiveinput rail. The bootstrap diode and transistorblock the input voltage and power to the driver isprovided from the bootstrap capacitor. At turn-off, the PWM output goes low turning on thelevel shift transistor.
Current starts to flow in R1 and R2 towardsground and the lower pnp transistor of the totem-pole driver turns on. As the gate of the mainMOSFET discharges, the drain-to-source voltageincreases and the source transitions to ground,allowing the rectifier to turn-on. During the offtime of the main switch, the bootstrap capacitoris recharged to the VDRV level through thebootstrap diode. This current is supplied by theCDRV bypass capacitor of the ground referencedcircuitry and it goes through DBST, CBST, and theconducting rectifier component. This is the basicoperating principle of the bootstrap technique.
VCC
OUT
GND
VDRV
PWMcontroller
VIN
RGATE
VOUT
DBST
CBSTQLS
Fig. 23. Integrated bootstrap driver.
2-24
2. Integrated bootstrap drivers.In medium input voltage applications, mainly
24V or 48V telecom systems, most of thebootstrap components can be integrated into thePWM controller as illustrated in Fig. 24.
VCC
OUT
GND
PWM controller
VIN
RGATE
VDRV
SRC
VBST
Leve
l-Shi
ft
DBST
CBST
Fig. 24. Integrated bootstrap driver.For even higher voltages, dedicated driver
ICs are available to ease the design of bootstrapgate drive with up to 600V rating. These highvoltage ICs are differentiated by their uniquelevel shift design. In order to maintain highefficiency and manageable power dissipation, thelevel shifters should not draw any current duringthe on-time of the main switch. Even a modest1mA current in the level shift transistors mightresult in close to 0.5W worst case powerdissipation in the driver IC.
A widely used technique for theseapplications is called pulsed latch leveltranslators and they are revealed in Fig. 25.
Q
Q
R
S
VBST
OUTH
SRC
PulseFilter
PWM
Fig. 25. Typical level shifter in high voltagedriver IC.
As indicated in the drawing, the PWM inputsignal is translated to ON/OFF commands. Theshort pulses generated at the rising and falling
edges drive the level shift transistor pair whichinterfaces with the high side circuitry.Accordingly, the floating portion of the driver ismodified as well, the level shifted commandsignals have to be differentiated from noise andmust be latched for proper action. This operationresults in lower power dissipation because of theshort duration of the current in the level shifterbut lowers noise immunity since the commandsignal is not present at the input of the drivercontinuously. The typical pulse width in a 600Vrated pulsed latch level translator is around 120nanoseconds. This time interval adds to naturaldelays in the driver and shows up as turn-on andturn-off delays in the operation and is indicatedin the data sheet of the drivers. Due to the longerthan optimum delays, the operating frequencyrange of the high voltage gate driver ICs islimited below a couple of hundreds of kHz.
Some lower voltage high side driver ICs (upto 100V) use continuous current DC level shiftcircuits to eliminate the delay of the pulsediscriminator, therefore they support higheroperating frequency.
3. Bootstrap switching action.Bootstrap gate drive circuits are used with
high side N-channel MOSFET transistors asshown in Fig. 26. The switching transitions ofthe high side switch were explored previouslywith respect to the high side N-channel directdrive scheme and are equally applicable withbootstrap drivers.
The biggest difficulty with this circuit is thenegative voltage present at the source of thedevice during turn-off. As shown previously, theamplitude of the negative voltage is proportionalto the parasitic inductance connecting the sourceof the main MOSFET to ground (including theparasitic inductance associated with the rectifier)and the turn-off speed (di/dt) of the device asdetermined primarily by the gate drive resistor,RGATE and input capacitor, CISS. This negativevoltage can be serious trouble for the driver’soutput stage since it directly affects the sourcepin – often called SRC or VS pin – of the driveror PWM IC and might pull some of the internalcircuitry significantly below ground.
2-25
VIN
RGATE
VCC
OUT
GNDHigh Side
Driver
VS
VB
Leve
l-Shi
ft
IN
VCC
OUT
GND
VDRV
PWMcontroller
Negativevoltage
transient
CBST
DBST
CDRV
Fig. 26. High voltage driver IC for bootstrap gate drive.The other problem caused by the negative
voltage transient is the possibility to develop anover voltage across the bootstrap capacitor.Capacitor CBST will be peak charged by DBSTfrom CDRV. Since CDRV is referenced to ground,the maximum voltage which can build on thebootstrap capacitor is the sum of VDRV and theamplitude of the negative voltage at the sourceterminal. A small resistor in series with thebootstrap diode can mitigate the problem.Unfortunately, the series resistor does not providea foolproof solution against an over voltage and italso slows down the recharge process of thebootstrap capacitor.
A circuit to deliver very effective protectionfor the SRC pin is given in Fig. 27. It involvesrelocating the gate resistor from the gate to thesource lead between the driver and the mainMOSFET and adding a small, low forwardvoltage drop Schottky diode from ground to theSRC pin of the driver.
In this circuit, RGATE has a double purpose; itsets the turn-on and turn-off speed in theMOSFET and also provides current limiting forthe Schottky diode during the negative voltagetransient of the source terminal of the mainswitch. Now, the switching node can swingseveral volts below ground without disturbing theoperation of the driver. In addition, the bootstrapcapacitor is protected against over voltage by thetwo diodes connected to the two ends of CBST.
VCC
OUT
GND
PWM controlleror driver output
VIN
RGATE
VDRV
SRC
VBST
Leve
l-Shi
ft CBST
DBST
Fig. 27. Protecting the SRC pin.The only potential hazard presented by this
circuit is that the charge current of the bootstrapcapacitor must go through RGATE. The timeconstant of CBST and RGATE slows the rechargeprocess which might be a limiting factor as thePWM duty ratio approaches unity.
4. Bootstrap biasing, transient issues and start-up.
Fig. 28 shows a typical application diagramof the bootstrap gate drive technique. There arefour important bypass capacitors marked on theschematic The bootstrap capacitor, CBST is themost important component from the design pointof view, since it has to filter the high peak currentcharging the gate of the main MOSFET whileproviding bias for the source referenced floatingcircuitry. In every switching cycle during normaloperation, the bootstrap capacitor provides the
2-26
total gate charge (QG) to turn-on the MOSFET,the reverse recovery charge (QRR) and leakagecurrent of the bootstrap diode (ILK,D), thequiescent current of the level shifter (IQ,LS) andthe gate driver (IQ,DRV), and the leakage currentbetween the gate-source terminals (IGS),including the current drawn by a potential gate-to-source pull down resistor. Some of thesecurrents flow only during the on-time of the mainswitch and some of them might be zerodepending on the actual implementation of thedriver and level shifter.
Assuming steady state operation, thefollowing general equation can be used tocalculate the bootstrap capacitor value to achievethe targeted ripple voltage, ∆VBST:
BST
DRV
MAXBSTRRG
BST ∆VfDIQQ
C⋅++
=
whereGSDRVQ,LSQ,DLK,BST IIIII +++=
To finalize the bootstrap capacitor value, twoextreme operating conditions must be checked aswell. During load transients it might be necessaryto keep the main switch on or off for severalswitching cycles. In order to ensure uninterruptedoperation under these circumstances, the CBSTcapacitor must store enough energy to hold thefloating bias voltage above the under voltagelockout threshold of the high side driver IC for anextended period of time.
Going from light load to heavy load, certaincontrollers can keep the main switch oncontinuously until the output inductor currentreaches the load current value. The maximum ontime (tON,MAX) is usually defined by the value andthe voltage differential across the output inductor.For these cases, a minimum bootstrap capacitorvalue can be established as:
UVLOBST
MAXON,BSTRRGMINBST, VV
tIQQC
−⋅++
=
where VBST is the initial value of the bootstrapbias voltage across CBST and VUVLO is the undervoltage lockout threshold of the driver. With adiscrete floating driver implementation, VUVLOcould be substituted by the minimum safe gatedrive voltage.
Any load transient in the other direction willrequire pulse skipping when the MOSFET staysoff for several switching cycles. When the outputinductor current reaches zero, the source of themain switch will settle at the output voltage level.The bootstrap capacitor must supply all the usualdischarge current components and store enoughenergy to be able to turn-on the switch at the endof the idle period. Similar to the previoustransient mode, a minimum capacitor value canbe calculated as:
( )UVLOBST
MAXOFF,DRVQ,LSQ,DLK,GMINBST, VV
tIIIQC
−⋅+++
=
VIN
RGATE
High SideDriver
VCC
OUT
GND
VBIAS
PWMcontroller
VOUT
CBSTCDRV
IN
VCC
GND
VS
OUT
VB
CBIAS
DBST
VDRV
CIN
COUT
Fig. 28. Bootstrap bypassing example.
2-27
VCC
OUT
GND
VBIAS
PWMcontroller
VIN
RGATEBattery
RSTART
High SideDriver
IN
VCC
GND
VS
OUT
VB
DSTART
DZCBST
DBST
Fig. 29. Bootstrap start-up circuit.In certain applications, like in battery
chargers, the output voltage might be presentbefore input power is applied to the converter. Inthese cases, the source of the main MOSFET andthe negative node of CBST are sitting at the outputvoltage and the bootstrap diode might be reversebiased at start-up. Delivering the initial charge tothe bootstrap capacitor might not be possibledepending on the potential difference betweenthe bias and output voltage levels.Assuming there is enough voltage differentialbetween the input and output voltages, a simplecircuit comprised of RSTART resistor, DSTARTdiode, and DZ zener diode can solve the start-upproblem as shown in Fig. 29.
In this start-up circuit, DSTART serves as asecond bootstrap diode used for charging thebootstrap capacitor at power up. CBST will becharged to the zener voltage of DZ which issupposed to be higher than the driver’s biasvoltage during normal operation. The chargecurrent of the bootstrap capacitor and the zenercurrent are limited by the start-up resistor. Forbest efficiency the value of RSTART should beselected to limit the current to a low value sincethe second bootstrap path through the start-updiode is permanently in the circuit.
5. Grounding considerations.There are three important grounding issues
which have to be addressed with respect to theoptimum layout design of the bootstrap gatedrivers with high side N-channel MOSFETs. Fig.28 can be used to identify the most critical highcurrent loops in a typical application.
The first focus is to confine the high peakcurrents of the gate in a minimal physical area.Considering the path the gate current must passthrough, it might be a challenging task. At turn-on, the path involves the bootstrap capacitor, theturn-on transistor of the driver, the gate resistor,the gate terminal, and finally, the loop is closedat the source of the main MOSFET where CBSTis referenced. The turn-off procedure is morecomplicated as the gate current has two separatecomponents. The discharge current of the CGScapacitor is well localized, it flows through thegate resistor, the turn-off transistor of the driverand from the source to the gate of the powerMOSFET. On the other hand, the CGDcapacitor’s current must go through RGATE, theturn-off transistor of the driver, the output filter,and finally the input capacitor of the power stage(CIN). All three loops carrying the gate drivecurrents have to be minimized on the printedcircuit board.
The second high current path includes thebootstrap capacitor, the bootstrap diode, the localground referenced bypass capacitor of the driver,and the rectifier diode or transistor of the powerstage. CBST is recharged on the cycle-by-cyclebasis through the bootstrap diode from theground referenced driver capacitor, CDRV,connected from the anode of DBST to ground. Therecharge happens in a short time interval andinvolves high peak current. Therefore, the highside driver must be bypassed locally on its inputside as well. According to the rule-of-thumb,CDRV should be an order of magnitude larger
2-28
than CBST. Minimizing this loop area on theprinted circuit board is equally important toensure reliable operation.
The third issue with the circuit is to containthe parasitic capacitive currents flowing betweenpower ground and the floating circuitry in a lowimpedance loop. The goal is to steer thesecurrents away from the ground of the sensitiveanalog control parts. Fig. 30 reveals the parasiticcapacitive current paths in two representativeapplications with high side driver ICs.
Single high side driver ICs usually have onlyone GND connection. Since the capacitivecurrents must return to the ground potential ofthe power stage, the low side portion of the ICshould be referenced to power ground. This iscounterintuitive, since the control signal of thedriver is referenced to signal ground.Nevertheless, eliminating the high capacitivecurrent component between analog and powerground will also ensure that the potentialdifference between the two grounds areminimized.
VCC
OUT
GNDHigh SideDriver
VS
VBLe
vel-S
hift
IN
VBIAS
VCC
OUT
GND
PWMcontroller
VIN
RGATE
VCC
HO
GND
Half BridgeDriver
VS
VB
Leve
l-Shi
ft
HI
VBIAS
VCC
OUT1
GND
PWMcontroller
VIN
RGATE
COM
LOLIOUT2
Fig. 30. Capacitive currents in high side applications.
2-29
The situation is greatly improved withgeneral purpose half bridge driver ICs whichcontain one low side and one high side driver inthe same package. These circuits have twoground connections usually labeled as GND andCOM, providing more flexibility in layout. Toreturn the capacitive currents to power ground inthe shortest possible route, the COM pin isconnected to power ground. The GND pin can beutilized to provide connection to the signalground of the controller to achieve maximumnoise immunity.
For completeness, the bypass capacitor of thePWM controller should be mentioned as well,which is placed near to the VCC and GND pinsof the IC. Referring to Fig. 28 again, CBIAS is arelatively small capacitor with respect to CBSTand CDRV since it provides only high frequencybypassing and it is not involved in the gate driveprocess.
VII. AC COUPLED GATE DRIVE CIRCUITS
AC coupling in the gate drive path provides asimple level shift for the gate drive signal. Theprimary purpose of AC coupling is to modify theturn-on and turn-off gate voltages of the mainMOSFET as opposed to high side gate driveswhere the key interest is to bridge large potentialdifferences. In a ground referenced example likethe one in Fig. 31, the gate is driven between-VCL and VDRV-VCL levels instead of the originaloutput voltage levels of the driver, 0V and VDRV.The voltage, VCL is determined by the diodeclamp network and it is developed across thecoupling capacitor. The benefit of this techniqueis a simple way to provide negative bias for thegate at turn-off and during the off state of theswitch to improve the turn-off speed and thedv/dt immunity of the MOSFET. The trade-off isslightly reduced turn-on speed and potentiallyhigher RDS(on) resistance because of the lowerpositive drive voltage.
The fundamental components of AC couplingare the coupling capacitor CC and the gate-to-source load resistor RGS.
The resistor plays a crucial role during powerup, pulling the gate low. This is the onlymechanism keeping the MOSFET off at start updue to the blocking effect of the coupling
capacitor between the output of the driver and thegate of the device. In addition, RGS provides apath for a current across the coupling capacitor.
RGS
VCC
OUT
GND
VDRV
PWMcontroller
CC
+VDRV VDRV-VCL
0V -VCL
-VCLIC,AVE=0
Fig. 31. Capacitively coupled MOSFET gatedrive.
Without this current component the voltagewould not be allowed to build across CC.Theoretically, in every switching cycle the sameamount of total gate charge would be deliveredthen removed through the capacitor and the netcharge passing through CC would be zero.
The same concept can be applied for steadystate operation to determine the DC voltageacross the coupling capacitor with RGS in thecircuit. Assuming no clamp circuitry, a constantVC voltage across the capacitor, and a constantduty cycle D, the current of RGS can berepresented as an additional charge componentpassing through CC. Accordingly, the total chargedelivered through the coupling capacitor duringturn-on and consecutive on-time of the MOSFETis:
DRVGS
CDRVGONC, f
DR
VVQQ ⋅−+=
Following the same considerations for theturn-off and successive off-time of the switch, thetotal charge can be calculated as:
DRVGS
CGOFFC, f
D1RVQQ −⋅+=
For steady state operation, the two chargesmust be equal.
Solving the equations for VC determines thevoltage across the coupling capacitor:
DVV DRVC ⋅=
2-30
This well known relationship highlights theduty ratio dependency of the coupling capacitorvoltage. As duty cycle varies, VC is changing andthe turn-on and turn-off voltages of the MOSFETadjust accordingly. As Fig. 32 exemplifies, at lowduty cycles the negative bias during turn-off isreduced, while at large duty ratios the turn-onvoltage becomes insufficient.
The inadequate turn-on voltage at large dutyratios can be resolved by using a clamp circuitconnected in parallel to RGS as shown in Fig. 31.Its effect on the coupling capacitor voltage is alsoshown in Fig. 32. As the coupling-capacitorvoltage is limited by the clamp, the maximumnegative bias voltage of the gate is determined.Since the gate drive amplitude is not effected bythe AC coupling circuit, a minimum turn-onvoltage can be guaranteed for the entire dutycycle range.
Nor
mal
ized
Ste
ady
Stat
e D
CVo
ltage
(VC/V
DR
V) A
cros
s C
C
Duty Ratio
0.2
0.4
0.6
0.8
1
0.20 10
0.4 0.6 0.8
Zener ClampVCL
VDRV
Fig. 32. Normalized coupling capacitor voltageas a function of duty ratio.
A. Calculating the Coupling CapacitorThe amount of charge going through CC in
every switching cycle causes an AC ripple acrossthe coupling capacitor on the switchingfrequency basis. Obviously, this voltage changeshould be kept relatively small compared to theamplitude of the drive voltage.
The ripple voltage can be calculated based onthe charge defined previously as:
( )DRVGSC
CDRV
C
GC fRC
DVVCQ∆V
⋅⋅⋅−+=
Taking into account that Vc=D⋅VDRV, theequation can be rearranged to yield the desiredcapacitor value as well:
( )DRVGSC
DRV
C
GC fR∆V
DD1V∆VQC
⋅⋅⋅−⋅+=
The expression reveals a maximum at D=0.5.A good rule of thumb is to limit the worst caseAC ripple amplitude (∆Vc) to approximately10% of VDRV.
B. Start up Transient of the Coupling CapacitorBefore the desired minimum coupling
capacitor value could be calculated, one moreparameter must be defined. The value of RGS hasto be selected. In order to make an intelligentdecision the start up transient of the AC couplingcircuit must be examined.
At power up, the initial voltage across CC iszero. As the output of the driver start switchingthe DC voltage across the coupling capacitorbuilds up gradually until it reaches its steady statevalue, VC. The duration to develop VC across CCdepends on the time constant defined by CC andRGS. Therefore, to achieve a target start-uptransient time and a certain ripple voltage of thecoupling capacitor at the same time, the twoparameters must be calculated together.Fortunately, there are two equations for twounknowns:
( )
CGSCGS
DRVGSC
DRV
C
GC
CRCR
fR∆VDD1V
∆VQC
ττ =→⋅=
⋅⋅⋅−⋅+=
which will yield a single solution. Substitutingthe expression for RGS from the second equation,D=0.5 for worst case condition and targeting∆Vc=0.1⋅VDRV, the first equation can be solvedand simplified for a minimum capacitor value:
( )5f2VfQ20CDRVDRV
DRVGMINC, τ
τ−⋅⋅⋅
⋅⋅⋅=
Once CC,MIN is calculated, its value and thedesired start-up time constant (τ) defines therequired pull down resistance. A typical designtrade-off for AC coupled drives is to balance
2-31
efficiency and transient time constant. Forquicker adjustment of the coupling capacitorvoltage under varying duty ratios, higher currentmust be allowed in the gate-to-source resistor.
VIII. TRANSFORMER COUPLED GATE DRIVES
Before the appearance of high voltage gatedrive ICs, using a gate drive transformer was theonly viable solution to drive high side switches inoff-line or similar high voltage circuits. The twosolutions coexist today, both have their pros andcons serving different applications. Theintegrated high side drivers are convenient, usesmaller circuit board area but have significantturn-on and turn-off delays. The properlydesigned transformer coupled solution hasnegligible delays and it can operate across higherpotential differences. Usually it takes morecomponents and requires the design of atransformer or at least the understanding of itsoperation and specification.
Before concentrating on the gate drivecircuits, some common issues pertinent to alltransformer designs and their correlation to gatedrive transformers will be reviewed.• Transformers have at least two windings. The
use of separate primary and secondarywindings facilitates isolation. The turns ratiobetween primary and secondary allowsvoltage scaling. In the gate drive transformer,voltage scaling is usually not required, butisolation is an important feature.
• Ideally the transformer stores no energy, thereis no exemption. The so called flyback“transformer” really is coupled inductors.Nevertheless, small amounts of energy arestored in real transformers in the non-magnetic regions between the windings andin small air gaps where the core halves cometogether. This energy storage is representedby the leakage and magnetizing inductance.In power transformers, reducing the leakageinductance is important to minimize energystorage thus to maintain high efficiency. Thegate drive transformer handles very lowaverage power, but it delivers high peakcurrents at turn-on and turn-off. To avoidtime delays in the gate drive path, lowleakage inductance is still imperative.
• Faraday’s law requires that the averagevoltage across the transformer winding mustbe zero over a period of time. Even a smallDC component can cause flux “walk” andeventual core saturation. This rule will have asubstantial impact on the design oftransformer coupled gate drives controlledby single ended PWM circuits.
• Core saturation limits the applied volt-secondproduct across the windings. The transformerdesign must anticipate the maximum volt-second product under all operating conditionswhich must include worst case transients withmaximum duty ratio and maximum inputvoltage at the same time. The only relaxationfor gate drive transformer design is theirregulated supply voltage.
• A significant portion of the switching periodmight be reserved to reset the core of themain power transformer in single endedapplications, (working only in the firstquadrant of the B-H plane) such as theforward converter. The reset time intervallimits the operating duty ratio of thetransformer. This is rarely an issue even insingle ended gate drive transformer designsbecause they must be AC coupled thus theyoperate with bi-directional magnetization.
A. Single-Ended Transformer Coupled GateDrive Circuits
These gate drive circuits are used inconjunction with a single output PWM controllerto drive a high side switch. Fig. 33 shows thebasic circuit.
VCC
OUT
GND
VDRV
PWMcontroller
+VDRV
0V VC+ -
+VDRV-VC
-VC
RGS
RC CC
Fig. 33. Single ended transformer coupled gatedrive.
2-32
The coupling capacitor must be placed inseries with the primary winding of the gate drivetransformer to provide the reset voltage for themagnetizing inductance. Without the capacitorthere would be a duty ratio dependent DC voltageacross the winding and the transformer wouldsaturate.
The DC voltage (VC) of CC develops thesame way as shown in AC coupled direct drives.The steady state value of the coupling capacitorvoltage is:
DRVC VDV ⋅=Similar to AC coupled direct drives, the
actual gate drive voltage, VC, changes with dutyratio. In addition, sudden changes in duty ratiowill excite the L-C resonant tank formed by themagnetizing inductance of the gate drivetransformer and the coupling capacitor. In mostcases this L-C resonance can be damped byinserting a low value resistor (RC) in series withCC. The value of RC is determined by thecharacteristic impedance of the resonant circuitand given as:
C
MC C
L2R ⋅≥
Keep in mind that the RC value defined in theequation above is the equivalent series resistancewhich includes the output impedance of thePWM driver. Additionally, consider that acritically damped response in the couplingcapacitor voltage might require unreasonablehigh resistor value. This would limit the gatecurrent, consequently the switching speed of themain switch. On the other hand, underdampedresponse may result in unacceptable voltagestress across the gate source terminals during theresonance.
The current building VC has two components;the magnetizing current of the transformer andthe current flowing in the pull down resistorconnected between the gate and the source of themain MOSFET. Accordingly, the start-up andtransient time constant governing the adjustspeed of the coupling capacitor voltage reflectsthe effect of the magnetizing inductance of thegate drive transformer and can be estimated by:
GSMDRV
CGSMDRV
RLfπ2CRLf2 πτ
+⋅⋅⋅⋅⋅⋅⋅⋅=
The magnetizing inductance has anothersignificant effect on the net current of the driver,and on its direction. Fig. 34 highlights thedifferent current components flowing in thecircuit and the sum of the current components,IOUT, which has to be provided by the driver.
VOUT
VT
IMIR
IG
IOUT
Fig. 34. Driver output current with transformercoupled gate drive.
Note the gray shaded area in the outputcurrent waveform. The output driver is in its lowstate which means it is supposed to sink current.But because of the magnetizing currentcomponent, the driver actually sources current.Therefore, the output must handle bi-directionalcurrent with transformer coupled gate drives.This might require additional diodes if the driveris not capable of carrying current in bothdirections. Bipolar MOSFET drivers are a typicalexample where a Schottky diode has to beconnected between the ground and the output pin.Similar situation can occur during the high stateof the driver at different duty cycle or currentcomponent values. One easy remedy to solve thisproblem and avoid the diodes on the driver’soutput is to increase the resistive currentcomponent to offset the effect of the magnetizingcurrent.
2-33
At wide duty cycles, like in the buckconverter, the circuit of Fig. 33 does not provideadequate gate drive voltage. The couplingcapacitor voltage increases proportionally to theduty ratio. Accordingly, the negative bias duringoff-time increases as well and the turn-on voltagedecreases. Adding two small components on thesecondary side of the gate drive transformer canprevent this situation.
Fig. 35 shows a commonly used technique torestore the original voltage levels of the gatedrive pulse.
VCC
OUT
GND
VDRV
PWMcontroller
+VDRV
0V
+VDRV-VD
-VDVC+ - + -
+VDRV-VC
-VC
VC-VD
RC CC1RGS
CC2DC2
Fig. 35. DC restore circuit in transformercoupled gate drive.
Here, a second coupling capacitor (CC2) and asimple diode clamp (DC2) are used to restore theoriginal gate drive amplitude on the secondaryside of the transformer. If a larger negative bias isdesired during the off time of the main switch, aZener diode can be added in series with the diodein a similar fashion as it is shown in Fig. 31, withrespect to the AC coupled direct drive solution.
1. Calculating the coupling capacitors.The method to calculate the coupling
capacitor values is based on the maximumallowable ripple voltage and the amount ofcharge passing through the capacitor in steadystate operation was described in the previous ACcoupled circuits. The equation for CC2 is similarto the one identified for direct coupled gate drivecircuit. The ripple has two components; one isrelated to the total gate charge of the mainMOSFET and a second component due to thecurrent flowing in the gate pull down resistor:
( )DRVGSC2
MAXFWDC2,DRV
C2
GC2 fR∆V
DVV∆VQC
⋅⋅⋅−
+=
This expression has a maximum at themaximum on-time of the switch, i.e. at maximumduty ratio.
In the primary side coupling capacitor themagnetizing current of the gate drive transformergenerates an additional ripple component. Itseffect is reflected in equation (A) below whichcan be used to calculate the primary sidecoupling capacitor value.
The minimum capacitance to guarantee tostay below the targeted ripple voltage under alloperating conditions can be found by determiningthe maximum of the above expression.Unfortunately the maximum occurs at differentduty ratios depending on the actual designparameters and component values. In themajority of practical solutions it falls betweenD=0.6 and D=0.8 range.
Also note that the sum of the ripple voltages,∆VC1+∆VC2 appears at the gate terminal of themain MOSFET transistor. When aiming for aparticular ripple voltage or droop at the gateterminal, it has to be split between the twocoupling capacitors.
2. Gate drive transformer design.The function of the gate drive transformer is
to transmit the ground referenced gate drive pulseacross large potential differences toaccommodate floating drive implementations.Like all transformers, it can be used toincorporate voltage scaling, although it is rarelyrequired. It handles low power but high peakcurrents to drive the gate of a power MOSFET.The gate drive transformer is driven by a variablepulse width as a function of the PWM duty ratioand either constant or variable amplitudedepending on the circuit configuration.
In the single ended circuits the gate drivetransformer is AC coupled and the magnetizinginductance sees a variable amplitude pulse. Thedouble ended arrangements, such as half-bridgeapplications, drive the gate drive transformer
( ) ( )2DRVMC1
32DRV
DRVGSC1
FWDC2,DRV
C1
GC1 fL4∆V
DDVfR∆V
DVV∆VQC
⋅⋅⋅−⋅+
⋅⋅⋅−
+= (A)
2-34
with a constant amplitude signal. In all cases, thegate drive transformers are operated in both, thefirst and third quadrant of the B-H plane.
The gate drive transformer design is verysimilar to a power transformer design. The turnsratio is usually one, and the temperature rise dueto power dissipation is usually negligible.Accordingly, the design can be started with thecore selection. Typical core shapes for gate drivetransformer include toroidal , RM, P or similarcores. The core material is high permeabilityferrite to maximize the magnetizing inductancevalue, consequently lower the magnetizingcurrent. Seasoned designers can pick the coresize from experience or it can be determinedbased on the area product estimation in the sameway as it is required in power transformer design.Once the core is selected, the number of turns ofthe primary winding can be calculated by thefollowing equation:
e
TRP A∆B
tVN
⋅⋅
=
where VTR is the voltage across the primarywinding, t is the duration of the pulse, ∆B is thepeak-to-peak flux change during t, and Ae is theequivalent cross section of the selected core.
The first task is to find the maximum volt-second product in the numerator. Fig. 36 showsthe normalized volt-second product for bothsingle ended and double ended gate drivetransformers as the function of the converter dutycycle.
For an AC coupled circuit, the worst case isat D=0.5 while direct coupling reaches the peakvolt-second value at the maximum operating dutyratio. Interestingly, the AC coupling reduces themaximum steady state volt-second product by afactor of four because at large duty ratios thetransformer voltage is proportionally reduced dueto the voltage developing across the couplingcapacitor.
It is much more difficult to figure out ∆B inthe Np equation. The reason is flux walkingduring transient operation. When the inputvoltage or the load are changing rapidly, the dutyratio is adjusted accordingly by the PWMcontroller. Deducing exact quantitative result for
the flux walk is rather difficult. It depends on thecontrol loop response and the time constant of thecoupling network when it is present. Generally,slower loop response and a faster time constanthave a tendency to reduce flux walking. A threeto one margin between saturation flux densityand peak flux value under worst case steady stateoperation is desirable for most designs to covertransient operation.
0 0.2 0.4 0.6 0.8 1
1
0.2
0.4
0.6
0.8
0
AC coupled(single ended)
DC coupled(double ended)
Duty RatioN
orm
aliz
ed V
·s P
rodu
ctV D
RV·
T DR
V
V TR· t
Fig. 36. Gate drive transformer volt-secondproduct vs. duty ratio.
The next step is to arrange the windings in theavailable window area of the core. As mentionedbefore, the leakage inductance should beminimized to avoid time delay across thetransformer, and the AC wire resistance must bekept under control. On toroidal cores, thewindings should be wound bifilar or trifilardepending on the number of windings in the gatedrive transformer. With pot cores, each windingshould be kept in a single layer. The primaryshould be the closest to the center post, followedby the low side winding, if used, and the highside winding should be the farthest from thecenter post. This arrangement in pot coresprovides an acceptable leakage inductance andthe lowest AC winding resistance. Furthermore,natural shielding of the control (primary) windingagainst capacitive currents flowing between thefloating components and power ground isprovided by the low side winding which isusually connected to the power ground directly.
2-35
VCC
OUT
GND
VDRV
PWMcontroller
+VDRV
0V
VC
+ - + -
+VDRV-VC
-VC
VC-VD
+VDRV-2 VD
Fig. 37. Power and control transmission with one transformer.
VCC
PWM
VDRV
Low Side IC +VDRV-2 VD
High Side IC
AM
OSC
Fig. 38. Power and control transmission with one transformer.
3. Dual duty transformer coupled circuits.There are high side switching applications
where the low output impedance and shortpropagation delays of a high speed gate drive ICare essential. Fig. 37 and Fig. 38 show twofundamentally different solutions to providepower as well as control to regular low voltagegate drive ICs in a floating application usingonly one transformer.
The circuit of Fig. 37 uses the switchingfrequency to carry the control signal and thepower for the driver. The operation is rathersimple. During the on-time of the main switch,the positive voltage on the secondary side of the
transformer is peak rectified to generate thesupply voltage for the gate drive IC. Since thepower is generated from the gate drive pulses,the first few drive pulses must charge the biascapacitor. Therefore, it is desirable that the driverIC chosen for this application has an undervoltage lock out feature to avoid operation withinsufficient gate voltage. As it is shown in thecircuit diagram, the DC restoration circuit (CC2and DC2) must be used to generate a bias voltagefor the driver which is independent of theoperating duty ratio. DC2 also protects the inputof the driver against the negative reset voltage ofthe transformer secondary winding. The
2-36
transformer design for this circuit is basicallyidentical to any other gate drive transformerdesign. The power level is just slightly increasedby the power consumption of the driver IC,which is relatively small compared to the powerloss associated by the total gate charge of theMOSFET. The transformer carries a high peakcurrent but this current charges the bypasscapacitor, not the input capacitance of theMOSFET. All gate current is contained locallybetween the main transistor, driver IC andbypass capacitor.
Another similar solution to transfer powerand control signal with the same transformer isshown in Fig. 38. The difference between thetwo circuits in Figs. 37 and 38 is the operatingfrequency of the transformer. Thisimplementation utilizes a dedicated chip pair.The high frequency carrier signal(fCARRIER>>fDRV) is used to power transfer, whileamplitude modulation transmits the controlcommand. The basic blocks of the gate driveschematic in Fig. 38 can be integrated into twointegrated circuits allowing efficient utilizationof circuit board area. Because of the highfrequency operation, the transformer size can bereduced compared to traditional gate drivetransformers. Another benefit of this solution isthat the bias voltage of the floating driver can beestablished independently of the gate drivecommands, thus the driver can react without thestart-up delay discussed in the previous solution.
B. Double-Ended Transformer Coupled GateDrives
In high power half-bridge and full-bridgeconverters, the need arises to drive two or moreMOSFETs usually controlled by a push-pull oralso called double-ended PWM controller. Asimplified schematic of such gate drive circuit isillustrated in Fig. 39.
In these applications a dual polaritysymmetrical gate drive voltage is readilyavailable. In the first clock cycle, OUTA is on,forcing a positive voltage across the primarywinding of the gate drive transformer. In the nextclock cycle, OUTB is on for the same amount oftime (steady state operation) providing anopposite polarity voltage across the magnetizing
inductance. Averaging the voltage across theprimary for any two consecutive switchingperiod results zero volts.
RGATE
VCC
OUTA
GND
VDRV
Driver
OUTB
RGATE
VIN
Fig. 39. Push-pull type half-bridge gate drive.Therefore, AC coupling is not needed in
push-pull type gate drive circuits.Designers are often worried about any small
amount of asymmetry that could be caused bycomponent tolerances and offsets in thecontroller. These small deviations are easilycompensated by the output impedance of thedriver or by a small resistor in series with theprimary winding of the transformer. The unevenduty cycle will cause a small DC current in thetransformer which generates a balancing voltageacross the equivalent resistance of the drivecircuit. Assuming two different duty ratios, DAand DB for the PWM outputs, the DC currentlevel of the magnetizing inductance is defined as:
( )BAEQV
DRVDC DD
R2VI −⋅⋅
=
To demonstrate the triviality of this problem,let’s assume that DA=0.33, DB=0.31 (6% relativeduty ratio difference!), VDRV=12V, andREQV=5Ω which is the sum of one low side andone high side driver output impedance. Theresulting DC current is 24mA and the excesspower dissipation is only 3mW.
2-37
The design of the gate drive transformerfollows the same rules and procedures as alreadydescribed in this chapter. The maximum volt-second product is defined by VDRV and theswitching period, because push-pull circuits areusually not duty ratio limited.
Appropriate margin (~3:1) between worstcase peak flux density and saturation flux densitymust be provided.
A unique application of the push-pull typegate drive circuits is given in Fig. 40 to controlfour power transistors in a phase shift modulatedfull-bridge converter.
Due to the phase shift modulation technique,this power stage uses four approximately 50%duty cycle gate drive signals. The two MOSFETsin each leg requires a complementary drivewaveform which can be generated by the twooutput windings of the same gate drivetransformer. Although, steady state duty ratiosare always 0.5, changing the phase relationship
between the two complementary pulse trainsnecessitates to have an asymmetry in the dutycycles. Therefore, during transient operation thePWM outputs are not producing the normal 50%duty cycle signals for the gate drivetransformers. Accordingly, a safety margin mustbe built in the transformer to cover uneven dutyratios during transients.
Another interesting fact to point out is thatlocal turn-off circuits can be easily incorporatedand are very often needed on the secondary sideof the transformer. The gate drive transformer,more precisely the leakage inductance of thetransformer exhibits a relatively high impedancefor fast changing signals. The turn-off speed anddv/dt immunity of the power circuit can beseverely impacted if the driver’s pull downcapability is not optimized for high speedswitching applications.
VDRV
VCC
OUTD
GND
Phase ShiftPWM controller
OUTC
OUTB
OUTA
VIN
Fig. 40. Push-pull type half-bridge gate drive.
2-38
IX. SUMMARY
Like all books, this article should be readfrom the beginning to the end to get the wholestory. Every consideration described earlierregarding switching speeds, dv/dt immunity,bypassing rules etc. are equally applicable for allcircuits including transformer coupled gatedrives. As the topics build upon each other, onlythe unique and new properties of the particularcircuit have been highlighted.
This paper demonstrated a systematicapproach to design high performance gate drivecircuits for high speed switching applications.The procedure can be summarized by thefollowing step-by-step checklist:• • The gate drive design process begins AFTER
the power stage is designed and the powercomponents are selected.
• Collect all relevant operating parameters.Specifically the voltage and current stressesof the power MOSFET based on theapplication requirements, operating junctiontemperature, dv/dt and di/dt limits related toexternal circuits around the power MOSFETwhich are often determined by the differentsnubber or resonant circuitry in the powerstage.
• Estimate all device parameters whichdescribe the parasitic component values ofthe power semiconductor in the actualapplication circuit. Data sheet values areoften listed for unrealistic test conditions atroom temperature and they must be correctedaccordingly. These parameters include thedevice capacitances, total gate charge, RDS(on),threshold voltage, Miller plateau voltage,internal gate mesh resistance, etc.
• Prioritize the requirements: performance,printed circuit board size, cost target, etc.Then choose the appropriate gate drive circuitto match the power stage topology.
• Establish the bias voltage level which will beused to power the gate drive circuit and checkfor sufficient voltage to minimize the RDS(on)of the MOSFET.
• Select a driver IC, gate-to-source resistorvalue, and the series gate resistance RGATEaccording to the targeted power-up dv/dt, anddesired turn-on and turn-off switching speeds.
• Design (or select) the gate drive transformerif needed.
• Calculate the coupling capacitor values incase of AC coupling.
• Check start-up and transient operatingconditions, especially in AC coupled gatedrive circuits.
• Evaluate the dv/dt and di/dt capabilities of thedriver and compare it to the valuesdetermined by the power stage.
• Add one of the turn-off circuits if needed, andcalculate its component values to meet dv/dtand di/dt requirements.
• Check the power dissipation of allcomponents in the driver circuitry.
• Calculate the bypass capacitor values.• Optimize the printed circuit board LAYOUT
to minimize parasitic inductances.• Always check the gate drive waveform on the
final printed circuit board for excessiveringing at the gate-source terminals and at theoutput of the driver IC.
• Add protection or tune the resonant circuitsby changing the gate drive resistor as needed.
• In a reliable design, these steps should beevaluated for worst case conditions aselevated temperatures, transient voltage andcurrent stresses can significantly change theoperation of the driver, consequently theswitching performance of the powerMOSFET.Of course, there are many more gate drive
implementations which are not discussed in thispaper. Hopefully, the principles and methodspresented here can help the reader’sunderstanding and analyzing of other solutions.For those who are looking for quick answers inthe rather complex field of high speed gate drivedesign, Appendix A through E offer typical,numerical examples of the different calculations.Appendix F provides a complete, step-by-stepgate drive design example for an active clampforward converter with a ground referenced and afloating gate drive circuits.
2-39
REFERENCES
[1] V. Barkhordarian, “Power MOSFETBasics”, International Rectifier, TechnicalPaper
[2] S. Clemente, et al., “UnderstandingHEXFET® Switching Performance”,International Rectifier, Application Note947
[3] B. R. Pelly, “A New Gate Charge FactorLeads to Easy Drive Design for PowerMOSFET Circuits”, International Rectifier,Application Note 944A
[4] “Understanding MOSFET Data”, Supertex,DMOS Application Note AN-D15
[5] K. Dierberger, “Gate Drive Design ForLarge Die MOSFETs”, PCIM ‘93, reprintedas Advanced Power Technology,Application Note APT9302
[6] D. Gillooly, “TC4426/27/28 System DesignPractice”, TelCom Semiconductor,Application Note 25
[7] “Gate Drive Characteristics andRequirements for HEXFET®s”,International Rectifier, Application NoteAN-937
[8] “TK75050 Smart MOSFET DriverDatasheet”, TOKO Power Conversion ICsDatabook, Application Information Section
[9] Adams, “Bootstrap Component SelectionFor Control IC’s”, International Rectifier,Design Tip DT 98-2
[10] “HV Floating MOS-Gate Driver ICs”,International Rectifier, Application NoteINT978
[11] C. Chey, J. Parry, “Managing Transients inControl IC Driven Power Stages”International Rectifier, Design Tip DT 97-3
[12] “HIP408X Level Shifter Types”, HarrisSemiconductor
[13] “IR2110 High and Low Side Driver”International Rectifier, Data Sheet No. PD-6.011E
[14] “Transformer-Isolated Gate DriverProvides Very Large Duty Cycle Ratios”,International Rectifier, Application NoteAN-950B
[15] W. Andreycak, “Practical Considerationsin Troubleshooting and Optimizing PowerSupply Control Circuits and PCB Layout”,Unitrode Corporation, Power Supply DesignSeminar, SEM-1200, Topic 4
[16] L. Spaziani, “A Study of MOSFETPerformance in Processor Targeted Buckand Synchronous Buck Converters”, HFPCPower Conversion Conference, 1996, pp123-137
[17] W. Andreycak, “Practical ConsiderationsIn High Performance MOSFET, IGBT andMCT Gate Drive Circuits”, UnitrodeCorporation, Application Note U-137
[18] J. O’Connor, “Unique Chip Pair SimplifiesIsolated High Side Switch Drive” UnitrodeCorporation, Application Note U-127
[19] D. Dalal, “Design Considerations for ActiveClamp and Reset Technique”, UnitrodeCorporation, Power Supply Design SeminarSEM1100, Topic 3
[20] E. Wittenbreder, “Zero voltage switchingpulse width modulated power converters”,U.S. Patent No. 5402329.
[21] R. Erickson, “Lecture 20, The Transistor asa Switching Device”, Power ElectronicsECE579 Course Notes, Fall 1987, pg. 20-4through 20-16.
[22] R. Severns, J. Armijos, “MOSFETElectrical Characteristics”, MOSPOWERApplications Handbook, Siliconix, Inc.,1984, pg. 3-1 through 3-8.
[23] J. Bliss, “The MOSFET Turn-Off Device - ANew Circuit Building Block”, MotorolaSemiconductor, Engineering BulletinEB142, 1990.
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