Proceedings

Design, Automation and Testin Europe

February 23-26, 1998Paris, France

Sponsored by ,

European Design and Automation Association -—EDAAElectronic Design Automation Consortium — ED AC

IEEE Computer Society Technical Committee on Test TechnologyInternational Federation of Information Processing -

Working Group on CAD — IFIP 10.5European CAD Standards Initiative — ECSI

In cooperation with ,

ACM-SIGDA

AEIA ATI CEPIS CLCR CNR IEEE CS DATC

GI GMM HTE ITG KVIV MATE NIISAPRAN

IEEE' _ _

COMPUTERSOCIETY

Los Alamitos, California

Washington • Brussels • Tokyo

Inv.-Nr.

Table of Contents

Event Steering Board xixConference Organizing Committee xxProgramme Topic Chairs xxiVendors Committee xxiiTechnical Programme Committee xxiiiWelcome to DATE 98 xxviKeynote Addresses Summaries xxviiTutorials xxxList of Reviewers xxxiii

Session 1A: Design Optimization of Building BlocksModerators: Y. Zorian, LogicVision, USA

P. Plaza, Telefonca I+D, SpainCollapsing the Transistor Chain to an Effective Single Equivalent Transistor 2

A. Chatzigeorgiou and S. NikolaidisDesign of Fault-Secure Parity-Prediction Booth Multipliers 7

M. Nicolaidis and R. O. DuartePASTEL: A Parameterized Memory Characterization System 15

K. Ogawa, M. Kohno, and F. Kitamura

Session IB: HW/SW Partitioning and Communication SynthesisModerators: K. Buchenrieder, Siemens AG, Germany

A. Jerraya, TIMA, Grenoble, FranceHardware Resource Allocation for Hardware/Software Partitioning in theLYCOS System 22

J. Grode, P.V. Knudsen, and J. MadsenHardware Software Partitioning with Integrated Hardware DesignSpace Exploration 28

V. Srinivasan, S. Radhakrishnan, and R. VemuriGeneration of Interconnect Topologies for Communication Synthesis 36

M. Gasteier, M. Munch, and M. Glesner

Session 1C: Asynchronous and Hybrid VHDL-Based DesignModerators: A. Vachoux, Ecole Poly technique Federate de Lausanne, Switzerland

T. Kazmierski, University of Southampton, UKThe Design of an Asynchronous VHDL Synthesizer 44

S.-Y. Tan, S.B. Furber, and W.-F. YenRepartitioning and Technology Mapping of Electronic Hybrid Systems 52

C. Grimm and K. WaldschmidtVHDL-AMS: The Missing Link in System Design — Experiments with UnifiedModelling in Automotive Engineering 59

E. Moser and N. Mittwollen

Session ID: Data Path and FPGA TestingModerators: H.-J. Wunderlich, University of Stuttgart, Germany

M. Nicolaidis, TIMA, Grenoble, France

Scheduling and Module Assignment for Reducing BIST Resources 66/. Parulkar, S.K. Gupta, and M.A. Breuer

An Efficient Algorithm to Integrate Scheduling and Allocation inHigh-Level Test Synthesis 74

T. Yang and Z. PengRAM-Based FPGA's: A Test Approach for the Configurable Logic 82

M. Renovell, J.M. Portal, J. Figueras, and Y. ZorianNovel Technique for Testing FPGAs 89

C. Metra, G. Mojoli, S. Pastore, D. Salvi, and G. Sechi

Session 2A: Design Methods for High Performance ApplicationsModerators: Y. Torroja, Polytechnical University of Madrid, Spain

R. Sarmiento, University of Las Palmas de Gran Canaria, SpainATM Traffic Shaper: ATS 96

J.C. Diaz, P. Plaza, and J. CrespoXFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers 102

E. Lago, C.J. Jimenez, D.R. Lopez, S. Sdnchez-Solano, and A. BarrigaHigh Speed Neural Network Chip for Trigger Purposes in High Energy Physics 108

W. Eppler, T. Fischer, H. Gemmeke, and A. Menchikovi

Session 2B: Scheduling in Embedded SystemsModerators: S.A. Huss, Darmstadt University of Technology, Germany

H.-P. Amann, University ofNeuchdtel, Switzerland

CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-TimeAperiodic and Periodic Specifications of Embedded System Architectures 118

B.P. Dave and N.K. JhaStream Communication Between Real-Time Tasks in a High-PerformanceMultiprocessor 125

J.A.J. Leijten, J.L. van Meerbergen, A.H. Timmer, and JA.G. JessScheduling of Conditional Process Graphs for the Synthesis ofEmbedded Systems 132

P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, and P. Pop

Session 2C: Advanced Techniques for VHDL DesignModerators: E. Villar, University ofCantabria, Spain

D. Sciuto, Politecnico di Milano, Italy

Model Abstraction for Formal Verification 140Y.-W. Hsieh and S.P. Levitan

VHDL Modelling and Analysis of Fault Secure Systems 148J. Coppens, D. Al-Khalili, and C. Rozon

Register Transfer Level Models without Clocks 153M. Mutz

Parallel VHDL Simulation 159E. Naroska

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Session 2D: Novel BIST ApproachesModerators: E. Aas, Norwegian University of Science and Technology, Norway

Z. Peng, Linkoping University, Sweden

Testing DSP Cores Based on Self-Test Programs 166W. Zhao and C. Papachristou

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs 173V.N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich

Built-in Self-Test with an Alternating Output 180T. Bogue, M. Gossel, H. Jurgensen, and Y. Zorian

Session 3A: Architectures for Image ProcessingModerators: I. Bolsens, IMEC, Belgium

A. Nunez, University of Las Palmas de Gran Canaria, SpainFrom Algorithms to Hardware Architectures: A Comparison of Regularand Irregular Structured IDCT Algorithms 186

C. Schneider, M. Kayss, T. Hollstein, and J. DeickeSmart Pixel Implementation of a 2-D Parallel Nucleic Wavelet .Transform for Mobile Multimedia Communications 191

A.M. Rassau, K. Eshraghian, H. Cheung, S.W. Lachowicz, T.C.B. Yu,W.A. Crossland, and T.D. Wilkinson

VLSI Architecture for Lossless Compression of Medical Images Usingthe Discrete Wavelet Transform 196

/. Urriza, J.I. Artigas, J.I. Garcia, L.A. Barragdn, and D. Navarro

Session 3B: Scheduling and Analysis of HW/SW SystemsModerators: R. Ernst, Technical University of Braunschweig, Germany

P. van der Wolf, Philips Research Laboratories, The Netherlands

A Model for System-Level Timed Analysis and Profiling 204A. Allara, W. Fornaciari, F. Salice, and D. Sciuto

Efficient Compilation of Process-Based Concurrent Programs withoutRun-Time Scheduling 211

B.LinA Macroscopic Time and Cost Estimation Model Allowing Task Parallelismand Hardware Sharing for the Codesign Partitioning Process 218

J.A. Maestro, D. Mozos, and H. MechaA Scaleable Methodology for Cost Estimation in a TransformationalHigh-Level Design Space Exploration Environment 226

J. Gerlach and W. Rosenstiel

Session 3C: Extensions to VHDLModerators: S. Maginot, LEDA, France

W. Ecker, Siemens AG, Germany

Object-Oriented Modelling of Parallel Hardware Systems 234G. Schumacher and W. Nebel

A Flexible Message Passing Mechanism for Objective VHDL 242W. Putzke-Roming, M. Radetzki, and W. Nebel

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Enhanced Reuse and Teamwork Capabilities for an Object-OrientedExtension of VHDL 250

M. MrvaFormal Specification in VHDL for Hardware Verification 257

R. Reetz, K. Schneider, and T. Kropf

Session 3D: Error Detection and Design ValidationModerators: T. Vierhaus, Technical University ofCottbus, Germany

R. Segers, Philips Semiconductors, The NetherlandsA Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths 266

A. Antola, V. Piuri, and M. SamiMeasuring the Effectiveness of Various Design Validation Approachesfor PowerPC™ Microprocessor Arrays 273

L.-C. Wang, M.S. Abadir, and J. ZengFunctional Scan Chain Testing 278

D. Chang, M.T.-C. Lee, K.-T. Cheng, and M. Marek-Sadowska

Session 3E: Hot Topic: IP Based System-on-a-Chip DesignCo-ordinators: Carlo Guardiani, SGS-Thomson, Italy

Wolfgang Nebel, Oldenburg University and OFFIS, GermanyModerator: Alberto Sangiovanni-Vincentelli, University of California at Berkeley, USASpeakers: Grant Martin, Cadence, USA

Mike Muller, ARM, UKBart De Loore, Philips Semiconductors, The Netherlands

Panelists: Doug Fairbairn, VSI Alliance, USA 'Pietro Erratico, SGS-Thomson, ItalyFaysal Soheil, Synopsys, USA

Design Methodologies for System Level IP 286G. Martin

WIP-Based System-on-a-Chip Design 290 |JB. De Loore

Session 4A: Design Reuse MethodologiesModerators: J. Heaton, ICL, UK

R. Seepold, FZI Karlsruhe, GermanyA Systematic Analysis of Reuse Strategies for Design ofElectronic Circuits 292

M. Koegst, P. Conradi, D. Garte, and M. WahlVHDL Teamwork, Organization Units and Workspace Management 297

S. Olcoz, L. Ayuda, I. Izaguirre, and O. PenalbaAn Object-Oriented Model for Specification, Prototyping, Implementationand Reuse 303

J. Bbttger, K. Agsteiner, D. Monjau, and S. Schulze

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Session 4B: Flat and Timing-Driven Processor DesignModerators: E. Barke, University of Hannover, Germany

I. Rugen-Herzig, Temic Telefunken Microelectronic GmbH, GermanyA Flat, Timing-Driven Design System for a High-Performance CMOSProcessor Chipset 312

J. Koehl, U. Baur, T. Ludwig, B. Kick, and T. PfluegerAlgorithms for Detailed Placement of Standard Cells 321

J. VygenTiming Analysis and Optimization of a High-Performance CMOSProcessor Chipset 325

U. Fassnacht and J. SchietkeA Sequential Detailed Router for Huge Grid Graphs 332

A. Hetzel

Session 4C: Hot Topic: Reconfigurable SystemsCo-ordinator: Ivo Bolsens, IMEC, BelgiumModerator: Nadir Bagherzadeh, University of California at Irvine, USASpeakers: W. Shields Neely, National Semiconductor, USA

Jan Rabaey, University of California at Berkeley, USAIan Page, University of Oxford, UK

Reconfigurable Logic for Systems on a Chip 340W. Shields Neely

An Energy-Conscious Exploration Methodology for Reconfigurable DSPs 341J. Rabaey and M. Wan

Design of Future Systems 343I. Page

Session 4D: Digital Simulation and EstimationModerators: Peter Schwarz, Fraunhofer EAS Dresden, Germany

H. Fleurkens, Philips Research Laboratories, The NetherlandsAFTA: A Formal Delay Model for Functional Timing Analysis 350

V. Chandramouli, J.P. Whittemore, and K.A. SakallahPower-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs 356

D. Robe, G. Jochens, L. Kruse, and W. NebelAdvanced Optimistic Approaches in Logic Simulation 362

S. Schmerler, Y. Tanurhan, and K.D. Miiller-Glaser

Session 5A: Synthesis of Reprogrammable and Reconfigurable ArchitecturesModerators: F. Kurdahi, University of California, Irvine, USA

A. Jerraya, TIMA, Grenoble, FrancePSCP: A Scalable Parallel ASIP Architecture for Reactive Systems 370

A. Pyttel, A Sedlmeier, and C. VeithA Constraint Driven Approach to Loop Pipelining and Register Binding 377

B. Mesman, M. Strik, A.H. Timmer,J.L. van Meerbergen, and J.A.G. Jess

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Multiple Behavior Module Synthesis Based on Selective Groupings ...384J.-H. Yi, H. Choi, I.-C. Park, S.H. Hwang, and C.-M. Kyung

Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures 389M. Kaul and R. Vemuri

Session 5B: Partitioning and RoutingModerators: M.D.F. Wong, University of Texas at Austin, USA

F.M. Johannes, Technical University of Munich, GermanyAn Effective General Connectivity Concept for Clustering 398

J. Song, Z. Shen, and W. ZhuangImproved Approximation Bounds for the Group Steiner Problem 406

C.S. Helvig, G. Robins, and A. ZelikovskyAn Interactive Router for Analog IC Design 414

T. Adler and J. Scheible

Session 5C: Panel - Formal Verification: A New Standard CAD Tool for the IndustrialDesign FlowCo-ordinators: Wolfgang Rosenstiel, University of Tubingen, Germany

Gerry Musgrave, Brunei University, UKModerator: Gerry Musgrave, Brunei University, UKPanelists: Dominique Borrione, TIMA-UJF, France

Antun Domic, Synopsys, USARamayya Kumar, Verysys, GermanyAlan Page, Abstract Design Automation, UKMichael Payer, Siemens, Germany

Formal Verification: A New Standard CAD Tool for the Industrial Design Flow 422W. Rosenstiel

Session 5D: Simulation for High-Level DesignModerators: J. Forrest, UMIST, Manchester, UK

M. Pfaff, Johannes Kepler University Linz, AustriaA System-Level Co-Verification Environment for ATM Hardware Design 424

G. Post, A. Miiller, and T. GrotkerFRIDGE: A Fixed-Point Design and Simulation Environment 429

H. Keding, M. Willems, M. Coors, and and H. MeyrVerification by Simulation Comparison Using Interface Synthesis 436

C. Hansen, A. Kunzmann, and W. Rosenstiel

Session 6A: Architectural SynthesisModerators: P. Marwedel, University of Dortmund, Germany

A. Timmer, Philips Research Laboratories, The NetherlandsLayout-Driven High Level Synthesis for FPGA Based Architectures 446

M. Xu and F.J. KurdahiCross-Level Hierarchical High-Level Synthesis 451 '

O. Bringmann and W. Rosenstiel

An Algorithm to Determine Mutually Exclusive Operations inBehavioral Descriptions 457

J. Li and R.K. Gupta

Session 6B: Timing and Crosstalk in InterconnectModerators: R. Peset Llopis, Philips Research Laboratories, The Netherlands

B. Schiirmann, University of Kaisers tautern, GermanyA Performance-Driven MCM Router with Special Consideration ofCrosstalk Reduction ...466

D. Wang and E.S. KuhInterconnect Tuning Strategies for High-Performance ICs 471

A.B. Kahng, S. Muddu, E. Sarto, and R. SharmaA Polynomial Time Optimal Algorithm for Simultaneous Bufferand Wire Sizing 479

C.C.N. Chu and D.F. Wong

Session 6C: Panel: Next Generation System Design ToolsCo-ordinators: Wolfgang Rosenstiel, University of Tubingen, Germany

Joachim Kunkel, Synopsys, USAModerator: Joachim Kunkel, Synopsys, USAPanelists: Misha Burich, Cadance/Alta, USA

Raul Camposano, Synopsys, USAMark Genoe, Alcatel, BelgiumLev Markov, Mentor Graphics, USASteve Schulz, Texas Instruments, USA

Next Generation System Level Design Tools 488W. Rosenstiel

Session 6D: IDDQ and Memory TestingModerators: M. Sachdev, Philips Research Laboratories, The Netherlands

B. Straube, FhG IIS/EAS Dresden, GermanyEstimation of the Defective IDDQ Caused by Shorts inDeep-Submicron CMOS ICs 490

R. Rodriguez-Montanes and J. FiguerasA Fully Digital Controlled Off-Chip IDDQ Measurement Unit 495

B. Straka, H. Manhaeve, J. Vanneuville, and M. SvajdaMarch Tests for Word-Oriented Memories 501

A.J. van de Goor and I.B.S. Tlili

Session 7A: MicrosystemsModerators: J. Bausells, CNM, Barcelona, Spain

M. Glesner, Technical University of Darmstadt, GermanyA Modeling Approach to Include Mechanical Microsystem Componentsinto the System Simulation 510

R. Neul, U. Becker, G. Lorenz, P. Schwarz,J. Haase, and S. Wilnsche

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Fast Field Solvers for Thermal and Electrostatic Analysis 518V. Szekely and M. Rencz

Microsystems Testing: An Approach and Open Problems 524M. Lubaszewski, E.F. Cota, and B. Courtois

Session 7B: Interconnect ModelingModerators: F.M. Johannes, Technical University of Munich, Germany

J. Koehl, IBM Deutschland Entwicklung GmbH, Germany

Reduced-Order Modeling of Large Linear Passive Multi-Terminal CircuitsUsing Matrix-Pade Approximation 530

R.W. Freund and P. FeldmannAn Efficient Algorithm for Fast Parasitic Extraction and PassiveOrder Reduction of 3D Interconnect Models 538

N. Marques, M. Kamon, J. White, and L.M. SilveiraMCM Interconnect Design Using Two-Pole Approximation 544

J. Shao and R.M.M. Chen

Session 7C: Design for Manufacturability - Embedded TutorialModerators: M. Servit, Czech Technical University, Czech Republic

R. Peset Llopis, Philips Research Laboratories, The NetherlandsDesign-Manufacturing Interface: Part I — Vision 550

W. Maly, H.T. Heineken, J. Khare, and P.K. NagDesign-Manufacturing Interface: Part II — Applications 557

W. Maly, H.T. Heineken, J. Khare, P.K. Nag, P. Simon, and C. OuyangPerformance - Manufacturability Tradeoffs in IC Design 563

H.T. Heineken and W. Maly

Session 7D: Sequential Circuit TestingModerators: C. Landrault, LIRMM, France

D. Medina, Italtel, Italy

Fast Sequential Circuit Test Generation Using High-Level andGate-Level Techniques 570

EM. Rudnick, R. Vietti, A. Ellis, F. Corno,P. Prinetto, and M. Sonza Reorda

State Relaxation Based Subsequence Removal for Fast Static Compactionin Sequential Circuits 577

M.S. Hsiao and S.T. ChakradharProcedures for Static Compaction of Test Sequences for SynchronousSequential Circuits Based on Vector Restoration 583 f

R. Guo, I. Pomeranz, and S.M. Reddy 1

Session 8A: Issues in Behavioral Synthesis |Moderators: J. van Meerbergen, Philips Research Laboratories, The Netherlands

H. Hermanani, Lebanese American University, Lebanon

Architectural Simulation in the Context of Behavioral Synthesis 590A. Jemai, P. Kission, and A.A. Jerraya

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Scheduling of Outputs in Grammar-Based Hardware Synthesis of DataCommunication Protocols 596

J. Oberg, A. Kumar, and A. HemaniConcurrent Error Recovery with Near-Zero Latency in Synthesized ASICs 604

S.N. Hamilton and A. Orailoglu

Session 8B: Formal Equivalence Checking Using Decision DiagramsModerators: T. Filkorn, Siemens AG, Germany

H. Eveking, Darmstadt University of Technology, GermanyDynamic Minimization of Word-Level Decision Diagrams 612

S. Horeth and R. DrechslerSequential Equivalence Checking without State Space Traversal 618

C.A.J. van EijkOn the Reuse of Symbolic Simulation Results for Incremental EquivalenceVerification of Switch-Level Circuits 624

L. Ribas-Xirgo and J. Carrabina-Bordoll

Session 8C: Hot Topic: Silicon Debug of Systems-on-ChipsCo-ordinator: Wim Verhaegh, Philips Research Labs, The NetherlandsModerator: Erik Jan Marinissen, Philips Research Labs, The NetherlandsSpeakers: Karel van Doorselaer, Alcatel Telecom, Belgium

Sridhar Narayanan, Sun Microsystems, USAGert Jan van Rootselaar, Philips Research Labs, The Netherlands

Silicon Debug of Systems-on-Chips 632

Session 8D: Characterization and Verification of Analogue CircuitsModerators: G. Gielen, Katholieke Universiteit Leuven, Belgium

C. Descleves, Dolphin Integration, FranceHierarchical Characterization of Analog Integrated CMOS Circuits 636

J. Eckmiiller, M. Gropl, and H. GrabEASY — A System for Computer-Aided Examination of Analog Circuits 644

G. Droge, M. Thole, and E.-H. HorneberA Formal Approach to Verification of Linear Analog Circuits withParameter Tolerances 649

L. Hedrich and E. Barke

Session 9A: Benchmark Circuits, Technology Mapping and Scan ChainsModerators: A ten Berg, Philips Research Laboratories, The Netherlands

M. Berkelaar, Eindhoven University of Technology, The NetherlandsSynthesis of Wiring Signature-Invariant Equivalence Class CircuitMutants and Applications to Benchmarking 656

D. Ghosh, N. Kapur, J. Harlow HI, and F. BrglezTechnology Mapping for Minimizing Gate and Routing Area 664

A. Lu, G. Stenz, and F.M. JohannesExploiting Symbolic Techniques for Partial Scan Flip Flop Selection 670

F. Corno, P. Prinetto, M. Sonza Reorda, and M. Violante

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Session 9B: Physical to Gate Level Design for Low-PowerModerators: C. Piguet, CSEM, Switzerland

E. Macii, Politecnico di Torino, ItalyTemperature Effect on Delay for Low Voltage Applications 680

J.M. Daga, E. Ottaviano, and D. AuvergneData Driven Power Optimization of Sequential Circuits 686

Q. Wang and S.B.K. VrudhulaGated Clock Routing Minimizing the Switched Capacitance 692

J.W. Oh and M. PedramExact and Approximate Estimation for Maximum Instantaneous Currentof CMOS Circuits 698

Y.-M. Jiang and K.-T. Cheng

Session 9C: Hot Topic: Embedded Memory and Embedded LogicCo-ordinator: Ivo Bolsens, IMEC, BelgiumModerator: Ivo Bolsens, IMEC, BelgiumSpeakers: Norbert Wehn, University of Kaiserslautern, Germany

Soren Hein, Siemens, GermanyFrancky Catthoor, IMEC, BelgiumRoelof Salters, Philips Research Labs, The Netherlands

Embedded DRAM Architectural Trade-Offs 704N. Wehn and S. Hein

Energy-Delay Efficient Data Storage and Transfer Architectures: CircuitTechnology Versus Design Methodology Solutions 709

F. Catthoor

Session 9D: Analogue Circuit Modeling and Design MethodologyModerators: J. Franca, 1ST, Lisbon, Portugal

H. Kerkhoff, University of Twente, The NetherlandsHierarchical Top-Down Design of Analog Sensor Interfaces: FromSystem-Level Specifications Down to Silicon 716

J. Vandenbussche, S. Donnay, F. Leyn, G. Gielen, and W. SansenA Systems Theoretic Approach to Behavioural Modeling and Simulationof Analog Functional Blocks 721

R. Rosenberger and S.A. HussSwitching Response Modeling of the CMOS Inverter for Sub-Micron Devices 729

L. Bisdounis, S. Nikolaidis, O. Koufopavlou, and C.E. Goutis

Session 10A: Combinational Logical SynthesisModerators: M. Berkelaar, Eindhoven University of Technology, The Netherlands

L. Stok, IBM T.J. Watson Research Center, USA

On Removing Multiple Redundancies in Combinational Circuits 738S.-C. Chang, D.I. Cheng, and C.-W. Yeh

Multi-Output Functional Decomposition with Exploitation of Don't Cares 743C. Scholl

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An Efficient Divide and Conquer Algorithm for Exact Hazard FreeLogic Minimization 749

J.W.J.M. Rutten, M.R.C.M. Berkelaar, C.A.J. van Eijk, and M.A.J. KolsterenRestructuring Logic Representations with Easily Detectable SimpleDisjunctive Decompositions 755

H. Sawada, S. Yamashita, and A. Nagoya

Session 10B: High Level Power EstimationModerators: W. Nebel, University of Oldenburg and OFFIS, Germany

J. Benkoski, Synopsys, France

Power Estimation of Behavioral Descriptions 762F. Ferrandi, F. Fummi, E. Macii, M. Poncino, and D. Sciuto

Characterization-Free Behavioral Power Modeling 767A. Bogliolo, L. Benini, and G. De Micheli

Trace-Driven Steady-State Probability Estimation in FSMs withApplication to Power Estimation 774

D. Marculescu, R. Marculescu, and M. Pedram

Session IOC: Petri Nets and Dedicated FormalismsModerators: L. Claesen, IMEC, Belgium

C. Delgado Kloos, ETSI Telecommunicacion, SpainEfficient Verification Using Generalized Partial Order Analysis 782

S. Vercauteren, D. Verkest, G. de Jong, and B. LinEfficient Encoding Schemes for Symbolic Analysis of Petri Nets 790

E. Pastor and J. CortadellaPropagation of Last-Transition-Time Constraints in Gate-LevelTiming Analysis 796

M. Kassab, E. Cerny, S. Aourid, and T. KrodelCombinational Verification Based on High-Level Functional Specifications 803

E.I. Goldberg, Y. Kukimoto, and R.K. Brayton

Session 10D: Mixed-Signal Test and DFTModerators: A. Richardson, University of Lancaster, UK

M. Sachdev, Philips Research Laboratories, The NetherlandsSwitch-Level Fault Coverage Analysis for Switched-Capacitor Systems ..810

S. Mir, A. Rueda, D. Vazquez, and J.L. HuertasOptimized Implementations of the Multi-Configuration DFT Techniquefor Analog Circuits 815

M. Renovell, F. Azais, and Y. BertrandAnalog Test Design with IDD Measurements for the Detection ofParametric and Catastrophic Faults 822

W.M. Lindermeir, T.J. Vogels, and H.E. Graeb

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Session 11 A: Sequential Logic SynthesisModerators: L. Stok, IBM T J Watson Research Center, USA

A ten Berg, Philips Research Laboratories, The NetherlandsA New Paradigm for Dichotomy-Based Constrained Encoding 830

O. CoudertA Dynamic Model for the State Assignment Problem 835

M. Martinez, M.J. Avedillo, J.M. Quintana, and J.L. HuertasEfficient Minarea Retiming of Large Level-Clocked Circuits 840

N. Maheshwari and S.S. Sapatnekar

Session 11B: High-Level Power OptimizationModerators: M. Pedram, University of Southern California, USA

M. Poncino, Politecnico di Torino, Italy

IMPACT: A High-Level Synthesis System for Low Power Control-FlowIntensive Circuits 848

K.S. Khouri, G. Lakshminarayana, and N.K. JhaInstruction Scheduling for Power Reduction in Processor-Based System Design 855

H. Tomiyama, T. Ishihara, A. Inoue, and H. YasuuraAddress Bus Encoding Techniques for System-Level Power Optimization 861

L. Benini, G. De Micheli, E. Macii, D. Sciuto, and C. Silvano

Session 11C: System Architecture DesignModerators: M. Kovac, University of Zagreb, Croatia

W. Glauert, University of Erlangen-Nurnberg, GermanyA Scaleable Architecture for Multi-Threaded JAVA Applications 868

M. Mrva, K. Buchenrieder, and R. KressHardware/Software Co-Design of a Fuzzy RISC Processor 875

V. Salapura and M. GschwindInnovative System-Level Design Environment Based on FORM forTransport Processing System 883

K. Higuchi and K. Shirakawa

Session 11D: Simulation and Test Tools for Analogue CircuitsModerators: J.L. Huertas, Centro Nacional de Microelectronica, Spain

J. Pikkarainen, Nokia Mobile Phones, Finland

Efficient Techniques for Accurate Modeling and Simulation of SubstrateCoupling in Mixed-Signal ICs 892

J.P. Costa, M. Chou, and L.M. SilveiraEfficient DC Fault Simulation of Nonlinear Analog Circuits 899

M. W. Tian and C. -J.R. ShiAn Approach to Realistic Fault Prediction and Layout Design forTestability in Analog Circuits 905

J.A. Prieto, A. Rueda, I. Grout, E. Peralias,J.L. Huertas, and A.M.D. Richardson

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Poster SessionSynthesis of Communicating Controllers for ConcurrentHardware/Software Systems 912

R. Niemann and P. MarwedelA Knowledge-Based System for Hardware-Software Partitioning 914

M.L. Lopez, C.A. Iglesias, and J.C. LopezA Formal Description of VHDL-AMS Analogue Systems 916

T. KazmierskiScanning Datapaths: A Fast and Effective Partial Scan Selection Technique 921

M.L. Flottes, R. Pires, B. Rouzeyre, and L. VolpeUniversal Strong Encryption FPGA Core Implementation 923

D. Runje and M. KovacData Cache Sizing for Embedded Processor Applications 925

P.R. Panda, N.D. Dutt, and A. NicolauA Programmable Multi-Language Generator for CoDesign 927

J.P. Calvez, D. Heller, F. Muller, and O. PasquierRegister-Constrained Address Computation in DSP Programs. 929

A. Basu, R. Leupers, and P. MarwedelGraphical Entry of FSMDs Revisited: Putting Graphical Modelson a Solid Base 931

T. Muller-Wipperfurth and R. HagelauerAGENDA: An Attribute Grammar Driven Environment for the DesignAutomation of Digital Systems 933

G. Economakos, G. Papakonstantinou, and P. TsanakasStatic Analysis Tools for Soft-Core Reviews and Audits 935

S. Olcoz, A. Castellvi, M. Garcia, and J.-A. GomezA VHDL SGRAM Model for the Validation Environment of a High PerformanceGraphic Processor 937

M.G. Wahl and H. VolkelA Comparing Study of Technology Mapping for FPGA 939

H.-G. Martin and W. RosenstielFuzzy-Logic Digital-Analogue Interfaces for Accurate Mixed-SignalSimulation 941

T.J. KazmierskiOptimized Timed Hardware Software Cosimulation without Roll-Back 945

W. Sung and S. HaA Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design 947

J.A. Montiel-Nelson, V. de Armas, R. Sarmiento, and A. NunezArchitectural Rule Checking for High-Level Synthesis 949

J. Gong, C.-T. Chen, and K. KiiciikcakarA Unified Technique for PCB/MCM Design by Combining ElectromagneticField Analysis with Circuit Simulator 951

H. Kimura andN. IyenagaCore Interconnect Testing Hazards 953

P. Nordholz, H. Grabinski, D. Treytnar, J. Otterstedt,D. Niggemeyer, U. Arz, and T. W. Williams

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Quality Estimation of Test Vectors and Functional Validation ProceduresBased on Fault and Error Models 955

T. Riesgo, Y. Torroje, E. de la Torre, and J. UcedaFault Analysis in Networks with Concurrent Error Detection Properties 957

C. Bolchini, F. Salice, and D. SciutoIOCIMU — An Integrated Off-Chip IDDQ Measurement Unit 959

M. Svajda, B. Straka, and H. ManhaeveAutomatic Topology Optimization for Analog Module Generators 961

M. Wolf and U. KleineAsynchronous Scheduling and Allocation 963

A. PrihozhyPath Verification Using Boolean Satisfiability 965

M. Ringe, T. Lindenkreuz, and E. BarkePowerShake: A Low Power Driven Clustering and Factoring Methodologyfor Boolean Expressions '. 967

S. Roy, H. Arts, and P. BanerjeePower and Timing Modeling for ASIC Designs 969

W. Roethig, A.M. Zarkesh, and M. AndrewsConstraints Space Management for the Layout of Analog ICs 971

B.G. Arsintescu and R.H.J.M. OttenA Synthesis Procedure for Flexible Logic Functions 973

I. Pomeranz and S.M. ReddyDenotational Semantics of a Behavioral Subset of VHDL 975

F. NicoliCorrect High-Level Synthesis: A Formal Perspective 977

J.M. Mendias, R. Hermida, and M. FernandezA Bypass Scheme for Core-Based System Fault Testing 979

M. Nourani and C. PapachristouHighly Testable and Compact 1-out-of-n Code Checker with Single Output 981

C. Metra, M. Favalli, and B. RiccoDesign-for-Testability for Synchronous Sequential Circuits UsingLocally Available Lines 983

/. Pomeranz and S.M. ReddyCMOS Combinational Circuit Sizing by Stage-Wise Tapering 985

S. Pullela, R. Panda, A. Dharchoudhury, G. Vijayan, and D. BlaauwFault Detection for Linear Analog Circuits Using Current Injection 987

J. Velasco-Medina, T. Calin, and M. Nicolaidis

Author Index 989

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