design compiler user guide.pdf

Design Compiler User Guide 2003

ASIC Design Manual

Design Compiler User Guide

Published in March, 2003Document ID: BDE0010A

(C) Copyright 2003 TOSHIBA Corporation

All Rights Reserved

The information contained herein is subject to change without notice.

TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.

The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer’s own risk.

Toshiba does not take any responsibility for incidental damage (including loss of business profit, business interruption, loss of business information, and other pecuniary damage) arising out of the use or disability to use the product.

The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or patent rights of TOSHIBA or others.

The products described in this document may include products subject to the foreign exchange and foreign trade laws.

Design Compiler and PrimeTime are trademarks of Synopsys, Inc. Verilog is a trademark of Cadence Design Systems, Inc. All other products or services mentioned in this document are identified by the trademarks or service marks of their respective companies or organizations.

Design Compiler User Guide Preface

Preface

This manual is for ASIC designers using Synopsys’s Design compiler. This manual discusses logic synthesis and optimization methodologies, and the Links-to-Layout (LTL) methodology. Before performing logic synthesis, be sure to read this manual.

You can use Synopsys’ manual and Toshiba’s design tool manuals and data books, along with this manual.

All information in this manual is based on the latest product information available at the time of printing. Toshiba reviewed the accuracy of this manual, but should you find, in this manual, any ambiguities or be in doubt as to any meanings, please direct all queries to your nearest Toshiba ASIC design center.

Design Compiler Versions Supported

For the versions of Design Compiler supported by Toshiba, ask your Toshiba design center engineer.

Technology and Sign-Off System Supported

The following shows the array families and NLDM library versions described in this manual.

Array Family

Gate Array TC190G, TC200G, TC203G, TC220G, TC223G

Cell-based ICTC190C, TC200C, TC203C, TC220C, TC222C, TC223C, TC240C, TC260C, TC280C

Embedded Array TC200E, TC203E, TC220E, TC223E, TC240E, TC260E

Note: Ask your design center engineer for Toshiba-supported technology series and libraries.

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Preface Design Compiler User Guide

Manual Organization

This manual is organized as follows:

Part 1: Toshiba Design Compiler Design Kit

Describes features of the libraries used with the Toshiba Design Compiler design kit, design environment setup for Design Compiler, and recommended circuit structure.

♦ Chapter 1, "Toshiba Library Features", describes the features of the libraries used with the Toshiba Design Compiler design kit.

♦ Chapter 2, "Design Environment Setup", describes how to set up the environment for Design Compiler.

♦ Chapter 3, "Recomended Circuit Structure", describes circuit structure recommended by Toshiba.

Part 2: Running Design Compiler

Perform logic synthesis by using Synopsys’ Design Compiler. Describes preparation for static timing analysis, and static timing analysis with PrimeTime.

♦ Chapter 4, "Logic Synthesis and Optimization", describes the Design Compiler commands used for logic synthesis and design optimization.

♦ Chapter 5, "Static Timing Analysis", describes preparation for static timing analysis and static timing analysis with PrimeTime.

Part 3: RTL Coding Styles

Designing today’s complex ASICs requires you to specify your designs at register-transfer level (RTL) in Verilog-HDL or VHDL. Once you have created a design implementation that meets your high-level cost and timing goals, you map your design to a technology-specific library to create a gate-level design. To achieve a desired design implementation, you need to be familiar with the features of Toshiba’s ASIC library as well as some of the concepts of synthesis specific to Verilog-HDL and VHDL coding styles.

♦ Chapter 6, "Register Definition", presents a number of Verilog-HDL and VHDL descriptions to make the best use of Toshiba’s cell library to produce sequential behavior. Also, describes module partitioning, Finite-State Machines (FSMs) and combinational synthesis.

♦ Chapter 7, "Considerations in RTL-level Descriptions", describes important things you should know about descriptions at the RTL level.

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Design Compiler User Guide Preface

Other Sources of Information

♦ Synopsys documentation (CD-ROM)

Synopsys On-Line Documents (SOLD)

♦ Toshiba documentation

Design Manual

• CMOS ASIC Design Manual

• DESIGN-FOR-TEST HANDBOOK

Design Tool Manual

• VSO/VITALSO x.xx User Guide

• VOYSO x.xx User Guide

• VSO/DFT and VITALSO/DFT

• Sign-Off System Command Reference

• MemoryBIST Design System

• PrimeTime Sign-Off System User Guide

Data Book

Data book of the technology family shown in "Technology and Sign-Off System Supported" on page i.

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Preface Design Compiler User Guide

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Design Compiler User Guide Contents

Contents

Part 1 Toshiba Design Compiler Design Kit . . . . . . . . . . . . . . . . . . . . . 1

Chapter 1 Toshiba Library Features . . . . . . . . . . . . . . . . . . . . . . . . 3Library Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Nonlinear Delay Model (NLDM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Multiple K-Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Design Kit Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Design Kit Supporting Multiple K-factors (TC203 or Later Series) . . . . . . . . . . . . . . . 4Design Kit Supporting Single K-factor (TC220 or Earlier Series) . . . . . . . . . . . . . . . . 9

Library Specifications and Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 2 Design Environment Setup . . . . . . . . . . . . . . . . . . . . . 15Creating the .synopsy_dc.setup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Specifying Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Bus Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Variables Used for HDL (VHDL) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Internal Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Naming Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Invoking Design Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Setting Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Invoking Design Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chapter 3 Recommended Circuit Structure . . . . . . . . . . . . . . . . . 21Basic Circuit Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Top Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Circuit Structure around Megacells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Considering Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Considering Scan Design and ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Megacell Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Circuit Structure around I/O Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Considering Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Considering JTAG Boundary-Scan Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Forbidden Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Unconnected Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Wired-ORed Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Pass-Through Nets and Multiple-Port Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Feed-Back Loop of Combinational Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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Contents Design Compiler User Guide

Part 2 Running Toshiba Design Compiler . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 4 Logic Synthesis and Optimization . . . . . . . . . . . . . . . 33Selecting a New Wire Load Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Net Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

K-Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Multiple K-Factors (TC203 or Later Series Libraries). . . . . . . . . . . . . . . . . . . . . . . . . 35Single K-factor (TC190 and TC200 Series Libraries) . . . . . . . . . . . . . . . . . . . . . . . . . 36Checking Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Setting Clock Waveforms (create_clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Suppressing Addition of Clock buffers to a Clock Signal (set_dont_touch_network) 38Setting Clock Skews (set_clock_uncertainty, set_fix_hold) . . . . . . . . . . . . . . . . . . . . 38Setting Delay to Gated Clock (set_propagated_clock) . . . . . . . . . . . . . . . . . . . . . . . . 39

Reset Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Suppressing Addition of Buffers to the Reset Signal (set_dont_touch_network) . . . . 40Notes on Synchronous Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Considerations on DFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Avoiding Mapping of Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Considerations on JTAG Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Megacells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44I/O Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Inserting I/O Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Logic Synthesizing Modules Containing I/O Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Pass-Through Nets and Multiple Port Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Interface to Other EDA Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Setting Variables in the .synopsys_dc.setup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Name Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Checking Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Checking Design Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Displaying Port Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Displaying Cell Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Displaying Net Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Checking Connection to Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Checking Drive Limit Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Checking Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Logic Synthesis and Optimization Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Chapter 5 Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 55Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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Design Compiler User Guide Contents

Timing Analysis Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Creating the DCSDF File (.dcsdf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Reading the DCSDF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Running the Timing Constraint Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Part 3 RTL Coding Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Chapter 6 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63VHDL Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Excluding Specific Register Cells from Sequential Mapping . . . . . . . . . . . . . . . . . . . . . . 65Wait Statement (VHDL Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Sequential Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Mapping to Flip-Flops Available in the Toshiba Library . . . . . . . . . . . . . . . . . . . . . . 67Mapping to Latches Available in the Toshiba Library . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Mapping to Latches Unavailable in the Toshiba Library . . . . . . . . . . . . . . . . . . . . . . . . . 91Module Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Finite-State Machines (FSMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Mealy Machines vs. Moore Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96State Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Combinational Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Chapter 7 Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Verilog-HDL and Synthesis of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

The casez and casex Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Assignment and Comparison Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Module Statement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

VHDL and Synthesis of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Recommended VHDL Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104The case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Other Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105I/O Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Handling of an X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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Style Conventions

The following syntax and notation conventions are used throughout this manual:

Courier Bold Indicates any reference to a command. In many cases, it indicates keywords or command line options that you must enter literally (or exactly as shown).

Courier Oblique Indicates variable information, or user-defined arguments for which you must substitute a name or a value.

Courier Plain In examples, shows text from files and reports printed by the system.

... Elements preceding ellipses may be repeated any number of times.

[A] Indicates an optional argument.

[A|B|C] Indicates a list of choices from which you can choose one.

{A|B|C} Indicates a list of choices from which you must choose one.

underscore|B|C Indicates a default option or argument when there is more than one choice.

You must type all other punctuation symbols such as the comma, colon, slash, backslash, and quotation mark, as shown.

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Part 1

Toshiba Design

Compiler Design Kit

1

Toshiba Library Features

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CHAPTER 1 Toshiba Library Features

This chapter describes the library for Toshiba Design Compiler design kit.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Library Features

The following advanced technical features for delay prediction provide the increased accuracy of the libraries.

Nonlinear Delay Model (NLDM)

Unlike typical linear delay model (LDM), propagation delays are presented in nonlinear format. Propagation delays are calculated with a cell’s output load (wire loads and fanout load) and slew rate.

Multiple K-Factors

With TC203 or later series, multiple K-factors are applied to library cells. Cells are classified into several groups, and different cell groups are assigned different K-factors in the technology library.

3


. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Design Kit Directory Structure

The contents of the design kit to be released vary depending on technology series and cells to be used. This section describes general directory structure of the Toshiba Design Compiler design kit.

Design Kit Supporting Multiple K-factors (TC203 or Later Series)

Figure 1–1 shows the directory structure of design kit with TC203 or later series, which supports multiple K-factors.

Figure 1–1 Design Kit Directory Structure (TC203 or Later Series)

The following discusses directories and files contained in a design kit.

♦ <Customername>

Specifies the customer name.

♦ Read.me

Contains the contents being released, and descriptions of how to read data from the media.

<CustomerName> Read.me

Application.Note

etc/

doc/

bin/

tcxxxx/

tcxxxx.db_<operating_condition>

TCxxxx_<metal_layer>_IO_SMACRO.db

TCxxxx_IO.db_<operating_condition>

TCxxxx_MACRO.db_<operating_condition>

TCxxxx_MEM_DC.db_<operating_condition>

TCxxxx_MEM_PT.db_<operating_condition>

and

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♦ Application.Note

Contains the library specifications.

♦ etc/

Contains the sample .synopsys_dc.setup file. For the details of the .synopsys_dc.setup file, see Chapter 2.

Earlier than sign-off system 1.12

• VSO: synopsys_dc.setup_for_Verilog_SO

• VITAL or VOYSO: synopsys_dc.setup_for_VHDL_SO

Contains two types of sample .synopsys_dc.setup file. One is used for VSO (Verilog sign-off simulator), and the other is for VITALSO or VOYSO (VHDL sign-off simulator.) Select either one of them depending Toshiba sign-off system being used.

Sign-off system 1.12A or later

• VSO, VITAL or VOYSO: synopsys_dc.setup_for_ToshibaSO

Sign-Off system 1.12A or later supports dc_shell and tcl script specifications, which are usable in either one of VSO, VIAL or VOYSO environment.

♦ doc/

Contains the Design Compiler document files.

♦ bin/

Contains the application programs required for sign-off.

♦ tcxxx/

Contains the libraries and report files shown below. The library file have the filename extension db or sbd, and the report files have rep.

• tcxxxx.db_<condition_name>, tcxxxx.rep_<condition_name>

The standard K-factor library and report files. The standard K-factor indicates the operating condition values of cells contained in the design kit released by Toshiba. When synthesizing Toshiba ASICs under standard operating conditions, use this library. When you want to use non-standard conditions, use the K-factor library to be released by custom requirement. For the detail see "tcxxxx.db_<operating_condition>" on page 7.

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Table 1–1 shows the sample K-factor libraries for TC240C technology series.

Table 1–1 Sample Standard K-Factor Libraries (TC240C Series)

• tcxxxx_wire_load.db, tcxxxx.wire_load.rep

The library containing wire load models. Wire load models are contained in the Design Compiler design kit only.

• tcxxxx_<metal_layer>_io_macro.db, tcxxxx_<metal_layer>_io_macro.rep

All I/O cells for TC240 to TC260C series are softmacrocells that are hierarchically built by combining a main buffer and a prebuffer. This library contains net information between main buffers and prebuffers.

• tcxxxx_io.db<operating_conditon>, tcxxxx_io.rep

With some technology series, internal cells and I/O cells are stored separately in different files. This file contains prebuffers of I/O cells hierarchically built.

• tcxxxx_workview.sdb, tcxxxx_workview.rep

The symbol library containing graphic information of every cell, that is the information of cell shapes to be displayed with Design Analyzer.

• tcxxxx_ocs_macro.db, tcxxxx_ocs_macro.rep

Contains oscillator cells. This library does not exist when standard oscillator cells are not provided for some technology series.

• tcxxxx_hmacro.db, tcxxxx_hmacro.rep

Contains hardmacrocells, which are released with cell-based IC and embedded arrays. This library is not provided for the technology series in which the standard hardmacrocells are not used

FilenameOperating Condition

Temperature(°C)

Voltage(V)

Process

tc240c.db_NOMIN25 NOMIN25 25 2.50 Typical

tc240c.db_WCCOM25 WCCOM25 70 2.30 Worst

tc240c.db_WCIND25 WCIND25 85 2.30 Worst

tc240c.db_WCMIL25 WCMIL25 125 2.30 Worst

tc240c.db_BCCOM25 BCCOM25 0 2.70 Best

tc240c.db_BCIND25 BCIND25 -40 2.70 Best

tc240c.db_BCMIL25 BCMIL25 -55 2.70 Best

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♦ tcxxxx.db_<operating_condition>

The K-factor library released by custom requirements. When the customer uses conditions other than the typical condition, Toshiba releases this library. <operating_condition> indicates MAX, TYP or MIN. When you use worst-case K-factor library for TC240C technology series, for example, Toshiba releases the tc240c.db_MAX file.

♦ tcxxxx_MEM_DC.db_<operating_condition>♦ tcxxxx_MEM_PT.db_<operating_condition>♦ tcxxxx_MACRO.db_<operating_condition>♦ tcxxxx_IO.db_<operating_condition>

Contains megacells and custom cells. <operating_condition> depends on the K-factor to be applied. When the standard K-factor is used, it becomes the operating condition name in the standard K-factor library. In the case of the non-standard K-factor, MAX, TYP or MIN is used.

♦ tcxxxx_<metal_layer>_IO_SMACRO.db

All I/O cells for the TC240 or later series are softmacrocells that are hierarchically built. This library is provided for TC240 to TC260 series when custom I/O cells are softmacrocells.

TC260C Series Libraries

The following libraries are used depending on I/O cell type and primitive cell type. Be care different filenames set to different libraries.

Table 1–2 I/O Cell Library for TC260C Series

I/O Cell Library

I/O Type 1tc260c_wire_load.dbtc260c<metal_layer>_io_macro.dbtc260c_io.db_<operating_condition>

I/O Type 2c260c_wire_load.db_LHtc260c<metal_layer>_io_macro.db_LHtc260c_io.db_<operating_condition>_LH

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Table 1–3 Primitive Cell Library for TC260C Series

* When you use it, consult Toshiba ASIC engineering staff.

TC260E Series Libraries

The following libraries are used depending on I/O cell type. Be care different filenames set to different libraries.

Table 1–4 I/O Cell Library for TC260E Series

TC280C Series Libraries

The following libraries are used depending on I/O cell type and primitive cell type. Be care different filenames set to different libraries.

Table 1–5 I/O Cell Library for TC280C Series

Primitive Cell Library

Primitive Type 1 tc260c.db_<operating_condition>

Primitive Type 2*(High-speed Library)

tc260c_hs.db_<operating_condition>

Primitive Type 3*(Post-mask ECO Library)

tc260c_pme.db_<operating_condition>

I/O Cell Library

I/O Type 1tc260e_wire_load.dbtc260e<metal_layer>_io_macro.dbtc260e_io.db_<operating_condition>

I/O Type 2tc260e_wire_load.db_LHtc260e<metal_layer>_io_macro.db_LHtc260e_io.db_<operating_condition>_LH

I/O Cell Library

I/O Type 1tc280c_wire_load.dbtc260c_io.db_<operating_condition>

I/O Type 2tc280c_wire_load.db_LHtc280c_io.db_<operating_condition>_LH

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Table 1–6 Primitive Cell Library for TC280C Series

* When you use it, consult your Toshiba design center engineer.

Design Kit Supporting Single K-factor (TC220 or Earlier Series)

Figure 1–2 shows the directory structure of the design kit for TC190 and TC200 series which support single K-factor.

Figure 1–2 Design Kit Directory Structure (TC200 or Earlier Series)

The following discusses only the structure of the design kit that is different from that of the design kit supporting multiple K-factors.

♦ TCxxxx_MACRO.db, TCxxxx_IO.db

Contains megacells and custom cells.

♦ megacell.db

Contains the information of the top level for megacells.

Primitive Cell Library

Primitive Type 1 tc280c.db_<operating_condition>


tc280c_hs.db_<operating_condition>


tc280c_vs.db_<operating_condition>

Primitive Type 4*(Post-mask ECO Library)

tc280c_pme.db_<operating_condition>

<CustomerName> Read.me

Application.Note

etc/

doc/

tcxxxx/

TCxxxx_MACRO.db, TCxxxx_IO.db

megacell.db

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Library Specifications and Constraints

This section describes library specifications and constraints.

♦ Operating system (OS)

Libraries to be used do not depend on the operating system. You can use libraries on any operating system supported by Design Compiler. When using an operating system, consult your Toshiba design center engineer.

♦ Version

The libraries created by Design Compiler with earlier versions can be used with the later version. When using a library, consult your Toshiba design center engineer.

♦ Time units

The units of delay time are ns for all technology series. Specify the delay in ns units from the command line.

♦ Loading Units

The following shows the loading units used by every technology series. Loading units must be specified inside and outside of ASIC separately.

Table 1–7 Loading Units (Pre-TC240 Series)

Input Pin Output Pin Bidirectional Pin

Internal Cell LU LU -

Input Buffer pF LU -

Output Buffer LU pF -

Bidirectional Buffer LU LU pF

Note: Loading Units (LU) is defined as the sum of a P- and N-channel MOSFET gate capacitance.

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Table 1–8 Loading Units (TC240, TC260 and TC280 Series)

♦ Area units of an individual cell

The following shows the area units used for individual cell in Toshiba Design Compiler library for every series. With cell-based ICs for TC240 or later series, the area units of an individual cell differ between Design Compiler library and Sign-off tool. (Grid is used with the sign-off tool).

Table 1–9 Area Units of a cell in Toshiba Design Compiler Library

♦ I/O Cells

• Delay time calculation and TTL or CMOS interface

Delays of output buffers and 3-state output buffers are calculated based on TTL interface, whereas delays of bidirectional buffers are calculated based on TTL level in the case of TTL interface, and CMOS level in the case of cells for CMOS. For the details, see the data book for specified series. The following shows examples:

BD4C: CMOS LEVELBD4TH: TTL LEVEL

Input Pin Output Pin Bidirectional Pin

Internal Cell fF fF -

Input Buffer pF fF -

Output Buffer fF pF -

Bidirectional Buffer fF fF pF

Gate Array Cell-Based IC Embedded Array

Pre-TC240 Series Gate Grid Gate

TC240 Series -Unit

(Grid/4)Gate

TC260 Series -Unit

(Grid/3)Gate

TC280 Series -Unit

(Grid/4)-

Note: Parentheses indicate the units used with the sign-off tool.

Note: The chip area is obtained with the total number of grids or units. For how to obtain the chip area, consult your design center engineer.

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• Attribute

Set the dont_touch attribute to all I/O cells so that they can not be changed to other I/O cells with the compile command. The dont_use attribute is set to input buffers and bidirectional buffers in order to avoid malfunctions with the insert_pads command. For the insert_pads command, see "Automatic addition of output buffers" that follows.

• Automatic addition of output buffers

Current functions of Design Compiler can add Toshiba output buffers with the insert_pads command, but not bidirectional buffers and input buffers. Therefore, when adding bidirectional buffers and input buffers, add them in the source file before logic synthesis or in the gate-level netlist after logic synthesis.

♦ Symbol library substitution

With some series, the symbol libraries of other series can be substituted for these series. Since there is no problem for logic synthesis and timing analysis, symbol library substitution is available.

♦ Hierarchically built megacells (Cell-based IC and embedded array)

In order to make consistency to the SDF file for Design Compiler (.dcsdf) created with Toshiba sing-off system, cell-based ICs and embedded arrays offer the hierarchically built megacells as shown below.

RAMA, RAMB, RAMC, RAMD, RAMF, ROMA and CMPY

♦ YFD-type flip-flops and YLD-type latches

There are FD-type and YFD-type flip-flops, and LD-type and YLD-type latches in the Toshiba library. The YDF-type flip-flops and YLD-type latches are the register types wherein the Q output delay depends on the capacitance loads associated with the QN output. Since this type of register cells makes timing optimization and timing analysis unreliable, set the dont_use attribute which suppresses automatic mapping to these register cells in the library. Toshiba recommends you not to write the YDF-type flip-flops and YLD-type latches in the netlist, and also not to remove the dont_use attribute in the library.

Note: These cells are included in the pre-TC240 gate arrays and embedded arrays, and not included in cell-based IC and TC240 or later series.

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♦ Cells breaking the timing arc

When logic synthesis and timing analysis are performed, timing arcs of the following cells are automatically broken.

YFD2, YFD3, LSR1, LSR1P, LSR2 and LSR2P

Since this type of cells makes logic synthesis considering timing and timing analysis unreliable, set the dont_use attribute which suppresses automatic mapping to these cells in the library. Toshiba recommends you not to write these cells in the netlist, and not to remove the dont_use attribute in the library. The following shows the sample warning message issued when timing arc is broken in YFD2.

Warning: Disabling timing arc between pins ’Q’ and ’QN’ on cell ’YFD2’ to break a timing loop (OPT-314)

Note: These cells are included in the pre-TC240 gate arrays and embedded arrays, and not included in cell-based IC and TC240 or later series.

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CHAPTER 2 Design Environment Setup

This chapter describes how to create the .synopsys_dc.setup file, and set the environment for Design Compiler, and invoke Design Compiler.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Creating the .synopsy_dc.setup File

Before invoking Design Compiler, create the initial setup file named .synopsys_dc.setup by using the template of the .synopsys_dc.setup file which resides in the etc directory. The .synopsys_dc.setup file is read by Design Compiler simultaneously with invocation of Design Compiler.

Specifying Libraries

Figure 2–1 shows the format to specify libraries in the .synopsys_dc.setup file.

Figure 2–1 Format to Specify Libraries

search_path = {<install_path_1> <install_path_2>...}link_library = {<standard_cell_library> <custom_cell_library>...}target_library ={<standard_cell_library>}symbol_library = {tcxxx.workview.sdb}

Note: The sign-off system 1.12 or later supports dc_shell and tcl scripts. This section gives the description based on the dc_shell script. The template contained in the .synopsys_dc.setup file can be used with dc_shell and tcl scripts.

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♦ search_path

Specifies the install paths of libraries.

♦ link_library

Specifies the libraries used to read designs and perform timing analysis. Specifies the standard cell library (tcxxx.db or tcxxx.db<operating_conditon>) and the libraries of custom cells like megacells and analog cells.

♦ target_library

Specifies the standard cell library (tcxxx.db or tcxxx.db<operating_conditon>) to be used with mapping.

♦ symbol_library

Specifies the library containing symbol information of each cell. Specify tcxxx.workview.sbd.

Figure 2–2 shows a part of the template of the .synopsys_dc.setup file, that denotes a part to specify libraries.

Figure 2–2 Sample Template of the .synopsys_dc.setup File to Specify Libraries

############################################################## The sample setup file ## for TOSHIBA Verilog Sign Off System ## ## Please modify this file and include in your setup file. ## 1 Add <DesignCompiler install path>/libraries/syn to ## the search_path. ## 2 Set <install dir> to the directory name of ## installation of this design kit. ## 3 Set <special> to the request based library name. ## Add more libraries if needed. ## 4 Change ítcxxxxí into the suitable technology name. ## ## Do change_names command like an example below. ## ##############################################################

<<omitted>>

# === Single K technology sample === ## set tsb_lib_path { <install dir> <install dir>/tc200c }# set search_path [concat $search_path $tsb_lib_path]## set link_library { "*" tc200c.db tc200c_hmacro.db tc200c_osc_macro.db <special>.db }# set target_library { tc200c.db }# set symbol_library { tc200c.workview.sdb }## === Single K technology sample end ===

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# === Multi K techonology sample === ## set tsb_lib_path { <install dir> <install dir>/tc240c }# set search_path [concat $search_path $tsb_lib_path]# # set link_library {"*" tc240c.db_WCCOM25 tc240ct_io_macro.db special.db_MAX}# set target_library {tc240c.db_WCCOM25}## set_min_library tc240c.db_WCCOM25 -min_version tc240c.db_BCCOM25# set_min_library special.db_MAX -min_version special.db_MIN##set symbol_library {tc240c.workview.sdb}

# === Multi K techonology sample end ===

Bus Variables

For bus pins, designating their individual bits differs between Verilog-HDL and VHDL descriptions. Square brackets [ ] are used in Verilog-HDL, whereas curly brackets { } are used in VHDL. Set bus variables as shown below.

♦ Verilog-HDL

bus_naming_style = "%s[%d]"bus_inference_style = "%s[%d]"bus_extraction_style = "%s[%d:%d]"bus_dimension_separator_style = "]["

♦ Verilog-HDL

bus_naming_style = "%s(%d)"bus_inference_style = "%s(%d)"bus_extraction_style = "%s(%d:%d)"bus_dimension_separator_style = ")("

Variables Used for HDL (VHDL) Output

Different variables are prepared to output Verilog-HDL and VHDL. Output variables affect descriptions in the file generated with the write command.

Verilog-HDL Output Variables

verilogout_single_bit = false 1)verilogout_no_tri = true 2)verilogout_equation = false 3)

1. Set false. When setting true, bus pins are not described as a bus.

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2. Set true. When setting false, primitive cells in the Verilog library are generated.

3. Set false. When setting true, function description is generated.

Variables Used for VHDL Output

vhdlout_single_bit = "VECTOR" 1)vhdlout_preserve_hierarchical_types = "VECTOR" 2)vhdlout_follow_vector_direction = true 3)vhdlout_upcase = true 4)vhdlout_dont_create_dummy_nets = true 5)vhdlout_use_packages = {"<package_statement>"} 6)

1. Set the variable used to write the ports of the top module. You can set USER to maintain consistency to port descriptions in RTL, but USER may generate an unexpected module package in VHDL. Therefore, we recommend to set VECTOR.

2. Set the variable to write the ports of the lower modules. Set VECTOR, that is the same as step 1.

3. Set true. Setting true retains the same bus naming conventions as in RTL descriptions in specifying pin names. When downto is set in RTL, for example, downto is retained in the gate-level netlist.

4. Set true. Setting true outputs the netlist in upper-case, that is required to interface the netlist to VHDL sign-off system.

5. Set true. Setting false generates dummy nets for unconnected output pins. Setting false makes unconnected pins described as unconnected pins in VHDL descriptions. Set the following to output the package statement, which is required of the Toshiba sign-off system.

♦ Variable when a design contains only macrocells, primitive cells and I/O cells

"IEEE.std_logic_1164.all; ibrary tcxxxy; use tcxxxy.all"

When tc220c is set to tcxxxy, for example, the following package statement appears in the netlist.

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; LIBRARY TC220C; USE TC220C.ALL;

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♦ Variable when a design contains megacells and custom I/O cells

Set megacells like RAM and ROM to megacell, and custom I/O cells to specialcell.

"IEEE.std_logic_1164.all; \library tcxxxy; use tcxxxy.all; \library megacell ; use megacell.all; \library specialcell; use specialcell.all"

When tc240c is set to tcxxxy, for example, the following package statement appears in the netlist.

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; LIBRARY TC240C; USE TC240C.ALL;LIBRARY MEGACELL ; USE MEGACELL.ALL;LIBRARY SPECIALCELL; USE SPECIALCELL.ALL;

Internal Bus

Set whether to expand internal bus into individual signal names. When false is set to hdlout_internal_bussed, internal buses are expanded into signals and expressed with their individual bits. When true is set, bus expressions are retained without expansion of buses. This variable is used in both of Verilog-HDL and VHDL. Set false in Verilog-HDL and true in VHDL.

hdlout_internal_bussed = false (Verilog-HDL)

Naming Rule

Specify to change cell instance names and net names based on the naming rule of the sign-off system used after logic synthesis.

Figure 2–3 shows the format to specify naming rule in the .synopsys_dc.setup file.

Figure 2–3 Format to Specify Naming Rule

define_name_rules <rule_name> \ -max_length <max_length_of_occurrence> \ -allowed <allowed_character> \ -restricted <forbidden_character> \ -first_restricted

<forbidden_character_used_at_the_beginning_of_an_occurence_name> \ -last_restricted

<forbidden_character_used_at_the_end_of_an_occurence_name> \ -map { "<name_before_change>" "<name_after_change>" } \ -reserved_words { <name_not_to_be_used> } \ -case_insensitive

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For how to describe naming rule, see define_name_rules included in the template of the .synopsys_dc.setup file. You need to run the change_names command in order to make the contents you set here effective. For the change_names command, see Chapter 4.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Invoking Design Compiler

Setting Path

The following shows the command syntax to set the path.

% set path = ( <Synopsys_install_directory>/ \<architecture>/syn/bin $path )

The following shows an example of the command.

% set path = ( /usr/synopsys/sparcOS5/syn/bin $path )

Invoking Design Compiler

After running the UNIX source command, invoke Design Compiler.

The following describes how to invoke Design Compiler.

♦ General invocation at the dc_shell prompt

% dc_shell

♦ To make Design Compiler read the script file

% dc_shell -f script_filename

♦ To invoke Design Analyzer

% design_analyzer

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Recommended Circuit Structure

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CHAPTER 3 Recommended Circuit Structure

This chapter describes the ASIC circuit structure recommended by Toshiba.

For the detailed descriptions of Toshiba ASIC design, see CMOS ASIC Design Manual.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Basic Circuit Structure

This section describes the basic structures of the top module and one-low level submodule.

Top Module

Figure 3–1shows the recommended structure of the top module. In the top module, describe only I/O cells (input, output and bidirectional buffers), and the one-low level submodule. In the one-low level submodule, describe user-defined logic, RAMs, ROMs, CPUs and IP core cells. Separate the user-defined logic and other cells in different hierarchical levels, that facilitates test logic insertion and test pattern generation of individual blocks.

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Figure 3–1 Top Module (Recommended by Toshiba)

Submodule

Figure 3–2 shows the submodule structure containing a combinational logic block.

As shown "Recommended Circuit Structure" in Figure 3–2, describe a design so that the signal of the module can output from a flip-flop, that facilitates to equal propagation delays between the modules to be logic synthesized and the modules to be connected, and also to estimate the time when the signal inputs into the next module. That makes the set_input_delay, set_output_delay, and set_driving_cell commands be set easily.

In "Unrecommended Circuit Structure", since the signal output from a flip-flop comes into the next module through the combinational logic, it is difficult to estimate when the signal inputs into the next module. Also the signal output from the module through the combinational logic makes optimization difficult.

Note: The recommended structure of the top module depends on the physical layout to be performed in Toshiba. Consult your Design Center engineer beforehand.

Top Module

One-Low Level SubmoduleInput Buffer Output Buffer

Bidirectional

User-Defined Logic

RAM ROM CPU IPAnalog

Cell

DRAM

Buffer

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Figure 3–2 Low-level Module

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Circuit Structure around Megacells

This section describes the circuit structure around magacells like RAMs and ROMs. Since care must be taken in a design containing megacells, see the following manuals provided by Toshiba.

♦ DESIGN-FOR-TEST HANDBOOK

♦ CMOS ASIC Design Manual

♦ MemoryBist Design System

Considering Delays

Since a megacell is placed along the edge of a chip, wire between a combinational logic and a megacell will tend to become long. The delay around a megacell is longer than that around a combinational logic. The following shows how to structure a circuit considering delays.

Module to Be Synthesized

[Recommended Circuit Structure]

[Unrecommended Circuit Structure]

CombinationalLogic

F/F

Next-Step Module

CombinationalLogic

F/F

Module to Be Synthesized

F/F

Next-Step Module

CombinationalLogic

F/FCombinational

Logic

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♦ Connecting a megacell to a flip-flop directly

Connecting a megacell to a flip-flop directly as shown in Figure 3–3 is recommended so that delay around a megacell becomes small when the fast operational speed is required in a design. In this case, buffers used to prevent hold violations and repeater cells used to reduce resistance delays due to wire resistance may be inserted between a megacell and a flip-flop.

♦ Inserting a buffer to a clock signal of a megacell

Since a megacell is placed along the edge of a chip, a clock net runs to a chip. As the results, a clock tree structure becomes unbalanced and skew may be increased. Insert a buffer to the clock signal of a megacell as shown in Figure 3–3 in order to balance skew through the buffer.

Figure 3–3 Circuit Structure Considering Delays

Considering Scan Design and ATPG

The previous section describes that a megacell and a flip-flop must be connected directly. Generally in an actual design, a buffer used to prevent hold violations is inserted between a megacell and a flip-flop. In the design with non-strict timing requirement, a combinational logic is also inserted between them. These circuit structures do not cause the timing problem, but cause the fault coverage problem. The following subsections describes the cause of low fault coverage and the workaround for this problem.

Cause of Low Fault Coverage

Since a megacell is treated as a black box by ATPG, the output of a megacell can not be controlled and is treated as "X." When the output of a megacell is input to a combinational logic, the fault coverage for the combinational logic decreases.

F/F F/F

Megacell

Buffer(Used to prevent hold violations and repeater cell)

Buffer(Balance clock skew)XCTS

Clock

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The signals input to a black box can not be monitored, either. When the output of a combinational logic becomes an input to a megacell directly by bypassing a flip-flop, the signal which comes from the combinational logic to a megacell can not be monitored, resulting in low fault coverage.

Workaround for Low Fault Coverage

Figure 3–4 shows the design considering scan design and ATPG. Add a wandering net to bypass a megacell so that fault coverage may not be decreased. Add the branch net at the point between a combinational logic and a megacell, and insert a multiplexer between a megacell and the next combinational logic. The TMODE signal is used to switch the path to propagate a signal. With the TMODE signal, a signal is propagated from a combinational logic to a megacell directly in normal operation mode. In scan test mode, a signal bypasses a megacell. Since the latest DFT tool automatically adds a wandering net to bypass a megacell, use this workaround if required.

Figure 3–4 Design Considering Scan Design and ATPG

Megacell Test

When a design contains megacells, megacells are fully functionally tested before shipping of ASICs. You need to create test logic required to test megacells. There are two methodologies applicable to megacells: the direct access approach (multiplexing approach) and BIST.

♦ Direct access methodology (Multiplexing approach)

Isolate a megacell from the rest of the design with a multiplexing logic and test a megacell directly from outside of ASIC. The customer needs to add test logic.

F/F F/F

Megacell

TMODE

CombinationalLogic-3

MUX

In normal operation modeIn scan test mode

Clock



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♦ Built In Self Test (BIST)

Insert BIST logic with Toshiba Memory BIST for testing megacells. Since Toshiba inserts BIST logic using the netlist the customer submitted, BIST logic is transparent to the customer.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Circuit Structure around I/O Cells

This section describes the circuit structure around I/O cells.

Considering Delays

Since I/O cells are located along four edges of a device, wires connecting I/O cells and internal cells tend to become long. Connecting I/O cells to flip-flops directly without inserting combinational logics is recommended so that the fast operational speed (operation at a high frequency) can be achieved. You may insert buffers used to prevent hold violations and repeater cells used to decrease resistance delays between I/O cells and flip-flops.

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Figure 3–5 Design Structure around I/O Cells

Considering JTAG Boundary-Scan Design

Current Toshiba DFT tool can not insert boundary-scan resister cells (BSR cells) when I/O cells are not placed on the top level, but lower hierarchical level. When you use JTAG boundary-scan, place I/O cells on the top hierarchical level.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Forbidden Designs

This section describes forbidden designs. For the forbidden designs other than those shown in this section, consult your Toshiba design center engineer.

Input Buffer

[Input]

Output Buffer

[Output]

[Bidirectional]

Bidirectional Buffer

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Unconnected Input Pins

Unconnected input pins of modules and unconnected input pins of cells are disallowed. When Design Compiler reads RTL coding or gate-level netlist containing unconnected input pins, unconnected pins are automatically connected to ground, resulting in logic 0. Ensure that there is no unconnected input pin before logic synthesis. When an unconnected pin is found, the check_design and compile commands of Design Compiler issue the following message.

Warning: In design ’test2’, input pin ’A’ of cell ’INST1’ was left unconnected. Logic 0 assumed. (LINT-0)

Wired-ORed Connection

Wired-ORed connections are disallowed. When wired-ORed net description is found, the check_design and compile commands of Design Compiler issue the following message.

♦ check_design command

Information: In design ’test3’, net ’Z’ has multiple drivers. Wired AND assumed. (LINT-4)

♦ compile command

Information: In design ’test3’, there is 1 wired-AND net. (LINT-44)

Pass-Through Nets and Multiple-Port Nets

Pass-through nets which pass through a module without connecting to a cell, and multiple pot net, that a single net connected to multiple pins, are disallowed. Use the set_fix_multiple_port_nets command to prevent these nets. For sample execution, see "Pass-Through Nets and Multiple Port Nets" on page 47.

Feed-Back Loop of Combinational Logic

Do not create feed-back loop consisting of combinational logics only. Since Design Compiler can not calculate correctly delays of feed-back loop consisting of combinational logics, optimization function decreases, that causes malfunction of timing in the generated circuit. Placement and routing considering timing for feed-back loop can not be performed. When net description containing feed-back loop is found, the check_design and compile commands of Design Compiler issue the following message.

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Information: Timing loop detected. (OPT-150) INST1/B INST1/Z INST2/A INST2/Z INST3/A INST3/Z

Warning: Disabling timing arc between pins ’B’ and ’Z’ on cell íINST1í to break a timing loop (OPT-314)

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Part 2

Running Toshiba

Design Compiler

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Logic Synthesis and Optimization

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CHAPTER 4 Logic Synthesis and Optimization

This chapter describes the Design Compiler commands used for logic synthesis and optimization of which use requires care to develop Toshiba ASICs. For other commands, see "Logic Synthesis and Optimization Script" on page 51 and the manuals provided by Synopsys..

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Selecting a New Wire Load Model

Select an appropriate wire load model for the array being used with the set_wire_load_model command at the time of logic synthesis. Specifying the wire load model enables Design Compiler to calculate delays by using estimated wire lengths based on the wire loads of the array being used.

Specify a new wire load model with net area parameter to make Design Compiler perform logic synthesis taking net interconnects into account, that facilitates layout of the synthesized design. Select the wire load model name presented on the "Appendix H Toshiba ASIC Product Lines" in CMOS ASIC Design Manual. The "Array Type" column in the table indicates the wire load model name. The names of wire load models with net area parameters end with the characters "_W".

Note: This chapter discusses the methodology of timing optimization using both the worst-case and the best-case operating conditions.

Note: The sign-off system 1.12 or later supports dc_shell and tcl scripts. This section gives the description based on the dc_shell script. For execution with tcl script, see the manual provided by Synopsys.

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When the wire load model is used, drive limit value is also calculated.

Command Syntax

The following shows the command syntax at a dc shell prompt.

dc_shell> set_wire_load_model -name wire_load_model

Example

The following shows an example of the command to specify the wire load model T3S60_W with net area parameter for TC220C040 array type.

dc_shell> set_wire_load_model -name T3S60_W

Net Area

Use the report_area command to check the individual areas of your design. Figure 4–1 shows the execution results of the report_area command when the wire load model with net area is used. Where, "Net Interconnect area" indicates the value used by Design Compiler only, which is obtained with the number of fanouts of each net and wire loads. "Total area" indicates the value including "Net Interconnect area". Note that "Net Interconnect area" can not be used to check ease of layout since this information is used for logic synthesis considering net area.

Figure 4–1 Report_area Execution Results

Combinational area : 10841.000000Noncombinational area : 9764.000000Net Interconnect area : 25267.804688Total cell area : 20605.000000Total area : 45872.804688

Note: Wire load modes with net area parameters are usable only in Design Compiler. When specifying an array used by the sign-off simulator, you cannot specify the array name ending with the character "_W".

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .K-Factor

Specify the K-factor with the set_operating_conditions command at the time of logic synthesis. Timing is optimized so that a design can behave with the specified K-factor.

Design Compiler of v1998.02 or later can perform optimization simultaneously using both the worst-case and the best-case operating conditions. When performing optimization using these conditions, you need to run the set_min_library command before the set_operating_conditions command.

Multiple K-Factors (TC203 or Later Series Libraries)

Settings in the .synopsys_dc.setup File

When the library contains multiple files for individual operating conditions, specify the worst-case library file to lin_library and target_library. In the case of the library containing a single library file, you also need to specify the file to lin_library and target_library.

Command Syntax

Run the set_min_library command using the best-case and worst-case library files. Next, run the set_operating_conditions command. The following shows the command syntax.

dc_shell> set_min_library worst_case_library \-min_version best_case_library

dc_shell> set_operating_conditions \-max worst_case_name -max_libary worst_case_library \-min best_case_name -max_libary best_case_library \

Command Example


Note: The K-factor values vary depending on the package, the number of gates, switching frequency, signal switching activity ratio, supply voltage and operating temperature of an ASIC to be developed. For the K-factor, ask Toshiba ASIC design center engineering staff.

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dc_shell> set_min_library tc240c.db_MAX -min_version \tc240c.db_min

dc_shell> set_min_library tc240C.db_MAX \-min_version TC240C_MACRO.db_MIN

dc_shell> set_min_library tc240C_IO.db_MAX \-min_version TC240C_IO.db_MIN

dc_shell> set_operating_conditions \-max MAX -max_library tc240c.db_MAX:tc240c \-min MAX -min_library tc240c.db_MIN:tc240c

Single K-factor (TC190 and TC200 Series Libraries)

Settings in the .synopsys_dc File

There is only one type of the library file. Specify it to link_library and target_library.

Command Syntax

The following shows the command syntax. Run the set_operating_conditions command only. The set_min_library command is not required.

dc_shell> set_operating_conditions \-max worst_case_name \-min best_case_name

Command Example


dc_shell> set_operating_conditions -max WCMIL25 \-min BCCOM25

Checking Operating Conditions

Run the following command to check the operating conditions you specified.

dc_shell> report_design

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clock Signals

This section describes how to set clock signals.

Setting Clock Waveforms (create_clock)

When a logic has a clock input, specify the clock pin name and clock waveform with the create_clock command. By specifying the clock signal for logic synthesis, optimization is performed so that the design can behave by the clock with operating clock frequency and rising/falling edges you intended. If a logic has two or more clock inputs, run the create_clock command for individual clock signals.

Command Syntax

The following shows the command syntax.

dc_shell> create_clock clock_signal -period period \-waveform {rising_edge_time falling_edge_time} \ -name reference_name

where,

-period period

Specifies the clock period.

-waveform {rising_edge_time falling_edge_time}

Specifies the times of rising and falling edges of a clock signal.

-name reference_name

Specifies an arbitrary reference name to the clock signal.

Command Example

Below is an example of the create_clock command. Set clock period to 20 ns, with a rising edge at 0 ns and falling edge at 10 ns, and reference name SYSCLK to the clock pin CLK.

dc_shell> create_clock CLK -period 20 -waveform { 0 10 } \-name SYSCLK

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Suppressing Addition of Clock buffers to a Clock Signal (set_dont_touch_network)

When subclock buffers reside on a clock signal, CTS can not be performed. Use the set_dont_touch_network command to suppress addition of subclock buffers to a clock signal. Running the set_dont_touch_network command sets the dont_touch attribute to the net between the specified pin and a flip-flop, and suppresses addition of buffers to the clock signal.


dc_shell> set_dont_touch_network clock_signal

Setting Clock Skews (set_clock_uncertainty, set_fix_hold)

Skews Caused by the Same Clock Driver

Run the set_clock_uncertainty and set_fix_hold commands at logic synthesis to set clock skews, that enables you to synthesize a design containing no timing violation.

Setting clock skew is required for timing optimization using the best-case and worst-case operating conditions. For all technology series of all master slice types, we recommend to set 0.3 ns to the skew caused by the same clock under best-case, typical-case and worst-case operating conditions.

The setup time is automatically optimized by setting clock skew. In order to avoid hold violations, you must run the set_fix_hold command as well as setting of clock skew. Set the best-case operating condition in order to avoid hold violations caused by the same clock driver.


dc_shell> set_clock_uncertainty clock_skew \clock_signal

dc_shell> set_fix_hold clock_signal

Note: Specify uncertainty in the clock network delays as a way of incorporating a margin of error in the design to account for possible increase of the data path delay due to layout. We recommend to set 10 % margin. In the case of 20 ns clock cycle, for example, specify 18 ns.

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As shown in Figure 4–2, delay cells for timing adjustment are inserted to the part such as a shift-register that is prone to hold violations so that the delay of the data path can become larger than clock skew.

Figure 4–2 Insertion of Delay Cells to Data Path

Skews Caused by Different Clock Drivers

Design Compiler v199.05 or later enables you to set clock slew caused by different clock drivers.


dc_shell> set_clock_uncertainty clock_skew \-from clock_signal_1 -to clock_signal_2

Setting Delay to Gated Clock (set_propagated_clock)

When a clock signal is not connected directly to the clock input of a flip-flop such as a gated clock signal in the module to be logic synthesized, use the set_propagated_clock command to perform logic synthesis considering clock delays. That makes Design Compiler perform timing optimization of the clock signal in a data path.


dc_shell> set_propagated_clock clock_signal

[Data path connected directly to registers]

[Delay cells inserted to the data path between registers]

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Reset Signal

Suppressing Addition of Buffers to the Reset Signal (set_dont_touch_network)

Unlike clock signals, reset signals require neither a run of the create_clock command since a waveform does not need to be specified, nor the set_clock_uncertainty command since skews do not cause problems.

CTS is performed with reset signals as well as clock signals at the layout stage. Use the set_dont_touch_network command to suppress addition of buffers to reset signals. Running the set_dont_touch_network command sets the dont_touch attribute to the net between the specified pin and a flip-flop, and suppresses addition of buffers to reset signals.


dc_shell> set_dont_touch_network reset_signal

Notes on Synchronous Reset Signals

Run the set_dont_touch command, but not the set_dont_touch_network command, for the signal which comes to a flip-flop through a gate such as a synchronous reset signal. The set_dont_touch_network command sets the dont_touch attribute to the reset signal before a flip-flop. Therefore, when the reset signal is combined with a logic gate before the reset signal comes to a flip-flop, RTL codes are converted to gate-level netlists with logic synthesis, but optimization considering capacitance loads may not be performed.


dc_shell> set_dont_touch find(net, reset_signal)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Considerations on DFT

The section discusses notes required for logic synthesis during logic design considering Design-For-Test (DFT). For RTL coding, see Chapter 3. For more detailed descriptions, see the DFT-related manuals.

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Avoiding Mapping of Specific Registers

When performing scan conversion after logic synthesis, you need to exclude scan flip-flops and standard flip-flops which can not be converted to scannable versions during logic synthesis from sequential mapping. This is because scan conversion can not be performed if these flip-flops exist.

When you run the set_dont_use command to specify the scan flip-flops and flip-flops which can not be converted to scannable versions, the dont_use attribute is set to these flip-flops to avoid mapping of these flip-flops. This command may be set in the .synopsys_dc.setup file.

The following shows the command syntax. The flip-flops to be specified vary depending on the technology series.

♦ TC190G, TC200G/E, TC203G/E, TC220G/E, TC223G/E(The technology series needs to be modified.)

dc_shell> set_dont_use { tc220g/FJK* tc220g/FT* \ tc220g/YFD* tc220g/FD*S* }

♦ TC240E

dc_shell> set_dont_use { tc240e/GFJK* tc240e/GFT* \ tc240e/GFD*E* tc240e/GFD*SF* tc240e/GFD*Q* \tc240e/GFDN* }

♦ TC260E

dc_shell> set_dont_use { tc240e/GFJK* tc240e/GFT* \ tc240e/GFD*E* tc240e/GFD*SF* tc240e/GFD*Q* \tc240e/GFDN* }

♦ TC190C, TC200C, TC203C, TC220C, TC223C(The technology series needs to be modified.)

dc_shell> set_dont_use { tc203c/FSR* tc203c/FJK* \ tc203c/FT* tc203c/FDN* tc203c/FD*Q* tc203c/FD*R \ tc203c/FD*E* tc203c/FD*SF* tc203c/FD3 \tc203c/FD3P }

♦ TC220C, TC222C, TC223C(The technology series needs to be modified.)

dc_shell> set_dont_use { tc220c/FSR* tc220c/FJK* \tc220c/FT* tc220c/FDN* tc220c/FD*Q* tc220c/FD*R \tc220c/FD*E* tc220c/FD*SF* tc220c/FD3 \tc220c/FD3P tc220c/FD12* tc220c/FD14* }

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♦ TC240C, TC260C(The technology series needs to be modified.)

dc_shell> set_dont_use { tc240c/CFT* tc240c/CFD*E* \tc240c/CFD*SF* tc240c/CFD*Q* tc240c/CFDN* }

Table 4–1 shows Toshiba scan flip-flops and standard flip-flops which can be replaced to equivalent scan flip-flops.

Table 4–1 Toshiba Flip-Flops

Series DFT Style or Flip-Flop Flip-Flop

TC190G/ETC200G/ETC203G/ETC220G/ETC223G/E

Single-clock internal scan design FD1S(P), AFD2S(P), AFD3S(P), AFD4S(P)

Dual-clock internal scan design FD1(P), AFD2(P), AFD3(P), AFD4(P)

F/Fs replaced to scan version FD1(P), AFD2(P), AFD3(P), AFD4(P)

TC240E

Single-clock internal scan designGFD1EX2/X4, GFD2EX2/X4, GFD3EX2/X4, GFD4EX2/X4

Dual-clock internal scan designGFD1SFX2/X4, GFD2SFX2/X4, GFD3SFX2/X4, GFD4SFX2/X4

F/Fs replaced to scan versionGFD1X2/X4, GFD2X2/X4, GFD3X2/X4, GFD4X2/X4

TC260E

Single-clock internal scan designGFD1EX1/X2/X4, GFD2EXX1/2/X4, GFD3EX1/X2/X4, GFD4EX1/X2/X4

Dual-clock internal scan designGFD1SFX1/X2/X4, GFD2SFX1/X2/X4, GFD3SFX1/X2/X4, GFD4SFX1/X2/X4

F/Fs replaced to scan versionGFD1X1/X2/X4, GFD2X1/X2/X4, GFD3X1/X2/X4, GFD4X1/X2/X4

TC190CTC200CTC203CTC220CTC223C

Single-clock internal scan design FD1E, FD2E, FD3L1E, FD4E

Dual-clock internal scan designFD1SF(P), FD2SF(P), FD3L1SF(P), FD4SF(P)

F/Fs replaced to scan version FD1(P), FD2(P), FD3L1(P), FD4(P)

TC240CTC260C

Single-clock internal scan design

CFD1EX1/X2/X4/XL, CFD2EX1/X2/X4/XL, CFD3EX1/X2/X4/XL, CFD4EX1/X2/X4/XL, CFD1EAX1/X2/X4/XL, CFD2EAX1/X2/X4/XL, CFD3EAX1/X2/X4/XL, CFD4EAX1/X2/X4/XL

Dual-clock internal scan design

CFD1SFX1/X2/X4/XL, CFD2SFX1/X2/X4/XL, CFD3SFX1/X2/X4/XL, CFD4SFX1/X2/X4/XL

F/Fs replaced to scan versionCFD1X1/X2/X4/XL, CFD2X1/X2/X4/XL, CFD3X1/X2/X4/XL, CFD4X1/X2/X4/XL

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• TC190C, TC200C, TC203C and TC220 technology series have no power type cell of flip-flops for single-clock internal scan design. The flip-flops which can be replaced to scan flip-flops for single-clock internal scan design are FD1, FD2, FD3L1 and FD4.

• TC190C, TC200C, TC203C, TC220 and TC223 technology series have FD3 other than ED3L1 as a flip-flop with set/reset. However, FD3 is excluded since it can not be replaced to a scan flip-flop.

TC280C

Single-clock internal scan design

CFD1EX1/X2/X4/XL(H)(V), CFD1EQX1/X2/X4/XL(H)(V), CFD1MEX1/X2/X4/XL(H)(V), CFD1MEQX1/X2/X4/XL(H)(V), CFD2EX1/X2/X4/XL(H)(V), CFD2EQX1/X2/X4/XL(H)(V), CFD3EX1/X2/X4/XL(H)(V), CFD4EX1/X2/X4/XL(H)(V), CFD5MEX1/X2/X4/XL(H)(V), CFD5MEQX1/X2/X4/XL(H)(V)

Dual-clock internal scan design

CFD1SFX1/X2/X4/XL(H)(V), CFD1SFQX1/X2/X4/XL(H)(V), CFD1MSFX1/X2/X4/XL(H)(V), CFD1MSFQX1/X2/X4/XL(H)(V), CFD2SFX1/X2/X4/XL(H)(V), CFD2SFQX1/X2/X4/XL(H)(V), CFD3SFX1/X2/X4/XL(H)(V, CFD4SFX1/X2/X4/XL(H)(V, CFD5MSFX1/X2/X4/XL(H)(V, CFD5MSFQX1/X2/X4/XL(H)(V)

F/Fs replaced to scan version

CFD1X1/X2/X4/XL(H)(V), CFD1QX1/X2/X4/XL(H)(V), CFD1MX1/X2/X4/XL(H)(V), CFD1MQX1/X2/X4/XL(H)(V), CFD2X1/X2/X4/XL(H)(V), CFD2QX1/X2/X4/XL(H)(V), CFD3X1/X2/X4/XL(H)(V), CFD4X1/X2/X4/XL(H)(V, CFD5MX1/X2/X4/XL(H)(V), CFD5MQX1/X2/X4/XL(H)(V)

Series DFT Style or Flip-Flop Flip-Flop

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Considerations on JTAG Boundary Scan

When JTAG boundary scan is used, boundary scan register (BSR) cells are inserted automatically, resulting in increase of the delay for I/O cells. The delay of a multiplexer is added at the minimum by insertion of BSR cells. Care must be taken in timing of I/O cells in your design before insertion of BSR cells.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Megacells

Megacells like RAMs and ROMs, hard macrocells and analog cells can not be mapped by logic synthesis. You need to add structural descriptions of them in your RTL code.

Figure 4–3 shows an example of RTL code for RAMD (64-word × 5-bit) of TC220C series. This example represents RTL code in the explicit format. Toshiba recommends the explicit format because connection between cell pins and signals are described explicitly, that is useful for avoiding connecting mistakes.

Figure 4–3 Sample RTL Code of a Megacell

[Verilog-HDL]

AD6005A INST1( .CE(CE), .RW(RW), .A0(AA0), .A1(AA1), .A2(AA2), .A3(AA3), .A4(AA4), .A5(AA5), .I0(II0), .I1(II1), .I2(II2), .I3(II3), .I4(II4), .O0(OO0), .O1(OO1), .O2(OO2), .O3(OO3), .O4(OO4) )

[VHDL]

component AD6005A port( CE, RW : in std_logic; A0, A1, A2, A3, A4, A5 : in std_logic; I0, I1, I2, I3, I4, I5 : in std_logic; O0, O1, O2, O3, O4 : out std_logic );end component;INST1:AD6005A port map( CE=>CE, RW=>RW, A0=>AA0, A1=>AA1, A2=>AA2, A3=>AA3, A4=>AA4, A5=>AA5, I0=>II0, I1=>II1, I2=>II2, I3=>II3, I4=>II4, I5=>II5, O0=>OO0, O1O=>OO1, O2=>OO2, O3=>OO3, O4=>OO4 );

Note: For the detailed descriptions of design-or-test, see DESIGN-FOR-TEST HANDBOOK.

Note: The information of megacells is contained in Toshiba data book. When you describe megacells, check cell names, pin name and the number of pins in the data book.

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I/O Cells

Inserting I/O Cells

Like megacells, I/O cells can not be mapped by logic synthesis. Insert I/O cells by the following processing.

♦ Input and bidirectional buffers

Describe gate-level cells in RTL code.

♦ Output buffers

Insert output buffers with the insert_pads command.

Describing Gate-Level Cells in RTL Code

Figure 4–4 shows an example of RTL code to insert input and bidirectional buffers.

Figure 4–4 Sample RTL Code

[Verilog-HLD]

IBUF INST1( .Z(SYSCLK_I), PO(), .A(SYSCLK), .PI(1bí0), );B4 INST2( .Z(DO), .A(D) );

[VHLD]

compopnent IBUF port(Z, PO : out std_logic A, PI : in std_logic; );end component;compopnent B4 port( Z : out std_logic; A : in std_logic );end component;signal NC_0 : std_logic;begin NC_0 <= ’0’; INST1:IBUF port map( A=>SYSCLK, PI=NC_0, Z=>SYSCLK_I, PO=>OPEN ); INST2 : B4 port map( A=>D, Z=>DO );

Note: The insert_pads command of Design Compiler can insert output buffers only, but not input and bidirectional buffers.

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Using the insert_pads Command

Use the insert_pads command to insert output buffers. When the set_pad_type command is run before the insert_pads command, the port_is_pad attribute is set to these output buffers automatically.


dc_shell> set_pad_type -exact output_buffer output_pindc_shell> insert_pads

Logic Synthesizing Modules Containing I/O Cells

The following settings are required to perform logic synthesis of modules containing I/O cells.

Setting dont_touch to the Nets Connected to External Pins

Set the dont_touch attribute to the net connected to the external pin, that is presented with a bold line in Figure 4–5, to prevent insertion of buffers to the net.

Figure 4–5 Net Set with the dont_touch Attribute


dc_shell> set_dont_touch find(net, all_inputs())dc_shell> set_dont_touch find(net, all_outputs())

[Input Buffer]

[Bidirectional Buffer]

[Output Buffer]

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Setting Loads to External Pins

Set capacitance loads to external pins. Set only external capacitance loads of ASIC to external output and bidirectional pins. When the set_wire_load_model command is run, net loads are set to the nets connected to the output pins, that are presented with bold line in Figure 4–5. You must delete these net loads.


dc_shell> set_load output_load external_pin→ Set net load to extenal pin.

dc_shell> set_load 0 find( net, net_name )→ Delete net load of the specified net.

Setting Input Slews of External Pins

Set the input slew of an external signal. When an internal module is synthesized, specifying a cell with the set_driving_cell command sets output slew of that cell as the input slew rates on the driven cell. However, since an external input signal is the output from other IC, you need to specify input slew. The default input slew is 0 ns.


dc_shell> set_input_transition input_slew input_pin

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Pass-Through Nets and Multiple Port Nets

Before running the compile command, run the set_fix_multiple_port_nets command to suppress generation of pass-through nets and multiple-port nets. The following example specifies all modules on the hierarchy level specified with current_design in the script file and lower level.

dc_shell> set_fix_multiple_port_nets -all \-buffer_constants

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Interface to Other EDA Tools

This section discusses settings required to interface your design to other EDA tools after logic synthesis and optimization.

Setting Variables in the .synopsys_dc.setup File

The setting methodology for some of the variables described in the .synopsys_dc.setup file differ depending on the language used in the sign-off simulator to be used after logic synthesis. For the detailed description, see page 5 and page 17.

Name Change

Run the change_names command to change instance names, and net names before generating the gat-level netlist. Run the report_names command to check the instance names and net names before a run of the change_names command.


dc_shell> report_names -rules rule [-hierarchy]dc_shell> change_names -rules rule [-hierarchy]

where,

-rules rule Specifies the name change rule. The name change rule "toshiba" and "toshiba_port" are defined in the template of the .synopsys_dc.setup file. "toshiba" is the rule applied to the ASIC internal circuits. "toshiba_ports" is the rule applied to external pins of ASIC. When specifying toshiba, you must specify the -hierarchy option. When specifying toshiba_ports, you must specify the top module of ASIC with current_design in the script file and run the command without the -hierarchy option.

-hierarchy Specify this option when name changes are made in all modules existing on the specified hierarchy level or lower level. When toshiba_ports is specified with -rules, do not specify this option.

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Design Verification

Run DVER which is the verification tool included in Toshiba sign-off system to verify the design after logic synthesis. Design Compiler can perform rough verification. This section describes the items to be verified with Design Compiler.

Checking Areas

Use the report_area and report_reference commands to check the areas of the modules on the hierarchy level specified with current_design in the script file and lower level. The report_area command reports "Net Interconnect area" as well as "cell area", as shown in Figure 4–1. Unlike DVER, all cells all of whose outputs are unconnected are not deleted automatically, that may cause difference from the result of DVER. For area units, see Table 1–9 on page 11.

dc_shell> report_areadc_shell> report_reference

Checking Design Structure

The report_hierarchy command displays the structure of the module on the hierarchy level specified with current_design in the script file and lower level. The cells used in the design, that indicates the cells being mapped, are also displayed.

dc_shell> report_hierarchy

Displaying Port Names

The report_port command displays the names of ports on the hierarchy level specified with current_design in the script file. The report_port command also displays the pin attribute in and out.

dc_shell> report_port

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Displaying Cell Names

The report_cell command displays the names of cells on the hierarchy level specified with current_design in the script file. The report_port command excludes the cells in lower level modules.

dc_shell> report_cell

Displaying Net Names

The report_net command displays the names of nets on the hierarchy level specified with current_design in the script file. The report_port command excludes the nets of lower level modules.

dc_shell> report_cell

Checking Connection to Clock Signal

Use the following command to check connection between the pin set to the clock signal and an internal cell.

dc_shell> report_transitive_fanout -clock_tree

Checking Drive Limit Violations

Use the following command to check drive limit violations. You need to specify the top module with current_design in the script file, and the wire load model with the set_wire_load command.

dc_shell> report_constraints -all_violators

Checking Design Information

Use the following command to check the wire load model and operating condition (K-factor).

dc_shell> report_design

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Logic Synthesis and Optimization Script

This section presents an example .synopsys_dc.setup file, and script used for logic synthesis and optimization.

♦ Top module name: TOP

♦ Wire load model name: T8H39QW8_W

♦ Operating condition:Worst-case operating condition = MAXBest-case operating condition = MIN

♦ Clock signal name, operating frequency, time at rising edge/time at falling edge: CLK, 50 MHz, 0 ns/10 ns

♦ Reset signal name: RST

♦ Data signal names (input signals except clock and reset signals): A, B, C

♦ External capacitance load: 100 pF

Figure 4–6 shows an example of the .synopsys_dc.setup file.

Figure 4–6 Sample .synopsys_dc.setup File

...tsb_lib_path = { . /usr/Synopsys/toshiba /usr/Synopsys/toshiba/tc260e }search_path = search_path + tsb_lib_pathlink_library = { tc260e_wire_load.db tc260e.db_MAX \ TC260E_MACRO.db_MAX \ tc260eq_io_macro.db tc260e_io.db_MAX }target_library = { tc260e.db_MAX }symbol_library = { tc260e.workview.sdb }

set_dont_use { tc260e/GFJK* tc260e/GFT* tc260e/GFD*E* \ tc260e/GFD*SF* tc260e/GFD*Q* tc260e/GFDN* }

define_name_rules toshiba ... bus_naming_style = "%s[%d]"bus_inference_style = "%s[%d]"bus_extraction_style = "%s[%d:%d]"bus_dimension_separator_style = "]["hdlout_internal_busses = falseverilogout_single_bit = falseverilogout_no_tri = trueverilogout_equation = false...

Figure 4–7 shows an example of the script for logic synthesis and optimization. The commands specified in the script file can be entered at the dc_shell prompt. You need to modify the script depending on design specifications.

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Figure 4–7 Sample Script

read -f verilog TOP.v 1)current_design TOP 2)set_wire_load_model -name T8H39QW8_W 3)set_min_library tc260e.db_MAX -min_version tc260e.db_MIN 4)set_min_library TC260E_MACRO.db_MAX \ 5) -min_version TC260E_MACRO.db_MINset_operating_conditions -max MAX -min MIN \ 6) -max_library tc260e.db_MAX:tc260e \ -min_library tc260e.db_MAX:tc260ereport_design 7)create_clock -name CLK -period 18 -waveform { 0 9 } CLK 8)set_clock_uncertainty 0.3 CLK 9)set_fix_hold CLK 10)set_clock_latency 4.0 CLK 11)set_dont_touch_network CLK 12)set_dont_touch_network RST 13)set_driving_cell -cell GFD2X2 -from CP -pin Q -library \ 14) tc260e all_inputs() - { CLK RST }set_driving_cell -cell GCLKBFX4 -library tc260e { CLK RST } 15)set_load 100 all_outputs() 16)set_input_delay 3 -clock CLK { A, B, C } 17)set_output_delay 15 -clock CLK all_outputs() 18)set_flatten false -design TOP 19)set_structure true -design TOP -boolean false -timing true 20)uniquify 21)set_fix_multiple_ports_net -all -buffer_constant 22)compile -map_effort medium 23)ungroup -all -flatten 24)compile -map_effort medium -incremental_mapping 25)report_names -hierarchy -rules toshiba > changed_names.rep 26)change_names -hierarchy -rules toshiba 27)write -f db -hi -o TOP_syn.db 28)write -f vhdl -hi -o TOP_syn.v 29)check_design 30)report_area 31)report_reference 32)report_design 33)report_clock 34)report_hierarchy 35)report_transitive_fanout -from CLK 36)report_transitive_fanout -from RST 37)report_constraints -all_violators 38)report_timing -delay max -transition_time -net -input \ 39) -max_paths 10report_timing -delay max -transition_time -net -input \ 40) -max_paths 10quit 41)

1. Specifies the Verilog library file to be read.

2. Specifies the hierarchy level to be synthesized and optimized.

3. Specifies the wire load model.

4. Specifies the best-case operating condition library containing standard cells which is used with timing optimization using best-case and worst-case operating conditions.

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5. Specifies the worst-case operating condition library containing megacells which is used with timing optimization using best-case and worst-case operating conditions.

6. Specifies the K-factor libraries released by custom requirements to the worst-case and best-case operating conditions.

7. Reports the specified wire load model and operating condition.

8. Sets the clock period and times at rising and falling edges.

9. Sets clock skew.

10. Specifies optimization of the minimum delay, that is hold time.

11. Specifies the clock delay. Ask Toshiba design center engineer about it since the clock delay is obtained with the physical layout results or derived from practical data.

12. Suppresses insertion of buffers to clock signals by considering CTS during physical layout stage.

13. Like clock signals, suppresses insertion of buffers to reset signals by considering CTS during physical layout stage.

14. Specifies the output signal of a cell connected to the driven input pin other than CLK and RST of a driven cell. It is assumed that Q of GFD2X1 is connected.

15. Specifies the output signal of a cell connected to the driven CLK and RST. It is assumed that GCLKBFX4 cell (clock buffer cell) is connected since CLK and RST are excluded from CTS.

16. Specifies capacitance load to the output pin of a module.

17. Specifies input delay to the input pin of a module except CLK and RST.

18. Specifies output delay to the output pin of a module.

19. to 20.Sets optimization algorithm. Specify false to "set_flatten". Specifies true to "set_structure" with some options.

21. When the same module is used multiple times on the hierarchy level specified with current_design in the script file or lower level, makes Design Compiler regard individual module as a different one.

22. Suppresses generation of pass-through nets and multiple port nets.

23. Performs logic synthesis and optimization.

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24. Flattens the modules on the hierarchy level specified with current_design in the script file or lower level. You may specify a logic operation block generated with Design Compiler with ungroup.

25. Performs optimization for the redundant part of a circuit generated with ungroup. This example performs incremental optimization by using options.

26. to 27.Changes the names of instances of cells and nets based on the name change rule defined with define_name_rules in the .synopsys_dc.setup file. In this example, the rule of name change is "toshiba". report_name displays the listing of instance names and net names to be changed, and change_name changes their names.

28. Outputs the logic synthesized and optimized design in db format.

29. Outputs the logic synthesized and optimized design in Verilog-HDL format.

30. to 40.Runs the various types of the report command.

41. Terminates Design Compiler.

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CHAPTER 5 Static Timing Analysis

This chapter describes preparations for static timing analysis (STA) and static timing analysis performed by PrimeTime.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Overview

Toshiba recommends to run STA for a design logic synthesized with Design Compiler because timings of most paths in a synchronous design can be analyzed in a short time before simulation.

Through this manual, logic synthesis and optimization performed by Design Compiler are discussed. This chapter describes static timing analysis performed by PrimeTime as well as Design Compiler. For the detailed description of STA, see the manual provided by Synopsys.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Timing Analysis Procedures

This section describes timing analysis procedures. For the details, see Toshiba Sign-Off System manuals.

Creating the DCSDF File (.dcsdf)

The following shows how to create the DCSDF file (.dcsdf) which is the SDF file for Design Compiler and PrimeTime. In this section, the SDF file (.sdf or .esdf) indicates the SDF file used for simulation.

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1. Set the tsb.config file.

Setting systemselect=DC in the *DCAL section of the tsb.config file generates the DCSDF file during DCAL. Setting sdfsw=ON generates the SDF file along with DCSDF file. Since the generated SDF file can not be used with simulation, set sdfsw=OFF to suppress generation of unrequired SDF file. Figure 5–1 shows an example of options specified in the tsb.config file.

Figure 5–1 Sample tsb.config file

...*DCALsystemselect = DCsdfsw = OFF...

Set the delay condition by specifying the condition, kf_temp and kf_volt options other than the above options. For the details, see the chapter on DCAL of the Sign-Off System Command Reference.

2. Creating the IOPARAM file.

Set output capacitance loading on output buffers, the type of capacitance load of the driven device (CMOS or TTL), and input buffer’s slew rates in the IOPARAM file. DCAL takes the IOPARAM file as input and generates the DCSDF file. When the IOPARAM file is not used, the default values are applied. For the IOPARAM file, see Sign-Off System Command Reference.

3. Run DCAL.

After creating the tsb.config file and IOPARAM file, run DCAL. The following shows the command syntax.

% dcal ioparam = IOPARAM_filename

When the IOPARAM file is not used as input, the ioparam option is not required. In the case that the IOPARAM filename is set in the tsb.config file, it is not required either.

Reading the DCSDF File

Design Compiler or PrimeTime reads the DCSDF file generated with DCAL. Before reading the DCSDF file, make Design Compiler or PrimeTime read the netlist. You need to specify the hierarchy level to be current_design in a script.

The following shows the command syntax for Design Compiler and PrimeTime.

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♦ Design Compiler

dc_shell> read_sdf DCSDF_filename\-min_type [sdf_min|sdf_typ|sdf_max]\-max_type [sdf_min|sdf_typ|sdf_max]

♦ PrimeTime

dc_shell> read_sdf DCSDF_filename\-min_type [sdf_min|sdf_typ|sdf_max]\-max_type [sdf_min|sdf_typ|sdf_max] \-analysis_type single [single|bc_wc]

"on_chip_variaton" can be set to the -analysis_type option of Primetime, but is unavailable for Toshiba ASIC development.

The following shows the examples of the command.

♦ To use the maximum delay for analysis of setup time, and the minimum delay for analysis of hold time, specify as follows.

[Design Compiler]

dc_shell> read_sdf DCSDF_filename -min_type sdf_min \-min_type sdf_max

[PrimeTime]

dc_shell> read_sdf DCSDF_filename \-min_type sdf_min -max_type sdf_max\-analysis_type bc_wc

♦ To use the maximum delay for analysis of setup time and hold time, specify as follow.

[Design Compiler]

dc_shell> read_sdf DCSDF_filename -min_type sdf_max \-max_type sdf_max

[PrimeTime]

dc_shell> read_sdf DCSDF_filename \-min_type sdf_max -max_type sdf_max \-analysis_type single

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Running the Timing Constraint Command

Timing constraints are imposed for timing analysis, that is same as logic synthesis and timing optimization. The following shows the commonly used commands. Options required with the following command differ between Design Compiler and PrimeTime. PrimeTime requires arguments in tcl format. When the DCSDF file is read, you don’t need to specify the wire load model with the set_wire_load_model command and the operating condition name with the set_operationg_condition command.

• create_clock

• create_generated_clock

• set_clock_uncertainty

• set_propagated_clock

• set_input_delay

• set_output_delay

• set_max_delay

• set_false_path

• set_multilcycle_path

• set_case_analysis (For PrimeTime Only)

Timing Analysis

The following shows the commands used with timing analysis by PrimeTime. For the details of commands and options, see the manual provided by Synopsys.

report_constraints

The report_constraints command displays where timing violation occurs.

pt_shell report_constraints [option . . . ]

where, option is one of the following.

-all_violators

Displays all paths where timing violations occur. If this option is not specified, only the path where the most serious violation occurs is displayed. This option displays the ends of paths for individual timing violations.

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-verbose Displays the details of the path where a timing violation occurs. When this option is specified along with the -all_violators option, the details of all paths where timing violations occur are displayed.

report_timing

The report_timing command displays paths with the maximum or minimum delay in the order from the top critical path for the timing constraint.

pt_shell report_constraints [option . . . ]

where, option is one of the following.

-from Specifies the start point of a path to be analyzed.

-to Specifies the end point of a path to be analyzed.

-through through_point

Specifies the point which the path to be analyzed goes through.

-delay path_type

Specifies the type of a path to be analyzed.

-nets Displays the number of fanouts on each analysis point.

-transition_time

Displays the signal transition time.

-max_paths number

Specifies the maximum number of paths to be displayed.

-nworst number

Displays the number of paths to be analyzed at every end point.

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Part 3

RTL Coding Styles

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CHAPTER 6 Register Definition

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Overview

When you design at RTL, it is important to write the HDL description so that the correct register type is directly inferred. You can write your coding such that "hints" are passed to the compiler, indicating which sequential cells are preferred. With VHDL, you can use attributes to restrict the inference to sequential cells with such simple behavior as asynchronous set/reset.

For example, Toshiba’s cell libraries do not include a D-type flip-flop with an asynchronous set pin that is active high. The statement "if(preset=’1’) then" written in VHDL would translate into an inverter in front of the FD4 flip-flop.

Furthermore, Toshiba’s libraries contain cells that you should avoid using in your design. You need to exclude these cells from sequential mapping. For example, use of scan flip-flops is discouraged because scan conversion is usually performed using a test synthesis tool.

This section presents a number of Verilog-HDL and VHDL descriptions to make the best use of Toshiba’s cell library to produce sequential behavior.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VHDL Attributes

With VHDL, you can effectively use attributes so that preferred flip-flops and latches are correctly inferred. Below is a list of useful attributes:

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♦ sync_set_reset

Indicates a register that has either a synchronous set pin or a synchronous reset pin or both.

♦ async_set_reset

Indicates a register that has either an asynchronous set pin or an asynchronous reset pin or both. This attribute can work on a single-bit signal only.

♦ sync_set_reset_local

Same as sync_set_reset, except that this attribute is effective only within a block or process block in which it is specified. This attribute can work on a single-bit signal only.

♦ async_set_reset_local

Same as async_set_reset, except that this attribute is effective only within a block or process block in which it is specified. This attribute can work on a single-bit signal only.

♦ sync_set_reset_local_all

Same as sync_set_reset. This attribute can be used, however, to ensure that all signals in a block or process block in which it is specified are either a synchronous set signal or a synchronous reset signal.

♦ async_set_reset_local_all

Same as async_set_reset. This attribute can be used, however, to ensure that all signals in a block or process block in which it is specified are either an asynchronous set signal or an asynchronous reset signal.

♦ one_hot

Specifies that at most one of the specified register pins can be active (logic high) at a time.

♦ one_cold

Specifies that at most one of the specified register pins can be active (logic low) at a time.

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Excluding Specific Register Cells from Sequential Mapping

Toshiba’s cell libraries contain cells you should avoid using in your design at the logic synthesis stage. You need to mark the following cells with the dont_use attribute before compile.

♦ Register types wherein the Q output delay depends on the capacitance loads associated with the QN output

♦ Scan cells

For example, YFD1 is a flip-flop whose Q output delay is dependent upon the load on the QN output. This hinders accurate delay estimation for the Q output; use of YFD1 often causes the Synopsys tools to issue warning messages. This type of register cells makes timing analysis unreliable, and will be an obstacle to the sign-off process. Toshiba recommends you not to use such register cells in your design. In the TC200G gate array library, these register cells are named YF* or YLD*. Following is an example of a setup to prevent the compiler from using YF* and YLD* cells:

dont_use find( cell,{tc200g/YF*, tc200g/YLD*})

A test synthesis tool usually takes care of scan conversion. You should exclude scan cells from sequential mapping for two reasons. First, if you have scan cells in your design, a test synthesis tool can not connect them in a scan chain automatically, thus lowering test fault coverage. Second, if your design contains scan cells, Design Compiler sometimes uses the functions of the scan cells to optimize the surrounding logic. In the TC200G gate array library, scan cells are named F*S or F*SP. Following is an example of a setup to prevent the compiler from using F*S and F*SP cells:

dont_use find( cell,{tc200g/F*S, tc200g/F*SP})

You can enter the dont_use commands in the .synopsys_dc.setup file, or run them before compile.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Wait Statement (VHDL Only)

Design Compiler supports wait until, but not wait on. Use the process statement with a sensitivity list in place of wait on. The following code fragment shows a description of an asynchronous set.

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Figure 6–1 Using the Process Statement with a Sensitivity List

Not This

processbegin wait on clk, reset ; if ( reset = '0' ) then regout <= '0' ; elsif ( clk'event and clk = '1' ) then regout <= data ; end if ;end process ;

But

process( clk , reset )begin if ( reset = '0' ) then regout <= '0' ; elsif ( clk'event and clk = '1' ) then regout <= data ; end if ;end process ;

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Sequential Inference

This section presents several examples of HDL descriptions that map to various register types. For details, see the HDL Coding Style: Sequential Devices Application Notes from Synopsys. Major topics in this section are:

♦ Mapping to Flip-Flops Available in the Toshiba Library

♦ Mapping to Flip-Flops Unavailable in the Toshiba Library

♦ Mapping to Latches Available in the Toshiba Library

♦ Mapping to Latches Unavailable in the Toshiba Library

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Mapping to Flip-Flops Available in the Toshiba Library

Toshiba’s cell libraries contain the following types of flip-flops:

♦ D-type flip-flop (FD1)

♦ D-type flip-flop with asynchronous set (FD4)

♦ D-type flip-flop with asynchronous reset (FD2)

♦ D-type flip-flop with asynchronous set and reset (FD3)

♦ JK flip-flop (FJK1)

♦ JK flip-flop with asynchronous reset (FJK2)

♦ JK flip-flop with asynchronous set and reset (FJK3)

♦ Toggle flip-flop with asynchronous set (FT4)

♦ Toggle flip-flop with asynchronous reset (FT2)

The HDL templates presented in this subsection allow Design Compiler to correctly infer the above flip-flops. You can simply use the following commands:

dc_shell> read -f {vhdl|verilog} vhdl/verilog_file

dc_shell> dont_use find( cell,{tc200g/YF*,tc200g/YLD*})

dc_shell> dont_use find( cell,{tc200g/F*S,tc200g/F*SP})

dc_shell> compile

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Following are the templates for the D-type flip-flop, FD1. VHDL does not require any attribute.

Figure 6–2 D-Type Flip-Flop (FD1)

VHDL

library IEEE, Synopsys ;

use IEEE.std_logic_1164.all; use Synopsys.attributes.all;

entity simple_dff isport ( data, clk : in std_logic ; q : out std_logic );

end simple_dff ; architecture rtl of simple_dff is

begin infer : process ( clk ) begin if ( clk'event and clk = '1' ) then

q <= data ; end if ; end process infer ;

end rtl ;

Verilog-HDL

module simple_dff ( data , clk , q );input data , clk ;

output q;reg q;always @(posedge clk)

q = data;endmodule

D-Type Flip-Flop (FD1)

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Following are the templates for the D-type flip-flop with asynchronous set, FD4. The VHDL code for FD4 uses the async_set_reset_local attribute. You can also use the async_set_reset attribute, or omit the attribute. The asynchronous set pin on FD4 is active low; so the VHDL code has a line that reads:if ( preset = ’0’ ) then. Note that Toshiba’s cell library does not contain a D-type flip-flop with asynchronous, active-high set. The statement "if ( preset = ’1’ )" would translate into an inverter in front of the asynchronous set input of the FD4 flip-flop.

Figure 6–3 D-Type Flip-Flop with Asynchronous Set (FD4)

VHDL


use IEEE.std_logic_1164.all;use Synopsys.attributes.all;

entity async_set_dff isport ( clk, preset , data : in std_logic ; regout : out std_logic );

end async_set_dff ; architecture rtl of async_set_dff is

attribute async_set_reset_local of infer : label is "preset" ;begin infer : process( clk, preset )

begin if ( preset = '0' ) then regout <= '1' ;

elsif ( clk = '1' and clk'event ) then regout <= data ; end if ;

end process ;end rtl ;

Verilog-HDL

module async_set_dff ( clk , preset , data , regout );

input clk , preset , data;output regout;reg regout;

always @( posedge clk or negedge preset ) if ( ~preset ) regout = 1'b1;

else regout = data;endmodule

D-Type Flip-Flop with Asynchronous Set (FD4)

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Following are the templates for the D-type flip-flop with asynchronous reset, FD2. Like FD4, the VHDL code for FD2 uses the async_set_reset_local attribute. You can also use the async_set_reset attribute, or omit the attribute. When you use the async_set_reset attribute, write as follows:

attribute async_set_reset of reset : signal is "true"

The asynchronous set pin on FD2 is active low; so the VHDL code has a line that reads: if ( reset = ’0’ ) then.

Figure 6–4 D-Type Flip-Flop with Asynchronous Reset (FD2)

VHDL

library IEEE, Synopsys ;use IEEE.std_logic_1164.all;use Synopsys.attributes.all;

entity async_reset_dff isport ( clk, reset , data : in std_logic ;

regout : out std_logic );end async_reset_dff ;

architecture rtl of async_reset_dff isattribute async_set_reset_local of infer : label is "reset" ;begin

infer : process( clk, reset ) begin if ( reset = '0' ) then

regout <= '0' ; elsif ( clk = '1' and clk'event ) then regout <= data ;

end if ; end process ;end rtl ;

Verilog-HDL

module async_reset_dff ( clk , reset , data , regout );input clk , reset , data;output regout;

reg regout;always @( posedge clk or negedge reset ) if ( ~reset )

regout = 1'b0; else regout = data;endmodule

D-Type Flip-Flop with Asynchronous Reset (FD2)

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Following are the templates for the D-type flip-flop with asynchronous set and reset, FD3. Like FD2, the VHDL code for FD3 uses the async_set_reset_local attribute. You can also use the async_set_reset attribute. Both of the asynchronous set and reset pins on FD3 are active low; so the VHDL code has lines that read: if ( reset = ’0’ ) then and elsif ( preset = ’0’ ) then. Note that the one_cold attribute is applied to the set and reset inputs so they will not be active low at the same time.

Figure 6–5 D-Type Flip-Flop with Asynchronous Set and Reset (FD3)

VHDL

library IEEE, Synopsys ;use IEEE.std_logic_1164.all;use Synopsys.attributes.all;

entity async_set_rset_dff isport ( clk, reset, preset, data : in std_logic ;

regout : out std_logic );end async_set_rset_dff ;

architecture rtl of async_set_rset_dff isattribute async_set_reset_local of infer : label is "preset, reset" ;attribute one_cold of preset, reset : signal is "true" ;

begin infer : process( clk, reset, preset ) begin

if ( reset = '0' ) then regout <= '0' ; elsif ( preset = '0' ) then

regout <= '1' ; elsif ( clk = '1' and clk'event ) then regout <= data ;

end if ; end process ;end rtl ;

D-Type Flip-Flop with Asynchronous Set and Reset (FD3)

71

Register Definition

Figure 6–5 (cont’d) D-Type Flip-Flop with Asynchronous Set and Reset (FD3)

Verilog-HDL

module async_set_rset_dff ( clk , reset , preset , data , regout );input clk , reset , preset , data;output regout;

reg regout;//synopsys one_cold "reset, set"always @( posedge clk or negedge reset or negedge preset )

if ( ~reset ) regout = 1'b0; else if ( ~preset )

regout = 1'b1; else regout = data;

endmodule

72

Register Definition

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Following are the templates for a JK flip-flop, FJK1. The VHDL code for FJK1 uses the sync_set_reset_local or sync_set_reset attribute.

Figure 6–6 JK Flip-Flop (FJK1)

VHDL



entity JK isport ( J, K, CLK : in std_logic ; Q_out : out std_logic );

end JK ; architecture rtl of JK is

attribute sync_set_reset of J, K : signal is "true";signal Q : std_logic ;begin

infer : process variable JK : std_logic_vector ( 1 downto 0 );begin

wait until ( CLK'event and CLK = '1' ); JK := ( J & K ); case JK is

when "01" => Q <= '0' ; when "10" => Q <= '1' ; when "11" => Q <= not (Q);

when "00" => Q <= Q ; when others => Q <= 'X' ; end case ;

end process infer ; Q_out <= Q ;end rtl ;

JK Flip-Flop (FJK1)

73

Register Definition

Figure 6–6 (cont’d) JK Flip-Flop (FJK1)

Verilog-HDL

module JK ( J , K , CLK , Q );input J , K;input CLK;

output Q;reg Q;// synopsys sync_set_reset "J , K"

always @( posedge CLK ) case ({J , K }) 2'b01 : Q = 0;

2'b10 : Q = 1; 2'b11 : Q = ~Q; endcase

endmodule

74

Register Definition

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Following are the templates for the JK flip-flop with asynchronous reset, FJK2. The VHDL code for FJK2 uses either the sync_set_reset_local or sync_set_reset attribute to specify the J and K inputs and either the async_set_reset or async_set_reset_local attribute to specify the asynchronous reset input.

Figure 6–7 JK Flip-Flop with Asynchronous Reset (FJK2)

VHDL

library IEEE, Synopsys;

use IEEE.std_logic_1164.all;use Synopsys.attributes.all;

entity jk_async_reset isport (RESET, J, K, CLK : in std_logic; Q_out : out std_logic );

end jk_async_reset; architecture rtl of jk_async_reset is

attribute sync_set_reset of J, K : signal is "true";attribute async_set_reset of RESET : signal is "true";

signal Q : std_logic;begin

infer : process (CLK , RESET )variable JK : std_logic_vector ( 1 downto 0);begin

if (RESET = '0') then Q <= '0'; elsif (clk'event and CLK = '1') then

JK := (J & K); case JK is when "01" => Q <= '0';

when "10" => Q <= '1'; when "11" => Q <= not(Q); when "00" => Q <= Q;

when others => Q <= 'X'; end case; end if;

Q_out <= Q;end process infer;end rtl;

JK Flip-Flop with Asynchronous Reset (FJK2)

75

Register Definition

Figure 6–7 (cont’d) JK Flip-Flop with Asynchronous Reset (FJK2)

Verilog-HDL

module jk_async_sr ( RESET , J , K , CLK , Q );input RESET , J , K;input CLK;

output Q;reg Q;// synopsys sync_set_reset "J , K"

always @( posedge CLK or negedge RESET ) if ( ~RESET ) Q = 1'b0;

else case ({J , K}) 2'b01 : Q = 0;

2'b10 : Q = 1; 2'b11 : Q = ~Q; endcase

endmodule

76

Register Definition

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Following are the templates for the JK flip-flop with asynchronous set and reset, FJK3. Like FJK2, the VHDL code for FJK3 uses either the sync_set_reset_local or sync_set_reset attribute for the J and K inputs and either the async_set_reset or async_set_reset_local attribute to specify the asynchronous set and reset inputs. Note that the one_cold attribute is applied to the set and reset inputs so they will not be active low at the same time.

Figure 6–8 JK Flip-Flop with Asynchronous Set and Reset (FJK3)

VHDL

library IEEE, Synopsys;use IEEE.std_logic_1164.all;

use Synopsys.attributes.all; entity jk_async_sr is

port ( RESET, SET, J, K, CLK : in std_logic; Q_out : out std_logic );end jk_async_sr;

architecture rtl of jk_async_sr is

attribute sync_set_reset of J, K : signal is "true";attribute one_cold of RESET ,SET : signal is "true";

signal Q : std_logic;begininfer : process (CLK , RESET , SET)

variable JK : std_logic_vector ( 1 downto 0);begin if (RESET = '0') then

Q <= '0'; elsif (SET = '0') then Q <= '1';

elsif (clk'event and CLK = '1') then JK := (J & K); case JK is

when "01" => Q <= '0'; when "10" => Q <= '1'; when "11" => Q <= not(Q);

when "00" => Q <= Q; when others => Q <= 'X'; end case;

end if; Q_out <= Q;end process infer;

end rtl;

JK Flip-Flop with Asynchronous Set and Reset (FJK3)

77

Register Definition

Figure 6–8 (cont’d) JK Flip-Flop with Asynchronous Set and Reset (FJK3)

Verilog-HDL

module jk_async_sr ( RESET , SET , J , K , CLK , Q );input RESET , SET , J , K , CLK;output Q;

reg Q;// synopsys sync_set_reset "J , K"// synopsys one_cold "RESET , SET"

always @( posedge CLK or negedge RESET or negedge SET ) if ( ~RESET ) Q = 0;

else if ( ~SET ) Q = 1; else // This is the clocking clause

case ({J , K}) 2'b01 : Q = 0; 2'b10 : Q = 1;

2'b11 : Q = ~Q; endcase

endmodule

78

Register Definition

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Following are the templates for the toggle flip-flop with asynchronous set, FT4. Like FD4, the VHDL code for FT4 uses the async_set_reset_local attribute. You can also use the async_set_reset attribute, or omit the attribute.

Figure 6–9 Toggle Flip-Flop with Asynchronous Set (FT4)

VHDL

library IEEE, Synopsys;use IEEE.std_logic_1164.all;

entity t_async_set isport( SET , CLK : in std_logic;

Q : out std_logic );end t_async_set;

architecture rtl of t_async_set is attribute async_set_reset of SET : signal is "true";

signal tmp_q : std_logic;begin

infer: process (CLK , SET) begin if (SET = '0') then tmp_q <= '1';

elsif (CLK'event and CLK = '1') then tmp_q <= not (tmp_q); end if;

end process infer; Q <= tmp_q;

end rtl;

Verilog-HDL

module t_async_set ( SET , CLK , Q );

input SET , CLK;output Q;reg Q;

always @( posedge CLK or negedge SET ) if ( ~SET )

Q = 1; else Q = ~Q;

endmodule

Toggle Flip-Flop with Asynchronous Set (FT4)

79

Register Definition

Following are the templates for the toggle flip-flop with asynchronous reset, FT2. Like FT4, the VHDL code for FT2 uses the async_set_reset_local attribute. You can also use the async_set_reset attribute, or omit the attribute.

Figure 6–10 Toggle Flip-Flop with Asynchronous Reset (FT2)

VHDL

library IEEE ;use IEEE.std_logic_1164.all;

entity t_async_reset isport( RESET , CLK : in std_logic;

Q : out std_logic );end t_async_reset;

architecture rtl of t_async_reset is

attribute async_set_reset of RESET : signal is "true";

signal tmp_q : std_logic;begin

infer: process (CLK , RESET) begin if (RESET = '0') then tmp_q <= '0';

elsif (CLK'event and CLK = '1') then tmp_q <= not (tmp_q); end if;

end process infer; Q <= tmp_q;

end rtl;

Verilog-HDL

module t_async_reset ( RESET , CLK , Q );

input RESET , CLK;output Q;reg Q;

always @( posedge CLK or negedge RESET ) if ( ~RESET )

Q = 0; else Q = ~Q;endmodule

Toggle Flip-Flop with Asynchronous Reset (FT2)

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Mapping to Flip-Flops Unavailable in the Toshiba Library

This subsection presents HDL descriptions to implement the following sequential logic functions unavailable in the Toshiba library. Design Compiler uses a D-type flip-flop from Toshiba’s library and adds a combinational logic to its data input to implement the specified function.

♦ D-type flip-flop with synchronous set

♦ D-type flip-flop with synchronous reset

♦ D-type flip-flop with synchronous multiplexed input

♦ D-type flip-flop with synchronous clock enable

81

Register Definition

Following are the templates for a D-type flip-flop with synchronous set. The Toshiba library does not contain such a flip-flop. The VHDL code uses the async_set_reset_local or async_set_reset attribute.

Figure 6–11 D-Type Flip-Flop with Synchronous Set

VHDL

library IEEE, Synopsys ;use IEEE.std_logic_1164.all;

use Synopsys.attributes.all;

entity dff_sync_set is

port ( data, clk, set : in std_logic ; q : out std_logic );end dff_sync_set ;

architecture rtl of dff_sync_set isattribute sync_set_reset of set : signal is "true";

begininfer : process ( clk ) begin if ( clk'event and clk = '1' ) then

if ( set = '1' ) then q <= '1' ; else q <= data ;

end if ; end if ;end process infer ;

end rtl ;

Verilog-HDL

module dff_sync_set ( data , clk , set , q );

input data , clk , set;output q;reg q;

//synopsys sync_set_reset "set"always @( posedge clk ) if ( set )

q = 1'b1; else q = data;

endmodule

D-Type Flip-Flop with Synchronous Set

82

Register Definition

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Following are the templates for a D-type flip-flop with synchronous reset. The Toshiba library does not contain such a flip-flop. The VHDL code uses the async_set_reset_local or async_set_reset attribute.

Figure 6–12 D-Type Flip-Flop with Synchronous Reset

VHDL



entity dff_sync_reset is

port ( data, clk, reset : in std_logic ; q : out std_logic );end dff_sync_reset ;

architecture rtl of dff_sync_reset isattribute sync_set_reset of reset : signal is "true";

begininfer : process ( clk ) begin if ( clk'event and clk = '1' ) then

if ( reset = '0' ) then q <= '0' ; else q <= data ;

end if ; end if ;end process infer ;

end rtl ;

Verilog-HDL

module dff_sync_reset ( data , clk , reset , q );input data , clk , reset;

output q;reg q;//synopsys sync_set_reset "reset"

always @( posedge clk ) if ( ~reset ) q = 1'b0;

else q = data;

endmodule

JK Flip-Flop with Synchronous Reset

83

Register Definition

Following are the templates for a D-type flip-flop with synchronous multiplexed input. The Toshiba library does not contain such a flip-flop. However, if you do not prevent the compiler from using scan cells, a muxed flip-flop for scan design (FD1S) may sometimes be inferred.

Figure 6–13 D-Type Flip-Flop with Synchronous Multiplexed Input

VHDL

library IEEE ;use IEEE.std_logic_1164.all;

entity muxed_dff isport ( d0, d1, sel, clk : in std_logic ; q : out std_logic );

end muxed_dff ;

architecture rtl of muxed_dff is

beginprocess ( clk ) begin if ( clk'event and clk = '1' ) then

if ( sel = '1' ) then q <= d1 ; else

q <= d0 ; end if ; end if ;

end process ;end rtl ;

Verilog-HDL

module muxed_dff ( d0 , d1 , sel , clk , q );

input d0 , d1 , sel , clk;output q;reg q;

always @( posedge clk ) if ( sel ) q = d1;

else q = d0;

endmodule

D-Type Flip-Flop with Synchronous Multiplexed Input

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Register Definition

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Following are the templates for a D-type flip-flop with synchronous clock enable input. The Toshiba library does not contain such a flip-flop.

Figure 6–14 D-Type Flip-Flop with Synchronous Clock Enable

VHDL


use IEEE.std_logic_1164.all; -- use Synopsys.attributes.all;

entity latch_sync_enable isport ( data, clk, enable : in std_logic ; q : out std_logic );

end latch_sync_enable ;

architecture rtl of latch_sync_enable is

-- attribute sync_set_reset of enable : signal is "true";begin

infer : process ( clk ) begin if ( clk'event and clk = '1' ) then if ( enable = '1' ) then

q <= data ; end if ; end if ;

end process infer ;end rtl ;

Verilog-HDL

module latch_sync_enable ( data , clk , enable , q );

input data , clk , enable;output q;reg q;

// synopsys sync_set_reset "enable"always @( posedge clk ) if ( enable )

q = data;endmodule

D-Type Flip-Flop with Synchronous Clock Enable

85

Register Definition

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Mapping to Latches Available in the Toshiba Library

Toshiba’s cell libraries contain the following types of latches:

♦ D-type latch, active high (LD1)

♦ D-type latch, active low (LD2)

♦ D-type latch with asynchronous reset, active high (LD3)

♦ D-type latch with asynchronous reset, active low (LD4)

86

Register Definition

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Following are the templates for a D-type latch with active-high control input (LD1). VHDL does not require any attribute.

Figure 6–15 D-Type Latch, Active High (LD1)

VHDL

library IEEE ;

use IEEE.std_logic_1164.all; entity d_latch is

port ( enable, data : in std_logic ; q : out std_logic );end d_latch ;

architecture rtl of d_latch isbegin

infer : process ( enable, data ) begin if ( enable = '1' ) then q <= data ;

end if ; end process infer ;end rtl ;

Verilog-HDL

module d_latch ( enable , data , q );input enable , data;output q;

reg q;

always @( enable or data )

if ( enable ) q = data;

endmodule

D-Type Latch, Active High (LD1)

87

Register Definition

Following are the templates for the D-type latch with active-low control input, LD1. VHDL does not require any attribute.

Figure 6–16 D-Type Latch, Active Low (LD2)

VHDL

library IEEE ;

use IEEE.std_logic_1164.all;

entity d_latch is

port ( enable, data : in std_logic ; q : out std_logic );end d_latch ;

architecture rtl of d_latch isbegin

infer : process ( enable, data ) begin if ( enable = '0' ) then q <= data ;

end if ; end process infer ;end rtl ;

Verilog-HDL

module d_latch ( enable , data , q );input enable , data;output q;

reg q;

always @( enable or data )

if ( ~enable ) q = data;

endmodule

D-Type Latch, Active Low (LD2)

88

Register Definition

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Following are the templates for the D-type latch with asynchronous, active-high control input, LD3. The VHDL code for LD3 uses the async_set_reset_local or async_set_reset attribute.

Figure 6–17 D-Type Latch with Asynchronous Reset, Active High (LD3)

VHDL


use Synopsys.attributes.all; entity d_latch_async_reset is

port ( enable, data, reset : in std_logic ; q : out std_logic );end d_latch_async_reset ;

architecture rtl of d_latch_async_reset is

attribute async_set_reset of reset : signal is "true"; begin

infer : process ( enable, data, reset ) begin if ( reset = '0' ) then q <= '0' ;

elsif ( enable = '1' ) then q <= data ; end if ;

end process infer ; end rtl ;

Verilog-HDL

module d_latch_async_reset ( enable , data , reset , q );input enable , data , reset;output q;

reg q;// synopsys async_set_reset "reset"always @( reset or enable or data )

if ( ~reset ) q = 0; else if ( enable )

q = data;

endmodule

D-Type Latch with Asynchronous Reset, Active High (LD3)

89

Register Definition

Following are the templates for the D-type latch with asynchronous, active-low control input, LD4. The VHDL code for LD4 uses the async_set_reset_local or async_set_reset attribute.

Figure 6–18 D-Type Latch with Asynchronous Reset, Active Low (LD4)

VHDL



entity d_latch_async_reset is

port ( enable, data, reset : in std_logic ; q : out std_logic );end d_latch_async_reset ;

architecture rtl of d_latch_async_reset is

attribute async_set_reset of reset : signal is "true";

begin

infer : process ( enable, data, reset ) begin if ( reset = '0' ) then q <= '0' ;


end process infer ;

end rtl ;

Verilog-HDL

module d_latch_async_reset ( enable , data , reset , q );input enable , data , reset;output q;

reg q;// synopsys async_set_reset "reset"always @( enable or data or reset )

if ( ~reset ) q = 0; else if ( ~enable )

q = data;endmodule

D-Type Latch with Asynchronous Reset, Active Low (LD4)

90

Register Definition

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ter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Mapping to Latches Unavailable in the Toshiba Library

This subsection presents HDL descriptions to implement sequential logic functions unavailable in the Toshiba library. Design Compiler uses a D-type latch from Toshiba’s library and adds a combinational logic to it to implement the specified function.

♦ D-type latch with asynchronous set

♦ D-type latch with asynchronous set and reset

♦ RS latch

91

Register Definition

Following are the templates for a D-type latch with asynchronous set. The Toshiba library does not contain such a latch. The VHDL code uses the async_set_reset_local or async_set_reset attribute.

Figure 6–19 D-Type Latch with Asynchronous Set

VHDL



entity d_latch_async_set is

port ( enable, data, set : in std_logic ; q : out std_logic );end d_latch_async_set ;

architecture rtl of d_latch_async_set is

attribute async_set_reset of set : signal is "true";

begin

infer : process ( enable, data, set ) begin if ( set = '0' ) then q <= '1' ;


end process infer ;

end rtl ;

Verilog-HDL

module d_latch_async_set ( enable , data , set , q );input enable , data , set;output q;

reg q;// synopsys async_set_reset "set"always @( enable or data or set )

if ( ~set ) q = 1'b1; else if ( enable )

q = data;

endmodule

D-Type Latch with Asynchronous Set

92

Register Definition

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Following are the templates for a D-type latch with asynchronous set and reset. The Toshiba library does not contain such a latch. The VHDL code uses the async_set_reset_local or async_set_reset attribute. Note that the one_cold attribute is applied to the set and reset inputs so they will not be active low at the same time.

Figure 6–20 D-Type Latch with Asynchronous Set and Reset

VHDL



entity d_latch_async isport ( enable, data, reset, set : in std_logic ; q : out std_logic );

end d_latch_async ;

architecture rtl of d_latch_async is

attribute async_set_reset_local of infer : label is "set , reset";attribute one_cold of set , reset : signal is "true" ;

begininfer : process ( enable, data, reset, set ) begin

if ( set = '0' ) then q <= '1' ; elsif ( reset = '0' ) then

q <= '0' ; elsif ( enable = '0' ) then q <= data ;

end if ;end process infer ;

end rtl ;

D-Type Latch with Asynchronous Set and Reset

93

Register Definition

Figure 6–20 (cont’d) D-Type Latch with Asynchronous Set and Reset

Verilog-HDL

module d_latch_async ( enable , data , reset , set , q );input enable , data , reset , set;output q;

reg q;// synopsys async_set_reset_local infer "reset , set"// synopsys one_cold "reset , set"

always @( enable or data or reset or set )begin : infer if ( !set )

q = 1'b1; else if ( !reset ) q = 1'b0;

else if ( !enable ) q = data;

endmodule

94

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Following are the templates for an RS latch. The Toshiba library does not contain an RS latch. The VHDL code uses the async_set_reset_local or async_set_reset attribute.

Figure 6–21 RS Latch

VHDL



entity rs_latch_if is

port ( reset, set : in std_logic ; y : out std_logic );

attribute async_set_reset of reset, set:signal is "true";end rs_latch_if ;

architecture rtl of rs_latch_if isbegininfer : process ( reset, set ) begin

if ( reset = '0' ) then y <= '0' ; elsif ( set = '0' ) then

y <= '1' ; end if ;end process infer ;

end rtl ;

Verilog-HDL

module rs_latch_if ( reset , set , y );input reset , set;

output y;reg y;//synopsys async_set_reset "set , reset"

always @( reset or set ) if ( ~reset ) y = 0;

else if ( ~set ) y = 1;endmodule

RS Latch

95

Register Definition

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Module Partitioning

It is always desirable to partition a design into modules along register outputs, as shown in Figure 6–22.

Figure 6–22 Module Partitioning

Design Compiler has an integral timing analyzer to optimize a design for timing. There are four types of timing paths: primary input to register, register to register, register to primary output, and primary input to primary output. As for register-to-register paths, timing analysis starts at register outputs and ends at register inputs. In other words, timing optimization works on the combinational logic between two given registers. That means confining the combinational logic within a single module simplifies timing analysis and thus optimization. Combinational logic that spans across multiple module boundaries makes gate-level timing optimization more complicated and sometimes restricted.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Finite-State Machines (FSMs)

In general, logic synthesizers work best on synchronous designs, which consist of a datapath part and a corresponding control part. A finite-state machine is used to build the control part at RTL.

Mealy Machines vs. Moore Machines

There are two forms of state machines, Mealy machines and Moore machines. Mealy and Moore machines make their state transitions in exactly the same way. The main difference between these machines is the way they assign values to the

F/F F/FComb.Logic

Comb.Logic

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outputs. While the outputs of a Moore machine are determined only by the internal state of the registers, the outputs of a Mealy machine are determined by the input value as well as the internal state.

Mealy machines generate control signals once per clock period. It is therefore easier to generate response signals (e.g., acknowledge/grant). However, Mealy machines have a potential risk of causing hold time violations, as shown below in Figure 6–23.

On the other hand, Moore machines generate control signals based on state transitions, and therefore, more efficient in transmitting the current state to the next-stage logic (Ready state in Figure 6–23). While a Moore machine operates reliably at a high frequency, it requires a greater number of clock periods for states to change.

Figure 6–23 Mealy and Moore State Machines

State Assignment

State encodings used internally to represent each state in a machine affect the logic required to implement the design, and consequently the area and speed of the resulting design.

One-hot encoding assigns one-bit per state, and thus one flip-flop is required per state. One-hot encoded machines have smaller propagation delays between states because the full state encoding does not need to be decoded. Also, one-hot encoded machines are glitch-free. Other state encoding styles such as binary encoding require fewer flip-flops than one-hot encoding. Machines using binary encoding tend to have larger propagation delays between states because of the complex

NRDY

RDY

Data(Valid) Grant

Moore Machine(State1)

S0

Data/Grant !Ready

Mealy Machine(State2)

S1

Clock

(Data)

State1

State2

Ready

Grant

Invalid Valid

NRDY RDY

S0 S1

Be cautious abouthold violations.

Ready

97

Register Definition

combinational logic to decode the state encoding. Consequently, it is more difficult to meet timing constraints by optimization. Furthermore, the combinational logic portion of a state machine is a glitch generator.

Table 6–1 Binary Encoding vs. One-Hot Encoding

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Combinational Synthesis

It is desirable to write register and combinational logic descriptions separately. At the RTL level, the same logic function can be described in many styles. Each style has its own benefits and penalties, and which style is used often depends on designer’s preferences.

As a way of a guideline, however, Toshiba recommends that you use the process block (with VHDL) or the always block (with Verilog-HDL) for register definitions, and use the function block for combinational synthesis. Following this practice makes the RTL structure more straightforward, and the relationships between two given registers and the combinational logic between them easier to understand. Furthermore, the reason for the function block being preferred for combinational synthesis is that it always corresponds to combinational logic to compute a result from its arguments.

Look at the Verilog-HDL code in Figure 6–24. The always block contains an if statement. If input G is 1, the value of input D is assigned to output Z. Because there is no else branch, it is implied that when the if condition evaluates to false (i.e. G = 0), output Z retains its old value. For synthesis, this implies that a latch will be inferred. You can avoid the creation of an extraneous register by using the function block, as shown in Figure 6–25.

Binary Encoding One-Hot Encoding

# of Flip-Flops Low High

Delay Large Small

Timing Constraints Difficult Easy

Glitches Potential glitch generator Glitch-free

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Figure 6–24 An if Statement without an Else Clause in the always Block

module ALWIF( D,G,Z ) input D,G ; output Z ; reg Z ;

always @( D or G ) if( G ) Z = D ;

endmodule

Figure 6–25 An if Statement without an Else Clause in the function Block

module FUNIF( D,G,Z );input D,G ;output Z ;

function IFTHEN ;

input DIN,GATE ; reg ZOUT ;

begin

if( GATE ) ZOUT = DIN; IFTHEN = ZOUT ;

endfunction

assign Z = IFTHEN( D, G ) ;

endmodule

99

Register Definition

100

Considerations

7. C

on

sid

erat

ion

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CHAPTER 7 Considerations

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Verilog-HDL and Synthesis of Logic

The purpose of this section is to discuss important things you should know about some Verilog-HDL features to obtain a Verilog-HDL description suitable for synthesis and get the intended behavior.

The casez and casex Statements

The casez and casex statements allow don’t-care values to be considered in case statements. The casez statement allows for z values to be treated as don’t-cares, and the casex statement allows for both z and x to be treated as don’t-cares. A question mark, ?, can also be used in place of either z or x, to indicate a don’t-care. Consider the casex statement shown in Figure 7–1.

Figure 7–1 The casex Statement

casex(S) 4’b0011 : Z = A ; //1 4’b10?? : Z = B ; //2 4’b0000 : Z = C ; //3 4’b?01? : Z = D ; //4endcase

In simulation, if S happens to be 0011, then Z = A is executed. Notice that 0011 also matches the expression ?01? in statement 4. The simulator evaluates case expressions in the order given in the description. However, if you give the parallel_case compiler directive, the logic synthesizer arbitrarily chooses either one of these. Should statement 4 be selected, there will be discrepancies between RTL- and gate-level simulation results.

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Assignment and Comparison Statements

An assignment and a comparison statement consist of two parts, a left-hand side and a right-hand side, separated an operator. Take great care to make operands before and after the operator the same bit-length. Remember that even if they are of unequal bit-lengths, HDL Compiler does not give you a courtesy to issue a warning message.

Assignment

Look at the code fragment in Figure 7–2. While the vector OUT_D is 8-bits wide, the right-side value of the assignment statement is only 6-bits wide. When HDL Compiler encounters this, it automatically pads the right-side operand with the needed number of bits (with a value of 0 for each added bit) to make both operands the equal length. The padding occurs from the leftmost bit; so 8’b00001100 is assigned to OUT_D.

Figure 7–2 Different Size Operands in an Assignment Statement (a)

reg[0:7] OUT_D ; : OUT_D = 6’b001100 ;

In the code fragment below in Figure 7–3, the right-hand side of the assign statement, ENZAN, is 6-bits wide as defined by the function statement, whereas the left-hand side (or the concatenated result of CO and S) is only 7-bits wide. CO is prepended with 1’b0, and the value of COUT is assigned to S[0].

Figure 7–3 Different Size Operands in an Assignment Statement (b)

function[0:5] ENZAN ; reg : COUT ; reg[0:4] : SUM ; : ENZAN = { COUT,SUM } ; endendfunction :wire CO ;wire[0:5] S ; :assign { CO , S } = ENZAN(...) ;

Now, look at the following example.The right-side operand is longer than the left-side operand in the assign statement. In this case, the extra bit value of ENZAN is truncated to make both operands the same bit-length.

CO is prepended with 1’b0, and the value of COUT is assigned to S[0].

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Figure 7–4 Different Size Operands in an Assignment Statement (c)

function[0:5] ENZAN ; reg : COUT ; reg[0:3] : SUM ; : ENZAN = { COUT,SUM } ; endendfunction :wire CO ;wire[0:3] S ; :assign { CO , S } = ENZAN(...) ;

Comparison

All relational and equality operators have the same procedure. All these operators compare operands bit for bit, with zero filling if the two operands are of unequal bit-length. The following if statement evaluates to true only when COMPD is 8’b00001101.

Figure 7–5 Different Size Operands in a Comparison Statement

reg[0:7] COMPD ;

if ( COMPD == 4’b1101 )

Module Statement

When external I/O pins are declared within the module statement, pin names may not be concatenated within parentheses since these pin names can not be interfaced to the VSO system. The following description causes an error.

Figure 7–6 Module Statement Example (Violates Rule)

module rmt_reg (CLK, RM, .DATA({ DATA[9], DATA[8], DATA[7], DATA[6], DATA[5], DATA[4], DATA[3], DATA[2], DATA[1], DATA[0] }), tst_en;input CLK, TEST_EN ;output RM, DATA[9], DATA[8], DATA[7], DATA[6], DATA[5], DATA[4], DATA[3], DATA[2], DATA[1], DATA[0] ;

CO is assigned the value of SUM[0], and the value of COUT is truncated.

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VHDL and Synthesis of Logic

The purpose of this section is to discuss important things you should know about some VHDL features to obtain a VHDL description suitable for synthesis and get the intended behavior.

Recommended VHDL Packages

Toshiba recommends you to use the arithmetic packages std_ulogic and std_logic, which are part of the IEEE 1164 standard library and support a full complement of arithmetic operations. These library packages have sufficient subprograms needed for common RTL descriptions, and most VHDL simulators (but not VSS) come with the IEEE-standard packages. This means you do not need to do many rewrites of your VHDL code each time you perform simulation and synthesis.

For wired- or 3-state logic, be sure to use std_ulogic instead of std_logic, since std_ulogic immediately produces an error message when it finds multiple drivers for a signal.

The case Statement

Compare the Verilog-HDL and VHDL case descriptions in Figure 7–7 and Figure 7–8. With VHDL, case must check for all possible values of the case conditions. If not all values are of interest, the syntax mandates the others clause. In contrast, Verilog-HDL does not require all possible case conditions.

Figure 7–7 The case Statement in Verilog-HDL

case(S) 3’b000 : Z = A ; 3’b010 : Z = B ; 3’b011 : Z = C ; 3’b111 : Z = D ;endcase

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Figure 7–8 The case Statement in VHDL

case S is when "000" => Z <= A ; when "010" => Z <= B ; when "011" => Z <= C ; when "111" => Z <= D ; when others => Z <= "000" ;endcase

The case description in Verilog-HDL gives you different synthesis results, depending on whether it is in the always block or the function block. If in the always block, the case description in Figure 7–7 produces a latch in order to hold the value of signal Z when no case condition is met. If in the function block, Z defaults to an initialized state ("0") when no case condition is met.

On the other hand, the case description in VHDL writes all possible case conditions, as shown in Figure 7–8. Since the value of signal Z is always determinate, the case description always generates a combinational logic, regardless of whether it is in the process block or the function block.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Other Considerations

Major topics in this section are:

♦ Loops

♦ I/O Buffers

♦ Handling of an X

Loops

Both VHDL and Verilog-HDL support repetitive operations by using loops such as for and while. Toshiba recommends you not to write complicated operations in terms of loops.

Although loops are very convenient, you should always be cautious when using them. Be sure not to spell out step-by-step operations of a desired design to avoid a poor-quality gate-level implementation as well as an excessive CPU resource and memory requirement for a later optimization. Following is a simple example of a bad loop coding for building a 5-bit adder.

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Figure 7–9 Bad Loop Coding

module YLOOP(A,S) ; input [4:0] A ; output[4:0] S ; reg [4:0] S ; integer I ;

always @( A ) begin S = A ; for ( I=1 ; I<=4 ; I=I+1 ) S = S + I ; endendmodule

A very simple statement can be written that is totally equivalent to this for loop, using this arithmetic equation:

S = A + 10 ;

It is quite common even for experienced designers to make mistakes of mixing such descriptions in a complicated loop. Be sure to review loop descriptions to determine that there is no clause you can move outside of the loop construct.

I/O Buffers

Toshiba’s input and bidirectional buffers have an extra NAND gate that is exclusively used for production testing. Because of this, the Design Compiler insert_pads command can not be used to insert these I/O buffers.

To work around this problem, add structural descriptions of the input and bidirectional buffers you want to use in your RTL code. This carries an added benefit of enabling Design Compiler to take the performance characteristics of the added buffers into consideration during gate mapping and optimization. Figure 7–10 and Figure 7–11 give examples of an input and a bidirectional buffer definition in Verilog-HDL and VHDL.

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Figure 7–10 Input and Bidirectional Buffers in Verilog-HDL

module SAMPLE ( IN0, CLK, OUT0);

input IN0, CLK; output OUT0; wire INT;

reg Q; supply1 NC_1 ;

always @( posedge CLK ) begin Q <= INT; end

IBUF INST0 ( INT, , IN0, NC_1); B4 INST1 ( OUT0, Q ) ;

endmodule

Figure 7–11 Input and Bidirectional Buffers in VHDL

library IEEE;

use IEEE.std_logic_1164.all; --The library specification is not required for simulation, but is

mandatory for synthesis.--library tc200g;--use tc200g.vcomponents.all;

entity SAMPLE is port ( IN0, CLK : in std_logic ;

OUT0 : out std_logic );end SAMPLE;

architecture rtl of SAMPLE is component IBUF port( Z, PO : out std_logic; A, PI : in std_logic);

end component; component B4 port( Z : out std_logic; A : in std_logic);

end component; signal INT, Q, NC_1: std_logic;

begin d_ff : process ( CLK ) begin if ( CLK'event and CLK = '1' ) then

Q <= INT ; end if ; end process d_ff ;

NC_1 <= '1'; INST0 : IBUF port map( Z => INT, PO => open, A => IN0, PI => NC_1);

INST1 : B4 port map( Z => OUT0, A => Q);

end rtl ;

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Handling of an X

Remember that the character X has different meanings for simulators and logic synthesizers. In Verilog-HDL and VHDL (when using the std_logic package), an X denotes a don’t-care state; that is, it does not matter if a logic value is 1 or 0. However, in functional and logic simulators, an X signifies an unknown and sometimes also the Z states.

Because of this, results of RTL- and gate-level simulations may turn out to be different. Look at the following example.

Figure 7–12 Handling of an X

module DCARE(DIN,S,OUTD) ; input [0:3] DIN,S ; output[0:2] OUTD ; reg COND ; reg [0:2] OUTD ;

always @( S or DIN ) begin case ( S ) // synopsys parallel_case full_case 4'b0001 : COND = DIN[0] ; 4'b0010 : COND = DIN[1] ; 4'b0100 : COND = DIN[2] ; 4'b1000 : COND = DIN[3] ; default : COND = 1'bx ; endcase end

always @( COND ) if ( COND == 1'b0 ) OUTD = 3'b001 ; else if ( COND == 1'b1 ) OUTD = 3'b100 ; else OUTD = 3'b111 ;

endmodule

When S = 4’b1100 (the default case in the case description) a simulator assigns a value of 1’bx to COND. Because COND = 1’bx does not match any of the if conditions (comparison constructs) in the second always block, OUTD becomes 3’b111.

However, HDL Compiler and Design Compiler interpret COND = 1’bx as a clear specification that it is not importance if COND is 1’b0 or 1’b1. For this reason, the HDL description in Figure 7–12 is resolved to build a logic design such that OUTD will be either 3’b001 or 3’b100.

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You can direct the simulator to issue an X for an illegal input in order to weep out the problem, but to save time and effort expended for redesign, you should avoid X assignment statements wherever possible while you are at coding. Again, be sure to check that designs before and after synthesis are functionally equivalent by running a simulation.

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Design Compiler User Guide Index

Index

Symbols.synopsys_dc.setup file

bus variables 17example 51internal bus 19naming rule 19specifying libraries 15variables used for HDL (VHDL) outputs 17

A-all_violators 58always block (Verilog-HDL) 98assignment statement

different size operands 102async_set_reset attribute (VHDL) 64async_set_reset_local attribute (VHDL) 64async_set_reset_local_all attribute (VHDL) 64ATPG 24

Bbinary encoding 97boundary scan register 44Built In Self Test (BIST) 26Bus 17

Ccapacitance load

setting loads to external pins 47case statement 104casex statement (Verilog-HDL) 101casez statement (Verilog-HDL) 101cell area 11change_names 48clock signal

suppressing addition of clock buffers 38clock skews 38

skews caused by different clock drivesr 39skews caused by the same clock driver 38

clock waveforms 37create_clock command 37, 58create_generated_clock command 58

DDCSDF file

creating 55reading 56

-delay option 59delay time 10delay to gated clock 39direct access methodology 25dont_use command 65D-type flip-flop (FD1) 68D-type flip-flop with asynchronous reset (FD2) 70D-type flip-flop with asynchronous set (FD4) 69D-type flip-flop with asynchronous set and reset

(FD3) 71D-type flip-flop with synchronous clock enable 85D-type flip-flop with synchronous multiplexed

input 84D-type flip-flop with synchronous set 82D-type latch with asynchronous reset, active high

(LD3) 89D-type latch with asynchronous reset, active low

(LD4) 90D-type latch with asynchronous set 92D-type latch with asynchronous set and reset 93D-type latch, active high (LD1) 87D-type latch, active low (LD2) 88

Eelse statement 98explicit format 44

Ffeed-back loop 28for statement 105-from option 59function block 98

Hhdlout_internal_bussed 19-hierarchy option 48

II/O buffers

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Index Design Compiler User Guide

structural descriptions 106I/O cells 11

inserting 45if statement 98

different size operands 103input slews

setting input slews of external pins 47insert_pads 46insert_pads command 45, 46, 106

JJK flip-flop (FJK1) 73JK flip-flop with asynchronous reset (FJK2) 75JK flip-flop with asynchronous set and reset

(FJK3) 77JK flip-flop with synchronous reset 83JTAG boundary-scan design 27, 44

KK-factor

multiple k-Factors (TC203 or later series libraries) 35

single K-factor (TC190 and TC200 series libraries) 36

LLD3 89loading 10logic synthesizing modules containing I/O cells 46loops 105

M-max_paths option 59Mealy machines 97Moore machines 97multiple-port nets 28, 47multiplexing approach 25

N-name option 37-nets option 59-nworst option 59

Oone_cold attribute (VHDL) 64one_hot attribute (VHDL) 64one-hot encoding 97others statement 104

Ppass-through nets 28, 47-period option 37process block (VHDL) 98

Rread_sdf 57register mapping

avoiding mapping of specific registers 41report_area command 34, 49report_cell 50report_constraints 50, 58report_design command 36, 50report_hierarchy 49report_names 48report_net 50report_port 49report_reference 49report_timing 59report_transitive_fanout 50reset signal

suppressing addition of buffers 40RS latch 95-rules option 48

Sscan conversion

avoid mapping of specific registers 41scan design 24sequential inference 66set_case_analysis command 58set_clock_uncertainty command 38, 58set_dont_touch command 40set_dont_touch find command 46set_dont_touch_network command 38, 40set_dont_use command 41set_false_path command 58set_fix_hold command 38set_fix_multiple_port_nets command 28, 47set_input_delay command 58set_input_transition command 47set_load 0 find command 47set_load command 47set_max_delay command 58set_min_library command 35set_multilcycle_path command 58

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Design Compiler User Guide Index

set_operating_conditions command 35, 36set_output_delay command 58set_pad_type command 46set_propagated_clock command 39, 58set_wire_load_model commnad 33state encodings 97state transitions 96std_logic package 104std_unlogic package 104sync_set_reset attribute (VHDL) 64sync_set_reset_local attribute (VHDL) 64sync_set_reset_local_all attribute (VHDL) 64synchronous reset signals 40

T-through option 59timing arc

breaking 13-to option 59toggle flip-flop with asynchronous reset (FT2) 80toggle flip-flop with asynchronous set (FT4) 79-transition_time option 59

V-verbose option 59

Wwait on statement (VHDL) 65wait statement (VHDL) 65wait until statement VHDL) 65-waveform option 37while statement 105wire load model 33wired-ORed connection 28

XX

logic synthesizers 108simulators 108

YYFD-type flip-flops 12YLD-type latches 12

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Index Design Compiler User Guide

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