design, development and test results of 20kw, 499.75 mhz

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Design, Development and Test Results of 20kW, 499.75 MHz Solid State Wide Band RF Power Amplifiers for the Sub-haromic buncher (CLIC Collaboration)* Purushottam Shrivastava ([email protected]), P. Mohania, A. Mahawar, P.D. Gupta Raja Ramanna Centre for Advanced Technology, Indore, India CLIC Workshop Jan 18-22, 2016 * DAE (India) CERN Collaboration under NAT Protocol

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Design, Development and Test Results of 20kW, 499.75 MHz Solid

State Wide Band RF Power Amplifiers for the Sub-haromic buncher

(CLIC Collaboration)*

Purushottam Shrivastava ([email protected]), P. Mohania,

A. Mahawar, P.D. Gupta

Raja Ramanna Centre for Advanced Technology,

Indore, India

CLIC Workshop Jan 18-22, 2016

* DAE (India) CERN Collaboration under NAT Protocol

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

Motivation

•Under DAE (India) CERN collaboration in Novel Accelerator Technologies, of

which CLIC collaboration is a part, a 20kW Solid State RF Power Amplifier R, D

& D effort by RRCAT, Indore was agreed an as R & D and protyping in this state

of the art area.

•RRCAT had earlier built a 476 MHz, 10kW Solid State RF Power Amplifier for

use in its FEL projects. RRCAT has also built solid state RF systems for the

characterization of Superconducting cavities at 325 MHz, 650MHz, 1.3 GHz.

•In order to achieve the desired specifications and feasibility RRCAT first

developed 1kW, 5 kW intermediate SSPA stages as a part of development and

improvements/ modifications were incorporated for realising the final 20kW

power level.

•In earlier workshop we reported a prototype 5kW SSPA development which

served as a base for development of present wide band 20kW SSPA. We have

developed the complete amplifier in-house using the design, fabrication, testing

and qualification facilities available at RRCAT.

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

Outline

• Technical requirements & Specifications

of the 20kW SSPA

• Device selection and amplifier design

• 20kW SSPA architecture

• 5kW prototype development for

feasibility and performance characteristics

studies

• Final amplifier development

• Test results

• Conclusion

CLIC DB front end

For time being only major component development: GUN, SHB, high bandwidth 500 MHz source, 1 GHZ MBK, modulator and accelerating structure in an high power test stand

Gun SHB 1-2-3

PB Buncher Acc. Structures

IOTs ?, SSPA 500 MHz

Modulator-klystrons, 1 GHz, 15 MW

~ 140 keV ~ 12 MeV

Diagnostics

~ 3 MeV

Courtesy: Steffen Doebert

Sub-harmonic bunching system Status: RF design existing, mechanical design done, Discussion with CERN work shop on realization Power source: 500 MHz, 20-115 kW, wide band (60 MHz) sources needed for fast phase switching. Solid state favored Comment: On 20kW prototype Done under collaboration with RRCAT

Hamed Shaker

SHB 1 SHB 2 SHB 3

Beam velocity 0.62 c 0.62 c 0.62 c

Current 5 A 5 A 5 A

Voltage 15 kV 30 kV 45 kV

Bunch form factor

0.058 0.57 0.73

Detuning 1.6 MHz 12.1 MHz 12.7 MHz

Courtesy: Steffen Doebert

Compact, 10kW solid state RF power amplifiers, @476 MHz using LDMOS transistors and

novel planar combiners and dividers for pre-buncher cavity of injector LINAC for CUTE

FEL and IR-FEL project at RRCAT

10kW SSPA during tests

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

A compact 10 kW, 476 MHz solid state radio frequency amplifier for pre-buncher cavity of free electron laser

injector linear accelerator. Published in: Review of Scientific Instruments (Volume:84 , Issue: 9 ) Sept 2013.

Parameter Nominal value Unit

Output power 20 kW

Frequency 499.75 MHz

Band width (3dB) 58 MHz

Pulse Length 140.3 micro sec

Repetition rate 50 Hz

Phase variation shot to shot, flat top

~1 deg

Amplitude stability ~1 %

Specifications of the 20kW Solid State Amplifier

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

RF Power LDMOS Transistors

Rugged N—Channel Enhancement--Mode Lateral MOSFETs

Withstands high VSWR industrial (including laser and plasma

exciters), broadcast (analog and digital), aerospace and radio/land

mobile applications.

• Unmatched Input and Output Allowing Wide Frequency Range

Utilization 1.8 and 600 MHz,1250 W CW, 50 V

• Single--Ended or in a Push--Pull Configuration

• Qualified Up to a Maximum of 50 VDD Operation

• Characterized from 30 V to 50 V for Extended Power Range

• Suitable for Linear Application with Appropriate Biasing

• Integrated ESD Protection with Greater Negative Gate--Source

Voltage Range

for Improved Class C Operation

• Characterized with Series Equivalent Large--Signal Impedance

Parameters

Salient Features of 20kW SSPA

• Developed using high power push-pull LDMOS transistors • The push-pull devices are operated under single ended

configuration to reduce space and improve repeatability. • The same design has been used to develop two 10 kW SSPA

at 476 MHz for injector LINACs of CUTE FEL and Indus synchrotrons.

• The 20 kW is achieved by combination of 32 transistors. • The high power combination is achieved using microstrip

line planar combiner (Wilkinson Type). • Design is highly modular, and size of each amplifier pallet

(one transistor based amplifier), is 5cmx10cm only. A single pallet can provide upto 1400W peak power.

5kW Amplifier Module 210mmx300mm

Amplifier Module enclosed and mounted on heat sink

Parameter Test Result Comments

Peak Power obtained 67.1dBm (~5120W) The maximum input power required is

+13dBm.

Gain @ 5kW 57 dB

54dB

54dB

@499.75MHz

@469.75MHz

@529.75MHz

Bandwidth (3dB) 60 MHz (+/-30MHz) Centre Frequency 499.75MHz

Pulse To Pulse Amplitude variation ~0.1dB @67.1dBm

Pulse to Pulse Phase variation ~1° @67.1dBm

In pulse amplitude variation <0.2dB @ 67.1dBm

In pulse phase variation <2° @67.1dBm

Test results of the 5kW prototype amplifier

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

Test Results of the 5kW prototype SSPA module

Test conditions: 50Hz repetition rate, 150µs pulse width, Input Power, 12.5dBm

Output Power vs Frequency response. Gain characteristics at 499.75 Mhz

Gain characteristics at 470.75 Mhz Gain characteristics at 528..75 Mhz

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

5kW prototype SSPA received at CERN undergoing tests during August 2015

5kW Wideband SSPA Delivery to CERN from RRCAT

Amplifier design

The amplifier is developed using eight amplifier modules capable of providing up to 4 kW of pulse power, which are combined by planar Wilkinson combiner and divider to generate 20 kW of pulsed output.

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

Input trigger signal 2.5V-5 V, 2 µs

(high Impedance)

The amplifier has been developed as a three stage amplifier which consists of the following

stages.

1 W Pre-driver amplifier

100 W GaN HEMT based driver amplifier

4kW High Power stage which is developed by combining 4 LDMOS transistors using

Wilkinson combiner and divider networks on low loss flexible PTFE based laminates.

8 units of 4kW modules combined to provide over 20kW output.

The switching ON time is defined by a RF switch which is having a controlled

mono-shot circuit which sends TTL signal to switch for 150µs at rising edge of the input

trigger (delay in RF ON ~200ns)

The three stages of the amplifier uses the following power supplies

1. 1W Pre-driver amplifier 24V, 600mA

2. Driver Amplifier 32V, 200mA for drain and -3.15V for Bias

3. High power stage 55V, 2A for drain and 2.15V for Bias

Description of stages of amplifier

High Power Microwave combiner (microstrip line based)

8:1

4kW amplifier modules

4kW module with 8:1 micro-strip power combiner

20kW pulsed Wide band solid state

Peak Power @

499.75MHz

≥ 73.0dBm

Gain @Peak Power

(499.75 MHz)

59 dB

3 dB bandwidth

@14dBm Input

470.75 MHz- 528.75

MHz

Pulse width

(user settable)

up to 140.3 µs

PRR up to 50 Hz

Input Connector Type-N (F)

Output Connector DIN 7/16 (F)

Pulse to pulse variation

in amplitude

< 0.1dB

Pulse to pulse variation

in phase

< 1°

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

20 kW SSPA Cabinet

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

Details of the Front Panel Controls

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

7/16 DIN ( Deutsches Institut für Normung) output connector of SSPA

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

• Heat run tests conducted in lab environment with

temperature around 25°C.

• The amplifier takes half an hour to reach thermal

equilibrium, the amplifier power reduced by around

0.2dB from cold condition to thermal equilibrium and

afterwards it remains consistent.

• The pre-driver, driver, all the eight amplifier modules

and the complete amplifier system were characterized.

• The characterization was done using a signal generator

in pulsed mode with pulse width 140.3μs and duty cycle

50 Hz.

Tests done on the 20kW SSPA at RRCAT, Indore, India

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

The subsequent images shows the amplitude and

phase response of the output pulse power at different

frequencies across the frequency band.

The amplitude shape is obtained by using a Peak

Power analyzer and the phase response is obtained

using a phase detector card.

Test conditions: 50 Hz repetition rate, 140.3 μs pulse

width, Input Power 14 dBm; Phase card response: 10

mV/degree

Amplifier amplitude and phase response

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

Picture on left is the output of the phase card which shows the variation of the output power

phase with respect to input during pulse. The right image is of detected power at peak power

analyzer. The phase card response is 10mV/degree. The two markers are set at 40 μs and 130 μs

in the lower image. The phase variation in pulse is 1.5 degree and amplitude variation ~0.2dB.

Phase and amplitude response at 470.75 MHz

The picture on left is the output of the phase card which shows the variation of

the output power phase with respect to input during pulse. The right image is of

detected power at peak power analyzer. The phase card response is

10mV/degree. The two markers are set at 40 µs and 130 µs in the lower image.

The phase variation in pulse is 3.3 degree and amplitude variation ~0.2dB.

Phase and amplitude response at 499.75 MHz

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

the picture left above is the output of the phase card which shows the variation of

the output power phase with respect to input during pulse. The image on right is of

detected power at peak power analyzer. The phase card response is 10mV/degree.

The two markers are set at 40 μs and 130 μs in the lower image. The phase

variation in pulse is 1.5 degree and amplitude variation ~0.2dB.

Phase and amplitude response at 528.75 MHz

Conclusion:

• The complete 20kW wide band SSPA has been designed, developed and

subjected to long duration endurance testing at RRCAT, Indore.

• Amplifier power reaches thermal equilibrium after 30 minutes and has

excellent phase and amplitude stability meeting specifications.

• 4 channel D. C. power supply which has stability of better than +/-0.05%

have been used as bias supplies.

• The desired specifications have been achieved and scope for further

improvements/upgrades depending upon application in the buncher can

be taken up as per feedback from the users.

• The 20kW SSPA has been delivered to CERN. Some misalignments in

the box and RF routing during transportation is being corrected after

which the final tests will be repeated at CERN.

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN

Purushottam Shrivastava, RRCAT: CLIC

WS Jan 18-22, 2016 CERN