design-for-testability techniques for 3d icstechniques for

DesignDesign--forfor--TestabilityTestabilityDesignDesign forfor Testability Testability Techniques for 3D ICsTechniques for 3D ICsTechniques for 3D ICsTechniques for 3D ICs

Jin-Fu Li f l i l i iDepartment of Electrical Engineering

National Central UniversityJhongli, Taiwan

Outline

Introduction3D Integration Technology Using TSV3D IC T t Ch ll3D IC Test ChallengesDesign-for-Testability Techniques for 3D g y qICsTest Interfaces for 3D ICsTest Interfaces for 3D ICsConclusion

Advanced Reliable Systems (ARES) Lab.EE, National Central University

2

IntroductionIntegrating more and more transistors in a single chip to support more and more powerful p pp pfunctionality is a trend

Using 2D integration technology to implement such g g gy pcomplex chips is more and more expensive and difficult

Some alternative technologies attempting to cope g p g pwith the bottlenecks of 2D integration technology have been proposedp p3D integration technology using through silicon via (TSV) has been acknowledged as one of the via (TSV) has been acknowledged as one of the future chip design technologies


3

IC Manufacturing


4

Why 3D IC?Integrating more and more transistors in a single chip to support more and more powerful p pp pfunctionality is a trend

Using 2D integration technology to implement such g g gy pcomplex chips is more and more expensive and difficult

Some alternative technologies attempting to cope g p g pwith the bottlenecks of 2D integration technology have been proposedp p3D integration technology using through silicon via (TSV) has been acknowledged as one of the via (TSV) has been acknowledged as one of the future chip design technologies


5

3D Integration Technology Using TSV

3D integration technology using TSVMultiple dies are stacked and TSV is used for the interMultiple dies are stacked and TSV is used for the inter-die interconnection

Die 1Die 2

Die 3

TSV

The fabrication flow of a 3D IC Di / f i

TSV

Die/wafer preparationDie/wafer assembly


6

An Exemplary Via-Last Process

Wafer Seed Layer Deposition

CMOS CMOS

Wafer Thinning TSV Filling

CMOS CMOS

TSV Etching Seed Layer Removal

CMOS CMOS


7Source: V. F. Pavlidis and E. G. Friedman, “Three-dimensional integrated circuits”.

Die/Wafer Assembly

Bonding technologies for 3D ICsWafer to wafer (W2W) Die to Wafer (D2W) and DieWafer-to-wafer (W2W), Die-to-Wafer (D2W), and Die-to-Die (D2D)

Comparison of different bonding technologiesComparison of different bonding technologies

D2D D2W W2WYieldFl ibilit

HighHi h

HighG d

LowPFlexibility

Production ThroughputHighLow

GoodGood

PoorHigh


8

3-Tier 3D IC Cross-Section


9

Source: E. G. Friedman, University of Rochester.

3D SiP & 3D IC

3D SiP3D IC

RF

AnalogFlash

Fl h

Analog

RF

Package

CPU

CPU

SRAM

Flash

Package

1 IO f di d 1 IOs of a die are TSVs1. IOs of a die are pads2. Number of allowed

bonding wires is medium

1. IOs of a die are TSVs2. Number of allowed

TSVs is large


10

Status of 3D IC R&DThermal

simulationCost-driven

3D EDA toolsClock-treeDesign

Yieldh t

Physical design

Scan design

Clock treesynthesis

DesignAutomation Open-access

3D EDA tools

enhancement design

Testing &DFT

Testaccess Test scheduling

DFT

Fault modelsPre-bond

Wafer/die test

Vertical Vias

Aligning,StackingManufacturing

Vertical Vias

Nearly mature Research initiated;Some tools and/or

No solution available;Research needed


11Source: H.-H. S. Lee & K. Chakrabarty, IEEE D&T, 2009

Techniques avaialbe

Test Flows of 2D & 3D ICs

Wafer Fab. 1 Wafer Fab. 2 Wafer Fab. n

3D-IC Test Flow2D-IC Test Flow

Wafer Fab.

KGD Test 1 KGD Test 2 KGD Test nWafer Test

Stacking 1+2

KGS Test 1+2

Stacking (1+2)+3Incremental

Test

KGS Test (1+2)+3Assembly & Packaging

Assembly & Packaging

KGD: Known-Good Die Test

Final Test


12

Source: Dr. Erik Jan MarinissenFinal TestKGS: Known-Good Stack Test

Test Challenges for 3D ICs

KGD (pre-bond test+burn-in test)W f l l KGD f 3D IC i diffi l Wafer-level KGD for 3D ICs is more difficult than existing KGD approaches for system-in-

k (SiP)package (SiP)KGS

DFT methodology should be able to support the incremental testincremental test

Post-bond test (final test)Test optimization

Test integration & modular testing Advanced Reliable Systems (ARES) Lab.EE, National Central University

est teg at o & odu a test g 13

3D-IC KGDWafer-level burn-in (WLBI)

Package Package Burn-In

WLBI


14

Source:ITRS 2009WLBI

3D-IC KGDWafer probing is difficult

Pitch of TSVs is much smaller than that of Pitch of TSVs is much smaller than that of probing pins of existing probe cardsTypically, TSV does not have ESD protectionp

Electrical access of TSVs is required S m t t pad h uld b impl m nt dSome test pads should be implemented


15

Economics of TestCost comparison between executing a top-die KGD test or not


16

Source: E.-J. Marinissen, et al., ITC 2009

Economics of TestTest cost of 3D ICs w.r.t. different test strategies


17

Source: D. Velenis, et al., 3D-IC conf. 2009

Outline

Introduction3D I i T h l U i TSV3D Integration Technology Using TSV3D IC Test Challenges3D IC Test ChallengesDesign-for-Testability (DFT) Techniques f 3D ICfor 3D ICsTest Interfaces for 3D ICsConclusion


18

Possible Defects in TSVs

Insulation oxide lost

Insulation discontinuity

Plating void

Seed layer discontinuity


19

Pre-Bond Testing of TSVs

An on-chip pre-bond TSV test scheme is d dneeded

To reduce the risk of bonding dies having g girreparable TSV failures and save costsTo distinguish fault-free and faulty TSVs To distinguish fault free and faulty TSVs efficiently so that the redundancy or repair strategy can be implemented with acceptable strategy can be implemented with acceptable overhead


20

Scan-Based Test for TSVs

Die 2Die 1Die 1 Die 2

FF

Scan-Out

FF

Scan-In

FFScan-In

01

To Logic

FF

FFFromLogic

FF

FF01

FFLogic

FF

Logic

FFFF01

Scan

FFFFScan

01

FFScan-Out

Scan wrapper

TSVs in Parallel Connections

Scan wrapper

TSVs in Serial Connections


21

Via-First TSV

Via-first process

I l tPoly-Si

Metal layer

Insulator

I l t l n+ n+ T

SNMOS Insulator layer (SiO2)

SV

h

Si Substratetox d


22

Characteristics of Via-First TSVs

Via-first/middle TSVs tend to be fine-pitch (≤ 15 μm) and high density (≥ 103/mm2)μm) and high-density (≥ 103/mm2)They are single-ended components with one end b i d h b k id hi h i ibl buried or on the backside which is not accessible before bondingThey cannot be tested by a scan chain, especially before wafer thinning and back metal patterningUniformity demands that the time constant of parasitic RC of a TSV is bounded p

τL ≤ τTSV ≤ τH


23

Testing Challenges High density of via-first TSVs (104/mm2)TSV failure rate remains relatively high (> 10ppm)TSV failure rate remains relatively high ( 10ppm)Individual TSVs are indistinguishable in a daisy chain or a serial scan chainchain or a serial scan chain

Difficult to rework once the test is done

They are not applicable before bonding Before bonding and thinning, TSVs have one end floating and buried deeply in the substrate


24


An open defect in the TSV

Poly-SiMetal layer

NMOS

InsulatorTSVh’n+ n+

Poly Si

Insulator layerNMOS h

Break (Open defect)

Insulator layer (SiO2)

(Open defect)

Si Substrate


25


A leakage path to ground in the TSV

Poly-SiMetal layer

Insulator

n+ n+

y

TNMOS S

VInsulator layer (SiO2)

Impurity(Resistive defect)

Si SubstrateSi Substrate


26

A Test Method for TSVsUtilize the RC constant of a TSV

Start

WE = 1: Write 1

TestMode = 1Steps

Write 1: Reset all TSVs to Vdd

R d 1 Di h d i

WE = 1: Write 1SAEN=0: Stop sensing,

WE = 0, SAEN = 1: Period = TL

1

2 Read 1: Discharge and sensing

Short term hold-on WE = 0

, LDischarge and sense2

3 Short term hold on

Read 0: Discharge and sensing

SAEN = 0: Stop sensing

WE = 0, SAEN = 1: Period = TH Discharge and sense

3

4

End TestMode = 0

Discharge and sense


27

Source: P.-Y. Chen, et al., ATS 2009

Thresholds of TSV Sensing

Specify the range as CL ≤ CTSV ≤ CH

Discharge for T and TDischarge for TL and TH

Sense and amplify in Read-1 and Read-0VX

VDD

Read 1 Read 0DD

CHVth H

Vth_LCL

CTSVth_H

Discharge timeTL TH


28

Pre-Bond Testing ApproachA test module (TM) includes a write buffer, a pull-down (PD) circuit, and a sense amp (SA)p ( ) p ( )A MUX is used to select between test and normal modesmodes

TSVMTo

To Normal Function CircuitVref TSV

R CTSV

MUX

StorageSA VX = VSensing point

ref

RTSV TSV

SAENTestMode S b t t (V )

WEPDCircuit

Mode

Discharge

Substrate (VSS)

1 / 0


29


Testing Multiple TSVs

Test Controller Result Collector TestOutputs

Test Commands

Test Mode Test Signals Test Address

p

TM FF

TMNormalFunctionCircuit

FF FF TM

…

…

…

…

TM T M d l FF Fli Fl

TM FF


30

TM: Test Module FF: Flip FlopSource: P.-Y. Chen, et al., ATS 2009

Using Inverter for SensingUse two inverters to “sense and amplify” and a NMOS transistor as the pull down circuitNMOS t a s sto as t e pu do c cu tVth_H and Vth_L merge to one Vth_INV

VX

VDD

Read 1 Read 0DD

CHVth INV

CL

CTSVth_INV

Discharge timeTL TH


31


Test IslandLayer test controller with IEEE 1149.1 TAP

Reusesable scan chain design in pre-bond and post-bond testing

Layer test controllerLayer test controller(LTC)

*Ref: D. L. Lewis, ITC’07


32

Clock Tree Design for TestUse redundant clock tree for the layer w/o normal clock tree

Wire length and power optimizedPre-bond untestable

Pre-bond testable, area and power wasting

Wire length and power Pre-bond test clock

Wire length and power optimized

Pre-bond testable


33*Ref: D. L. Lewis, ITC’07

Partial Circuit TestingBit-split Kogge-Stone adder

Add scan registers at the TSV edgeai bi

4567 0123

an

op

pigigi-1

pi-1gi-2p

TSV

ci 1

sc flo

ci

pi-2gi-n/2

pi-n/2

i-1

si

1357 0246 13573D bit-split

designg


34*Ref: D. L. Lewis, ISVLSI’09

Partial Circuit TestingPort-split register file

Test patterns are reducedSet test pattern on

one write port

Enable write port and all read portsp

Check read data write dataread data = write dataread port

Traditional Traditional test algorithm write port


35

*Ref: D. L. Lewis, ISVLSI’09

Post-Pond TSV Testing

core

TSV array

TSV array arrayarray

core core

Die 1 Die 2


36

Post-Pond TSV Testing

die1 die2 die3die1 die2 die3

WSI

WSCWSO


37

Outline

Introduction3D I i T h l U i TSV3D Integration Technology Using TSV3D IC Test Challenges3D IC Test ChallengesDesign-for-Testability (DFT) Techniques f 3D Ifor 3D IcsTest Interfaces for 3D ICsConclusion


38

Test Interface for 3D ICs

IntroductionReview of IEEE Std. 1149.1, 1500, and 1149.7 E t i f C t T t St d d f 3D Extensions of Current Test Standards for 3D ICs


39

Introduction

3D integration using through silicon via (TSV) is a promising IC design technology(TSV) is a promising IC design technology

Heterogeneous integration, high performance, low power, …

One of the challenges of 3D ICsgTesting

St d di d t t i t f (i t t Standardized test interface (i.e., test access architecture) is needed

Test reuse


40

IEEE 1149.1 & 1500 for SOCsSystem-on-Board System-on-Chip

1500

1149.1

System-on-Chipy p


41

IEEE 1149.1 (JTAG)


42

State Diagram of the TAP Controller

Load InstructionTest Application


43

Serial Board/MCM Scan


44

Parallel Board/MCM Scan


45

Independent Board/MCM Scan


46

IEEE 1500 Test Wrapper

Test stimuli Test responseWPI WPOCore

WB

R

WB

R

Functional Functional

Test response WPI WPO

WBY

data data

WBY

WIR WSOWSI

WSC


47

Wrapper Interface Ports

WrapperParallel Control

Optional WrapperParallel Port (WPP)

User Defined Portfor Test Flexibility

WPCWrapperParallel Input

WrapperParallel Output

Parallel Control

WPI WPO

Core

WrapperWSI WSOWrapper

Serial InputWrapper

Serial OutputWSCWrapper

Serial ControlStandardized Portfor Plug & Play

Required WrapperSerial Port (WSP)


48

for Plug & PlaySerial Port (WSP)

Wrapper Serial Control (WSC)

WRSTWCLKWSC

Wrapper

CoreWCLK

SelectWRCapture

Shift

WSCControls& Clock

ShiftUpdate

Transfer


49

IEEE 1149.7

1149.1 Core1149.7 AdAdapter


50

IEEE 1149.7 Classes

T5Scan+Data Channels with two or four pins, custom protocols

T4Scan with two/four pins in Star-2 Scan Topology

AdvancedCapability

p p gyT3

Star-4 Scan TopologiesT2T2

Chip bypass in a Series Scan TopologyT1

ExtendedCapability

Basic TAP.7 control, functionality extensions

T0IEEE 1149.1 Specified Behavior with

LegacyC bilit p

multiple on-chip TAP.1sCapability


51

IEEE 1149.7 Star-4 Configuration

TAP 1

TCK TMS TDI TDOParallel TDI/TDO

TAP 2TCK TCKTMS TMS

TDITDO

TDITDO

TCK TMS TDI TDO

TAP 3


52

IEEE 1149.7 Star-2 Configuration

TAP 1

TCK TMS TDI TDOMultiplexed

TMS/TDI/TDO

TAP 2TCK TCK

TMS TDITMSTDO

TCK TMS TDI TDO

TAP 3


53

IEEE 1149.7 Class T5 ─ An Example

TAP 1

TAP 2TCKTMSTMS

Custom-InCustom-Out

TAP 3TAP 3


54

Test Interface for 3D ICsStandardized test interface (test access architecture) for 3D IC is neededo 3 C s eeded

Data and control bandwidthTest standard

Test Interface

ANALOG

Test standardHardware

Test Interface

FLASH

Test Interface

Software Purpose

Test Interface

Test Interface

CPU

SRAMp

Test reuse

Test Interface

CPU


55

Data and Control Bandwidth

Die 1

1149.1 Switch

Die 1

Die 2

1149.1 Switch

Die 3

1149.1 Switch

TDI TDOTMS TCK TAM


56

Current 2D Method for SOB

Chip/Die Chip/Die Chip/Die

TAP TAP TAP

1149 1

TDOTDI TMS TCK

1149.1

Hardware

BSDLSoftware


57

BSDLSoftware

Current 2D Method for SOCs

Source: E. J. Marinissen, et al., VTS 2010

1149 1 15001149.1 1500

Hardware

BSDL CTLSoftware


58

BSDL CTLSoftware

Test Flows of 2D & 3D ICs

Wafer Fab. 1 Wafer Fab. 2 Wafer Fab. n

3D-IC Test Flow2D-IC Test Flow

Wafer Fab.

KGD Test 1 KGD Test 2 KGD Test nWafer Test

Stacking 1+2

KGS Test 1+2

Stacking (1+2)+3Incremental

Test

KGS Test (1+2)+3Assembly & Packaging

Assembly & Packaging

KGD: Known-Good Die Test

Final Test


59

Source: Dr. Erik Jan MarinissenFinal TestKGS: Known-Good Stack Test

Standardized Test Interface for 3D ICs Requirements

Support pre-bond (KGD), KGS, and post-bond testingSupport pre bond (KGD), KGS, and post bond testingCan handle different DFT circuits

E.g., IEEE std 1500 wrapped cores, logic BIST, memory BIST, g , pp , g , y ,etc.

1149.1/1149.7 compliance in chip levelPhysical position of the test interface should be defined

h l f hThe X-Y locations of the test TSVsDescription languages for the test interface….


60

1149.1 Compliance

Main highlights from 1149.1 standard:Can have only one TAPCan have only one TAPShall have a BYPASS register with a length of exactly one bitbitCan have an optional ID register with a length of exactly 32 bitsyCan have an optional TRST* pin that, when activated, resets all TAP controller logic to the defined “test glogic reset” stateShall have a BSDL file describing the implementation details

[Source: F de Jong and A Biewenga ”SiP TAP: JTAG for SiP” ITC 2006 ]


61

[Source: F. de Jong and A. Biewenga, SiP-TAP: JTAG for SiP , ITC 2006.]

Die with 1149.1Straightforward daisy-chain connection

TDITDO Die 1

TDITDO Die 2

TSV

TDITDO Die 3

TSV

TDITDO Die 4

TDITDO

Number of BYPASS registers is larger than 1


62

Number of BYPASS registers is larger than 1

TDI-TDO Connection

Board-level testingIn BYPASS mode the

TDODie 1

In BYPASS mode, the selection signal of muxs is set to 1Die 2

TDI0 1

Only one-bit BYPASS exists between the TDI

TDO

TDI0 1

and TDO of the 3D ICTDO

Die 3

0 1

TDODie 4

TDI0

TDO

TDI0 1


63

TDO TDI

Physical Location of Test TSVs

Different dies may have different TAM widths Location of TAM should be specifiedLocation of TAM should be specifiedLocation of TAM in each die should be the same

Die 1

Switch

Die 2

S i hSwitch


64

SOC-Level Test Access Architecture


65


Die-Level Wrapper Proposed by IMEC

WPO WPIs

bypass

Switch

bypass

Scan chain

Switch

WPI WPOs

box

Scan chain

WBR box

WIRWSI

WSO WSIs

WSOsWIR

WSC

WSI WSOs

WSCs


66


Test Access Architecture Proposed by IMECIMEC

bypassWPO

bypassWPO

bypassWPO

Switch b

bypass

bypass

SChain

Switch b

Switch b

bypass

bypass

SChain

Switch b

Switch b

bypass

bypass

SChain

Switch b

WPI

box

SChain

WBR

box

box

SChain

WBRbox

WSO

WPI

box

SChain

WBR

box

WSO

WPIWPI

1

TDO

TMS

TRST

WIR WIRWSC

WSIWIR

WSC

WSI

149.1

TDITCK

TMS


67


Example• ParallelPrebondBypassTurn

bypass

WPO WPIs

Switc

bypass

bypass

SwitcWPI WPOsch box

Scan chain

Scan chain

ch box

WPI WPOs

WBR

WSO WSIs

WIR

WSC

WSI WSOs

WSCs


68

Source: E. J. Marinissen, DATE 2010

Example

S

bypass

S

WPO

S

bypass

S

WPO

S

bypass

S

WPO

Switch box

bypass

SChain

SChain

Switch box

Switch box

bypass

SChain

SChain

Switch boxWPI

Switch box

bypass

SChain

SChain

Switch boxWPIWPI

TDO

WI

WBR

WI

WBR

WSC

WSI

WSO

WI

WBR

WSC

WSI

WSO1149.1

TDO

TCK

TMSTRST

R RWSC RWSC

1

TDI

SerialPostbond IntestElevatorS i lP tb d I t tT

SerialPostbond BypassTurn

SerialPostbond IntestTurn


69


Conceptual DFT Architecture for 3D ICs


70


TiTi Test Integration Architecture

1500 WCITDITUTDOTU

Slave Die

TDI 1500 WCI

TMS TDOTDI

TDOTDTDITD

Slave Die

…TSV

1500 WCITDITUTDOTU

TDOTDTDITD

Master DieTMS TDOTDI

JTAG/1500 CI TDITTDOT


71

TMS TDOTDI Source: C.-W. Chou, et al., ATS 2010

JTAG/1500 CI

M‐FSMA WSOMaster Die

Deco

OR

TMSCLK

IEEE 1500

WSO

Selection Register

oder

CLKB WSI

WSC

Bypass Register

Boundary Register

MUX2

MU

TDI

IEEE

WSO

Interface IRUX1

TDO

IEEE 1500

WSIInstruction Register

SwitchTDO

TDIT

TDOT


72

Source: C.-W. Chou, et al., ATS 2010

M-FSM

Test Logic Reset1 0

1 1 1Run Test/Idle Select-DR

Capture-DR

Select-IR

Capture-IR

0

0

0

0

1 10

Shift-DR

Exit-DR

Shift-IR

Exit-IR

0

0 0

0

1 1

Exit-DR

Pause-DR

Exit-IR

Pause-IR0

00

0

0

1

01 1

1

Exit-DR

Update-DR

Exit-IR

Update-IR

0 0

1 1

0 01 1


73


1500 WCI

Slave Die

S‐FSMTMS

AIEEE 1500

WSO

MUX

CLK BWSI

W

MU

TDI

TDO

WSOWSC

BR

IIR

X Decode

SR

TDOTD

TDITD

TDO

TDI Switch

TDOIEEE 1500

WSI

erTDOTU

TDITUTU


74


S-FSMTest Logic Reset

R T t/Idl S l t DR

1 01

1

Run Test/Idle Select-DR

Capture-DR

0

0

10

Shift-DR

Update DR

0

01

Update-DR

Capture/Shift-IR0

0

0

1

1

Update-IR

Exit-DR

0 1

1

Exit-DR

0 1


75


Overall Test Access Architecture

TAM

_ou

TAM Switch Box

TAM

_inut

TAM Switch BoxTAM Switch Box

15001500

…15001500

…15001500

…TSV TSV

WSO

T

15001500

………

TD15001500

………

TD TD

SO

15001500

………

TSV TSV

TD

JTAG/1500 CI

WSI WSOWSC

TDIT

T TD

OTD

1500 WCI

WSI WSOWSC

TD

OTD

TD

ITU

1500 WCI

WSI WSOWSC

DITU

TTDO

T

TDITD TMS TCKTDI TDO

TDITD

DO

TUTMS TCKTDI TDO

TDO

TU


76

TMS TCKTDI TDO Source: C.-W. Chou, et al., ATS 2010

Test Operation Flow

Set M‐TiTi IR

Set M‐TiTi & S‐TiTi IIR

S t M t & Sl WIRApply 1149 1 Test Vectors Set Master & Slave 1500 WIRApply 1149.1 Test Vectors

Apply Test Vectors

3D IC TestBoard Level

Test

Capture responses & Analysis


77

How to Deal with RAM Dies?


78

DFT Technique for 3D DRAMs

BISTRAM

Normal ……

BISTRAM

TSVs

… … DFTTSVsCollar

BIST_CTR

Collar

…

Source: G. H. Loh, ISCA 2008 Processor


79

TiTi Extension for Controlling MBIST/MBISR

MBCITDITU

TDOTU

Slave Die

TDOTDITD

TDITDO

Slave DieTMS TDOTDI

TDOTD

MBCI

TMS TDOTDI

TDITUTDOTU

TDOTD

TDITD

TDITUTDOTU

Slave Die

TMS TDOTDI

…TSV

1500 WCI

TMS TDOTDI

TDITUTDOTU

TDOTD

TDITD

JTAG/1500 CI TDITTDOT

Master Die


80TMS TDOTDI

TTDOT

MBIST/MBISR Control Interface (MBCI)

Slave Die

S-FSMTMS D

ec.

csi_encso

MBCI

MU

X

TCK

MU

X

mor

y

/BIS

R

TDO

BR

IIR

X

SR

Mem

BIS

T/

unrepStatus

MonitorTDOTU

TDOTD

TDITD

cmd_done

TDI

SwitchBox

csiTDITU

TU

TDI


81

Conceptual Test Interface for 3D ICs Using 1149 7 1149 1 and 1500Using 1149.7, 1149.1, and 1500

X-Y Location of Test TSVs Physical Information

1149.1 1500Hardware 1149.7TMS

S ft

TCK

BSDL CTLSoftware HSDL

Why IEEE 1149.7y1. Low pin/TSV cost2. Solve the “multiple TAPs” per chip problem


82

3. Can provide high bandwidth

Summary: Standardized Test Interface

Requirements of standardized test interface for 3D ICs3D ICs

Support the test access in the phases of the pre-bond (KGD) test KGS test and post bond test (KGD) test, KGS test, and post-bond test X-Y location of test TSVs1149 1/1149 7 Compliance 1149.1/1149.7 Compliance Description languages for all levels of test interfacesPortable test ectors Portable test vectors Support the test access of memory BIST of 3D RAMsC t l th it hi b t KGD d d t k d Control the switching between KGD pads and stacked TSVs


83

…

Conclusion

3D integration technology using TSV is one of f IC d i h l ifuture IC design technologiesIt can offer many advantages over the 2D integration technologyHowever, there are some challenges should be , govercome before volume-production of TSV-based 3D IC becomes possiblepTest challenge is one big challenge

Effective test techniques must be developedEffective test techniques must be developed


84

design-for-testability techniques for 3d icstechniques for

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