design methodologies and circuit technologies for embedded systems...
TRANSCRIPT
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Benny Thörnberg
Associate Professor in Electronics
Design Methodologies and Circuit Technologies for Embedded Systems
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Goal with this lecture
• Introduce you to the concepts of software hardware co-design
• Stimulate you to analyze and reflect on the Xilinx Vivado system development methodology that you are using in your projects
• How good is the Vivado workflow to handle co-design?
• Introduce basics concepts of circuit technologies for programmable hardware
• FPGA development towards SoC
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Example - Video surveillance of a carpark
Background estimation -
+
Dynamic segmentation
Image component
labelling
Computation of descriptors
Classification of intruder
Video input
Human, Animal, Car, Motorcycle
…
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Example - Video surveillance of a carpark
Background
estimation -+
Dynamic
segmentation
Image
component
labelling
Computation of
descriptors
Classification
of intruder
Video input
Human,
Animal, Car,
Motorcycle …
• What is the cost of implementing each operation?
• Cost can be a combination of speed, power, NRE cost, time-to-market …
• Estimate cost for software and different hwplatforms
• How can development work move on in parallel for all operations and for both sw and hw?
• How can we gradually refine a system specification into a synthesizable system model?
• How to verify functionality of sw on a hw platform that is not yet fully developed?
• Can High Level Synthesis be used with satisfactory result?
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What is hardware software co-design?
• The meeting of system level objectives by exploiting the tradeoffs between hardware and software in an embedded system through their concurrent design
• Concurrent design of hardware and software
• Integrated design environments
• Whole system functionality is captured in one executable specification
• No unjustified early assumptions on hardware software partitioning of functionality
• Partitioning is instead based on a Design Space Exploration where performance parameters are estimated on different HW/SW platforms
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Importance of co-design?
• Improves design quality, reduce design cycle time and cost
• Good methodology to handle growing design complexity
• Exploits advances in tools and technologies• Processor cores and multi-processor architectures
• High Level Synthesis (HLS)
• Asic design, FPGA System on Chip
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Why is co-design needed?
• Complexity of embedded systems is increasing• Control system for a washing machine
• Vision based ADAS or autonomous vehicles
• Large variation of complexity among different tasks
• Variation of nature of tasks, e.g. reactive and control flow intensive or data dominated tasks
• Most systems today include both custom designed hardware and software running on processors
• Reduce time to market
• Exploits Processor cores and heterogeneous multi-processor architectures
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The co-design problem?
• Specification of system
• Partitioning of functionality into smaller tasks executed as software or hardware modules
• Scheduling of software tasks
• Modelling of software and hardware during the design refinement process
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Traditional design flow of an embedded system
Reference
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Design flow for hardware/software co-design
Reference
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Comparison
Reference
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The SystemC approach to co-design
• C++ Class library for system modelling • Single model for both software and hardware
• Explore hardware architecture
• Support for different abstraction levels • Untimed Functional (UTF)
• Timed Functional (TF)
• Bus Cycle Accurate (BCA)
• Pin Cycle Accurate (PCA)
• Register Transfer Accurate (RT)
• Provides clear separation of communication and behavior
• Enables gradual refinement of abstraction levels for behavior and communication separately
• SystemC community at www.accellera.org
• SystemC was adopted as standard IEEE 1666-2011
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The SystemC approach to co-design
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SystemC abstractions and design flow
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Example of RTL modelling using VHDL
D Flip-Flop with Asynchronous Reset
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Example of SystemC modelling
D Flip-Flop with Asynchronous Reset
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Functional modelling using channel communication
Sequential inter-process communication and execution
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Producer
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Consumer
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Putting it all together
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The execution order in this example is A, A11, A12, A13A21, A22
Top most master port is assumed being accessed first.
In-Lined Execution
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Sequential execution semantics in multi-point
communication links
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The refinement procedure
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•Sequential communication channels are refined to concurrent cycle accurate
communication channels with a bus protocol.
•Functional processes are refined to synchronous processes, which have clocks
and resets.
Module refinement
Channel refinement
SystemC comes with three pre-defined bus protocols:
•No-handshake
•Enable-handshake
•Full-handshake
The refinement procedure
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Ex. Module refinement of producer to RTL
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Xilinx Vivado Design Suite High Level Design Flow
Reference: Xilinx User Guide 892
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Xilinx Vivado handoff to software development in SDK
Reference: Xilinx User Guide 898
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Xilinx Vivado is an IP centric system development suite
• IP core – Intellectual Property is a bundle of:• Synthesizable hardware description
• Software driver
• Test bench
• An IP-XACT xml-file description of meta-data
• IP-XACT is standardized in IEEE 1685-2009
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Vivado High Level Synthesis (HLS)
Reference: Xilinx User Guide 902
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Circuit Technologies for Programmable Logic
• Historical review – Programmable Array Logic
• Field Programmable Gate Arrays• CLB – Configurable Logic Block
• IOB – I/O Block
• Programmability
• From FPGA to SoC
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History - Programmable Array Logic – PAL
• Pre-fabricated building blocks with many AND/OR gates
• Is really build on NOR or NAND gates
• The circuit can be configured (programmed) by breakinginterconnection
• Block diagram for programmable circuit implementing logicexxpressions on sum-of-product form
• • •
inputs
AND
matrix
• • •
outputs
OR
matrixproduct
term
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Before Programming
• All possible connections are available before programming
AND-plane
Programmable connection
OR-plane
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• Connections are removed
• ’Fuse’ normally connected, remove not needed ones
• ’Anti-fuse’ (normally no-connection, create connections)
A B C
F1 F2 F3F0
AB
B'C
AC'
B'C'
A
After Programming
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• Simplified notation – all wires are not drawn
• Show that there is a connection to the input
• Implement F0=AB + A’B’ and F1=CD’ + C’D
AB+A'B'CD'+C'D
AB
A'B'
CD'
C'D
A B C D
Example
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• Alternative 1: ”CPLD” (Complex Prog. Logic Device)
• Put lots of PALs onto the same chip
• Add programmable interconnects between the PALs
• Alternative 2: ”FPGA”
• Pool of logic building blocks and pool of signal routing
• Called Field Programmable Gate Array (FPGA)
• That requires
• A way to implement configurable logic gates
• A way to make the configurable interconnections
Building large programmable circuits
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• Logic block
• Implements combinatorialand sequential logic
• Interconnects
• Wires connecting in-and outputs to logic blocks
• I/O block
• Special block for external connection of signals
Field Programmable Gate Array - FPGA
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Configurable Logic Block - CLB
3-input
LUT
3-input
LUT
*
*
*O
A
B
C
D
D-FF
D Q*
Out
Clk
O
O
O
O
O
• Simplified model for a CLB
• Lookup tables – LUTs are memories
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Configurable I/O Block - IOB
• Simplified model for an IOB
Pad*
D-FF
D Q*
Clk
D-FF
Q D
*
*
Out
In
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Programmability
• Volatile configuration
• Non Volatile configuration
SRAM
FLASH
One Time Programmable - OTP • Actel• QuickLogic• MicroChip
• Actel• QuickLogic• Lattice
• Xilinx• Altera
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Programmability
SRAM memory cell Floating gate transistor � FLASH
Source Drain
Gate
Floating gate
Example of OTP
metal-to-metal connection
Volatile Non Volatile
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From FPGA towards System on Chip - SoC
• FPGAs have evolved towards a heterogeneous platform for computation
• Programmable Logic Area – PLA
• CLBs
• Block-RAMs
• Pool of ALU blocks
• Adders
• Multipliers
• Dynamic memory controllers
• Configurable Processor System
• Memory controller
• Communication interfaces
• System bus connection to PLA