design of 10 ghz two stage rf low noise amplifier1 design of 10 ghz two stage rf low noise amplifier...

1

Design of

10 GHz Two Stage RF Low noise amplifier

Group No. #3

Submitted On : 4/8/2016

Avinash Parasuraman axp145330

Johns George jxg142830

Krishna Prasad Sreenivassa Rao kxs141030

Manjunath Swamy mxs144630

2

OBJECTIVE:

To design a 2 Stage Low Noise Amplifier (LNA) using RF and Microwave concepts.

DESIGN SPECIFICATIONS:

INTRODUCTION:

Low Noise Amplifier (LNA) is a specific type of linear amplifier that is primarily used to decrease

the overall Noise Figure (NF) of the system. RF devices add noise to the system which is characterized by

the Noise Figure. The input to the RF amplifier is usually the combination of signal and noise, measured

as SNR, which is equally amplified at the output of the amplifier. Apart from this, the amplifier adds extra

noise to the incoming signal thereby causing a degradation in SNR. Since the extra noise added is

inevitable, LNA is designed to minimize the effect of this noise in the system.

The Noise Figure (or Noise Factor) in a system is calculated as the ratio of the input SNR to the

output SNR,

𝑵𝑭 (𝒍𝒊𝒏𝒆𝒂𝒓) =𝑺𝑵𝑹𝒊𝒏

𝑺𝑵𝑹𝒐𝒖𝒕

𝑵𝑭 (𝒅𝑩) = 𝑺𝑵𝑹𝒊𝒏(𝒅𝑩) − 𝑺𝑵𝑹𝒐𝒖𝒕 (𝒅𝑩)

From the above relation, it is evident that the Signal-to-Noise-Ratio in a system is continually

degraded as it passes through passive devices like filters, mixers, power amplifiers etc., If we consider the

noise factors of these passive components as 𝐹1, 𝐹2, 𝐹3 … and the Gains (or Loss) of the components as

𝐺1, 𝐺2, 𝐺3 … , the overall noise factor of the system can be calculated using the following relation,

𝑭𝒄𝒂𝒔𝒄𝒂𝒅𝒆𝒅 = 𝑭𝟏 +𝑭𝟐 − 𝟏

𝑮𝟏+

𝑭𝟑 − 𝟏

𝑮𝟏𝑮𝟐+ ⋯

From the above mathematical relation, it can be proved that cascaded NF is prominently

dependent on the NF of the first element in the series. Therefore, when LNA is placed at the beginning of

the system, it reduces the overall NF due to its inherent characteristic. A typical block diagram of a 2 stage

LNA is shown below,

PARAMETER DESIGN GOAL

Center Frequency (GHz) 10

Bandwidth B3dB (GHz) 3<B3dB<4

Bandwidth B20dB (GHz) 4<B20dB<6

Noise Figure (dB) <2

Gain at Center Frequency (dB) >18

Gain outside B20dB (dB) <-3

Output Return Loss (dB) >10

Stability Unconditional

Vcc (V) 3.3

3

Figure 1 High level block diagram of LNA

Usually in a power amplifier, conjugate matching is performed to get maximum available power

from the network. Since low NF is the objective of an LNA, optimum source reflection coefficient (Γ𝑠,𝑜𝑝𝑡)

is selected to get good NF at the expense of the input matching.

All simulations are performed using AWR Design Environment 12. The microstrip parameters used

for this project are tabulated below,

PARAMETER VALUE

Conductor Copper

Conductor thickness 17 𝜇𝑚

Metal Bulk resistivity (𝜌) normalized to gold 0.706

Substrate dielectric constant (𝜖𝑟) 3

Substrate thickness 508 𝜇𝑚

Loss tangent (tan 𝑑) 0.0009

a. Gain and Noise figure budget

From the given specifications, we see that the overall gain obtainable from the 2-stage amplifier should

be

i. Greater than 18 dB at the center frequency = 10 GHz.

ii. Lesser than -3 dB beyond the 20 dB Bandwidth

Ideally, for the given 2-stage amplifier system, the noise added by the first stage contributes heavily to

the noise of the overall system. Additionally, the gain of the first stage varies inversely as the noise added

by the other stages after the first gain stage. Thus, a low noise figure and good gain added by the amplifier

would set the stage for a low noise figure for the overall amplifier.

4

As mentioned above, the first stage is designed for a minimum noise figure. Which implies that the

matching network that is designed between the input of the amplifier and source (with a 50 Ω source

impedance) is designed not for maximum power transfer, but it is designed such that the reflection at the

input of the amplifier (Γ𝑠) is equal to Γ𝑜𝑝𝑡, the reflection co-efficient associated with a minimum noise

figure. Thus, maximum power transfer (and hence maximum gain) is sacrificed in this first stage to obtain

a minimum noise figure, and this is confirmed by the non-zero reflection (𝑆11) at the input.

The output of the first stage is conjugate matched to 50 Ω, and the input of the second stage amplifier is

matched such that Γ𝑠 = Γ𝑜𝑝𝑡 for minimum noise figure. Hence the second transistor is also designed for

minimum noise figure.

Calculations for the gain of individual stages, cascaded gain and cascaded noise figure follow:

From AWR (as shown in the figure below):

Γ𝑜𝑝𝑡 = 0.52∠ − 158° (reflection co-efficient corresponding to the minimum noise figure of 1.3 dB).

Cascaded Gain:

For achieving minimum noise figure at the input, Γ𝑠 = Γ𝑜𝑝𝑡. The expression for Available Gain (𝐺𝐴) is given

by:

𝐺𝐴 = |𝑆21|2.1 − |Γ𝑠|2

(1 − |𝑆22 − Δ. Γ𝑠

2

1 − 𝑆11. Γ𝑠|) . |1 − 𝑆11. Γ𝑠|2

Calculating 𝐺𝐴 with the S-parameters given in the S2P file for 10 GHz, we obtain a value of 𝐺𝐴 = 9.92 𝑑𝐵.

Since the second stage again sees a minimum noise figure, cascaded gain is given by 𝑮𝑨(𝒅𝑩) +

𝑮𝑨(𝒅𝑩) = 𝟏𝟗. 𝟖𝟒 𝒅𝑩.

5

Figure 2. Noise figure circles

Cascaded Noise Figure:

i. Without feedback resistor

First stage is designed for minimum noise figure. Thus 𝐹1(𝑑𝐵) = 1.3 𝑑𝐵 => 𝐹1 = 100.13 = 1.349

Second stage is designed for maximum gain and minimum noise figure. Again, since , Γ𝑠 = Γ𝑜𝑝𝑡, 𝐹2 =

1.349. And the cascaded noise figure is given by:

𝐹 = 𝐹1 +𝐹2−1

𝐺𝐴1 = 1.349 +

0.349

101.984 = 1.352 => 1.309 dB

ii. With feedback resistor

The inclusion of the feedback resistor for stability in the input and the output stages increases the noise

figure from the ideal value. The feedback resistors included are of the order of 700 Ω. The schematic for

the input and the output matching networks with feedback resistors and bias network (𝜆

4 lines), DC block

capacitors and DC power supply together with the noise figure of the first amplifier stage is shown below

as an example.

6

Figure 3. Schematic of the first stage transistor

Figure 4. Noise figure of the first stage transistor

The overall noise figure of the circuit after simulation from AWR is F = 1.79 dB. This includes the noise

figure due to individual stages and the filter as well. Also, the inter stage and the output matching

networks (discussed later) were tuned to obtain desired S22 response and bandwidth which eventually

changed the noise figure from its theoretical value. Additionally, since microstrip is a lossy material

defined by its non-zero loss tangent, presence of transmission lines or any such microstrip elements on

the dielectric is bound to be lossy which is reflected in the noise figure. Thus, noise figure obtained

theoretically is lesser than the cascaded noise figure found through AWR.

1

2

SUBCKTID=S1NET="Project2_NEC_Spars_3V_10mA_complete_noise"

PORTP=1Z=50 Ohm PORT

P=2Z=50 Ohm

RESID=R1R=R Ohm

CAPID=C5C=100 pF

DCVSID=V3V=3.3 V

MLINID=TL11W=w umL=4793 umMSUB=SUB1

MLEFID=TL2W=w umL=ih um

MLINID=TL1W=w umL=ie um

MLINID=TL9W=w umL=4793 um

CAPID=C1C=100 pF

CAPID=C3C=100 pF

DCVSID=V1V=3.3 V

CAPID=C6C=100 pF

R=700

7

The final response is shown in the graph below. Gain is tuned and adjusted to 18.9 dB to obtain the 3dB

bandwidth while the total noise figure is maintained at 1.79 dB at 10 GHz.

Figure 5. Gain, Noise Figure and Output return loss

b. Matching network design

As mentioned earlier, the input and the inter stage matching network is designed for a minimum noise

figure and the output matching network also is designed for maximum power transfer.

i. Input matching network

Γ𝑜𝑝𝑡 = 0.52∠ − 158° is the point of minimum noise figure (1.3 dB). This is the Γ𝑠 at the input of the first

transistor to achieve a minimum noise figure. A shunt microstrip stub and the series microstrip line

achieve the matching. Since it is matched for a minimum noise figure, the input of the transistor is not

perfectly matched to the source, and thus maximum power is not transferred from the source to the input

of the transistor. The first stage of the amplifier is shown in the figure, with the matching network between

the transistor and the port. The capacitors are meant for DC blocking and does not interfere with

matching.

8

Figure 6. Matching indicated in Smith's chart

The figure above indicates matching designed using AWR on the Smith’s chart with the circuit schematic

shown in the figure.

Figure 7. Schematic of first stage transistor

R=700

ie=957.8 ih=2451w=1259.26

PORTP=1Z=50 Ohm


CAPID=C5C=100 pF

CAPID=C3C=100 pF

CAPID=C6C=100 pF

DCVSID=V3V=3.3 V

DCVSID=V1V=3.3 V

CAPID=C1C=100 pF




RESID=R1R=R Ohm

1

2


9

ii. Output matching network

The output matching network is designed to match the output of the amplifier to 50 Ω, ensuring maximum

power transfer. Additionally, since there are low pass and high pass filters present, additional matching

networks were required to match the output to 50 Ω.

The 𝑆22∗ of the second stage amplifier is matched to 50 Ω. This is because 𝑆22 of the second stage amplifier

gives Γ𝑜𝑢𝑡. Thus Γ𝑜𝑢𝑡∗ is matched to 50 Ω for maximum power transfer to the load.

Figure 8. S22 and conjugate displayed in smith's chart

iii. Interstage Matching network

Designing the interstage matching network is a bit complex, considering the fact that we have to

match 𝛤𝑜𝑢𝑡∗ (. 𝑖𝑒. 𝑆22

∗ ) of the first stage with 𝛤𝑜𝑝𝑡 of the second stage so that we can get minimum noise

figure. So ideally, in this case of inter stage matching, we combine the output matching network and

the input matching network in such a way that the 𝛤𝑜𝑢𝑡∗ of the first stage is first matched to 50Ω and

then the 50Ω is matched to 𝛤𝑜𝑝𝑡of the second stage.

10

Figure 9. Interstage matching network

𝛤𝑜𝑢𝑡 = 0.4815∠ − 150.9° 𝛤𝑜𝑢𝑡

∗ = 0.4815∠150.9° Γ𝑜𝑝𝑡 = 0.52∠ − 158°

w=1259.26

ie=957.8

ih=2451

oh=1777

oe=1415

RESID=R1R=R Ohm


RESID=R2R=R Ohm

CAPID=C1C=100 pF


CAPID=C2C=100 pF



DCVSID=V2V=3.3 V

DCVSID=V1V=3.3 V

1

2


1

2


CAPID=C5C=100 pF DCVS

ID=V4V=3.3 V



CAPID=C6C=100 pF

DCVSID=V3V=3.3 V

CAPID=C7C=100 pF

CAPID=C4C=100 pF

CAPID=C8C=100 pF

MLEFID=TL22W=w umL=1357 um


CAPID=C10C=100 pF

11

c. Bias network design

The bias network consists of the following and can be seen from the schematic as well:

a. DC power supplies at the gate and drain

b. DC block capacitors

c. 𝜆

4 transmission lines (@ 10 GHz)

Figure 10. First stage of the amplifier with bias networks

A small portion of the full schematic of the amplifier circuit is shown on the left displaying the bias

networks of the transistor.

1. The 𝜆

4 line at the gate of the transistor acts as an open at the end of the transmission line to AC signals

at 10 GHz and is thus prevented from entering the source

2. The capacitor in shunt with the DC source is a short any AC signals

3. The series capacitor in front of the transistors’ gate and drain terminals is a DC block capacitor to

prevent DC from the previous stage to bias the transistor’s gate

4. The series capacitor in the feedback network is also for DC blocking

RESID=R2R=R Ohm

CAPID=C2C=100 pF

DCVSID=V2V=0.3 V

1

2


CAPID=C9C=100 pF


DCVSID=V4V=3.3 V

CAPID=C4C=100 pF


CAPID=C7C=100 pF

CAPID=C8C=100 pF

12

5. The high value of capacitors (100pF) ensures that there is no significant impact in the matching or

stability of the amplifiers. Also, the 𝜆

4 section, being an open to AC at 10 GHz does not impact matching or

stability. The DC sources act as AC ground ensuring no impact in performance.

d. Stability Analysis

Since amplifiers are active devices, it is possible that they can function as an oscillator. Stability analysis is

performed on each stage of amplifier to ensure that the final amplifier does not oscillate in any frequency.

This can be broadly classified into 2 types,

Unconditionally Stable – The amplifier is stable for all the frequencies

Potentially Unstable – The amplifier is not unconditionally stable

An amplifier can be classified as Unconditionally Stable in 2 ways,

Plot K and Δ values across all frequencies. Condition : 𝒌 > 𝟏 & |𝚫| < 𝟏 ,

Where 𝒌 =𝟏−|𝑺𝟏𝟏|𝟐−|𝑺𝟐𝟐|𝟐+|𝚫|𝟐

𝟐|𝑺𝟐𝟏𝑺𝟏𝟐| and 𝚫 = 𝑺𝟏𝟏𝑺𝟐𝟐 − 𝑺𝟐𝟏𝑺𝟏𝟐

Plot input and output stability circles for all frequencies. Condition: The reflection coefficients Γ𝑠

and Γ𝐿 lies with the stable region determined by the stability circles. In other words, if all the

stability circles lie outside the smith chart then unconditional stability is achieved.

The S2P file for the transistor is imported into AWR and the stability circles are plotted to check for

stability.

Figure 11 Schematic of transistor

1

2


PORTP=1Z=50 Ohm

PORTP=2Z=50 Ohm

13

Figure 12 Stability circles for transistor

Since few stability circles lie within the smith chart, the amplifier is not unconditionally stable. A resistor

is added in parallel to the transistor to achieve unconditional stability.

Figure 13 Schematic of transistor with feedback resistor

A plot of stability circle shows that none of the circles lie inside the smith chart.

RESID=R1R=500 Ohm

1

2


PORTP=1Z=50 Ohm

PORTP=2Z=50 Ohm

14

Figure 14 Stability analysis of modified circuit

15

The values of K and B1 for all frequencies are displayed in the following table. Observe that k>1 and B1 >

0 for all frequencies.

Figure 15 K and B1 plots for individual transistor

16

After the stability of individual stages are taken care of, it is important to check the stability for complete

circuit. This can be verified by plotting stability circles or K and B1 factor which is shown below,

Figure 16 Stability circles for final stage

17

Figure 17 K and B1 analysis

From the stability plot and K & B1 values we can establish the stability of the Low Noise Amplifier.

18

e. Performance Analysis

The amplifier circuit was designed initially and then tuned to obtain the optimum gain and noise figure

and return loss. But since the 3-dB and 20-dB bandwidth requirements were not met, the matching

networks were redesigned, and then filters were added in the output to meet the bandwidth requirement.

The filter module at the output consists of three filters in parallel in the form of a triplexer. The triplexer

designed here is a combination of Low Pass, High Pass and Band Pass filter. While the desired bandwidth

can be achieved with just a bandpass filter, the purpose of the low pass and the high pass filter are

explained below.

Low Pass filter: Due to the high gain in the low band (below 8 GHz), a low pass filter is used to filter all low

frequency signals to matched load. Since band pass filters typically reflect out-of-band signals (because

they are designed using insertion loss method), they can reflect RF power and produce oscillations which

eventually can result in driving the amplifier to instability.

High Pass filter: Again, due to the possible harmonics and IMD elements at high frequencies which can get

reflected by the bandpass filter resulting in oscillations and eventual instability, a high pass filter will

terminate all high frequency signals to matched load.

Figure 18. Full amplifier schematic with bias networks and filters

PORTP=2Z=50 OhmPORT

P=1Z=50 Ohm


RESID=R2R=R Ohm

DCVSID=V1V=3.3 V

CAPID=C1C=100 pF


CAPID=C2C=100 pF

DCVSID=V2V=3.3 V

MSUBEr=3H=508 umT=17 umRho=0.706Tand=0.0009ErNom=12.9Name=SUB1


RESID=R1R=R Ohm



1

2


1 2

SUBCKTID=S5NET="HPF"

1

2


1 2

SUBCKTID=S4NET="Final Filter"

1 2

SUBCKTID=S3NET="LPF"

CAPID=C9C=100 pF


CAPID=C5C=100 pF



DCVSID=V4V=3.3 V

RESID=R3R=50 Ohm

CAPID=C3C=100 pF

CAPID=C4C=100 pF


DCVSID=V3V=3.3 V

CAPID=C6C=100 pF

CAPID=C8C=100 pF




RESID=R4R=50 Ohm



CAPID=C7C=100 pF

MLINID=TL17W=w umL=2151 umMSUB=SUB1

ie=957.8

oe=1415

ih=2451

w=1259.26

R=700

oh=1777

19

Compliance Matrix:

The final performance metric is shown here:

Figure 19. Performance analysis of the amplifier

PARAMETER DESIGN GOAL RESULT COMPLIANT?

Center Frequency (GHz) 10 10 YES

Bandwidth B3dB (GHz) 3<B3dB<4 3.145 YES

Bandwidth B20dB (GHz) 4<B20dB<6 5.282 YES

Noise Figure (dB) <2 1.793 YES

Gain at Center Frequency (dB) >18 18.91 YES

Gain outside B20dB (dB) <-3 <-3 YES

Output Return Loss (dB) >10 19.91 YES

Stability Unconditional Unconditional YES

Vcc (Volts) 3.3 3.3 YES

20

f. Conclusion

The primary function of the LNA is to reduce the overall Noise Figure of the system. For this reason, the

noise figure circles were plotted for the first transistor to locate 𝑁𝐹𝑚𝑖𝑛 at the design frequency, 10 GHz,

and the input source reflection coefficient (Γ𝑠,𝑜𝑝𝑡) is chosen to be at 𝑁𝐹𝑚𝑖𝑛 .Matching network was

designed at the input stage to match source impedance of 50Ω to the impedance corresponding toΓ𝑠,𝑜𝑝𝑡.

Similar procedure was followed at the intermediate stage so as to minimize the Noise Figure at the second

transistor by matching the output impedance at first stage to Γ𝑠,𝑜𝑝𝑡 at the second stage. The matching at

the input and the intermediate stages ensure that the minimum achievable Noise Figure is attained at the

end of 2 stages of transistor. At this point, matching must be done to achieve maximum power transfer

to the load. Therefore, the output reflection coefficient (Γ𝑜𝑢𝑡2) after 2 stages is matched to output

impedance, 50 Ω.

Since the Noise Figure and Gain requirement of the LNA can be achieved by adding appropriate

matching networks and tuning, bandwidth, however, is a different challenge. The bandwidth requirement

can be directly translated in to a Q requirement. Q factor is the ratio of the center frequency to the

bandwidth. Since AWR has the provision of Q contours on the smith chart, desired Q can be obtained by

adding matching networks in such a way that the path taken during matching (in a smith chart) touches

the Q contour at the final stage. However, with the Q contour, there is one more parameter added to the

trade-off list (apart from Noise Figure, Gain and Output return loss).

References

1. Microwave Transistor Amplifier Analysis and Design – By Guillermo Gonzalez

21

Appendix

The filter was designed using iFilter wizard of AWR, and the following are the circuits. They have been

included as sub-circuits in the original amplifier circuits.

1. Low Pass Filter

Distributed Stub, Microstrip filter, Degree = 8, Cutoff frequency = 4.5 GHz

2. High Pass filter

Optimum Distributed high pass filter, Microstrip, Degree = 11, Cutoff frequency = 11 GHz

L_v1=2987.54

Wg_v1=137.234

Ro_v2=4600.52L_v3=5772.6

Ro_v3=4362.11L_v5=3542.63Ro_v4=2734.23L_v6=1266.29

L_v4=7513.5

L_v2=1189.98

Theta_v1=59.9999999W_v1=1266.29

W_v2=274.469

Ro_v1=3830.69

Degree= 8

Fp= 4500 MHz

Microstrip LPF

Maximally Flat

Distributed Stubs Filter

Line Zo= 50

MDRSTUB2ID=ST2Ro=Ro_v2 umWg=Wg_v1 umW=W_v2 umTheta=Theta_v1 DegMLIN

ID=TL1W=W_v1 umL=L_v1 um

MDRSTUB2ID=ST3Ro=Ro_v3 umWg=Wg_v1 umW=W_v2 umTheta=Theta_v1 Deg MLIN

ID=TL5W=W_v1 umL=L_v1 um

MLINID=TL3W=W_v2 umL=L_v3 um

MSUBEr=3H=508 umT=17 umRho=1Tand=0.0009ErNom=3Name=SUB1

MDRSTUB2ID=ST1Ro=Ro_v1 umWg=Wg_v1 umW=W_v2 umTheta=Theta_v1 Deg

MTRACE2ID=X1W=W_v2 umL=L_v4 umBType=2M=1



MDRSTUB2ID=ST4Ro=Ro_v4 umWg=Wg_v1 umW=W_v2 umTheta=Theta_v1 Deg

MTAPERID=MT1W1=W_v1 umW2=W_v2 umL=L_v6 umTaper=LinearMethod=Default

PORTP=2Z=50 Ohm

PORTP=1Z=50 Ohm

L_v3=1865.62W_v3=1198.26

L_v7=1927.88

W_v4=892.675L_v4=1887.42

L_v2=1917.66

W_v7=494.952

L_v5=1908.11

W_v1=1266.29

D_v1=110.759

L_v6=1921.64

L_v1=1861.47

T_v1=44.303

W_v2=147.679

W_v6=545.252

W_v5=666.833

H_v1=508

Optimum Distributed Highpass Filter

Microstrip HPF

Degree= 11

Chebyshev

Fp= 13000 MHz

EL= 45 deg

1 2

3

MTEEX$ID=MT1



MVIA1PID=V1D=D_v1 umH=H_v1 umT=T_v1 umW=W_v2 umRHO=1




1 2

3

MTEEX$ID=MT3

1 2

3

MTEEX$ID=MT4


1 2

3

MTEEX$ID=MT2




1 2

3

MTEEX$ID=MT5








1 2

3

MTEEX$ID=MT9






1 2

3

MTEEX$ID=MT10


1 2

3

MTEEX$ID=MT6






1 2

3

MTEEX$ID=MT7

1 2

3

MTEEX$ID=MT8







1 2

3

MTEEX$ID=MT11


PORTP=2Z=50 Ohm

PORTP=1Z=50 Ohm

22

3. Bandpass filter

Edge coupled filter, microstrip, degree = 3, 𝑓𝑜 = 10 𝐺𝐻𝑧, BW = 5 GHz

PORTP=2Z=50 Ohm

PORTP=1Z=50 Ohm

MOPENXID=MO1W=W2_v1 um

MOPENXID=MO2W=W2_v1 umMSTEPXID=MS2W1=W2_v1 umW2=W2_v2 umOffset=-136 um

W1

W2

1

2

3

4

M2CLINID=TL3W1=W2_v2 umW2=W2_v2 umS=S_v2 umL=L_v3 umAcc=1


MSTEPXID=MS1W1=W_v1 umW2=W2_v1 umOffset=-398 um

W1

W2

1

2

3

4


L_v3=4844.7

L_v1=2419.91

S_v1=70.182W2_v1=468.926

W2_v2=742.065

W_v1=1266.29

L_v2=4920.25

S_v2=85.651

Microstrip BPF

Degree= 3

Fo= 10000 MHz

BW= 5000 MHz

Maximally Flat

Reson Zo= 50

Edge Coupled Bandpass Filter



W1

W2

1

2

3

4



MOPENXID=MO3W=W2_v2 um MSTEPX

ID=MS4W1=W2_v1 umW2=W_v1 umOffset=-398 um


MSTEPXID=MS3W1=W2_v2 umW2=W2_v1 umOffset=-136 um




W1

W2

1

2

3

4


design of 10 ghz two stage rf low noise amplifier1 design of 10 ghz two stage rf low noise amplifier...

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